CN118866943B - Super junction MOS device with improved avalanche tolerance and preparation method and chip - Google Patents
Super junction MOS device with improved avalanche tolerance and preparation method and chip Download PDFInfo
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Abstract
本申请属于功率器件技术领域，提供了一种改善雪崩耐量的超结MOS器件及制备方法、芯片，通过在第三N柱上设置栅极介质层、栅极多晶硅层，并在第三N柱与第二P柱之间设置掺杂浓度较高的第一N柱，在第三N柱与第三P柱之间设置掺杂浓度较高的第二N柱，在第一P柱与第一N柱之间设置较高掺杂浓度的第二P柱，在第二N柱与第四P柱之间设置较高掺杂浓度的第三P柱，使得器件内的电场更加均匀，器件在击穿时，器件内的电流分布可以更加均匀，提升了器件的击穿电压和雪崩耐量。
The present application belongs to the technical field of power devices, and provides a super junction MOS device with improved avalanche tolerance, a preparation method, and a chip. By arranging a gate dielectric layer and a gate polysilicon layer on a third N column, arranging a first N column with a higher doping concentration between the third N column and the second P column, arranging a second N column with a higher doping concentration between the third N column and the third P column, arranging a second P column with a higher doping concentration between the first P column and the first N column, and arranging a third P column with a higher doping concentration between the second N column and the fourth P column, the electric field in the device is more uniform, and when the device breaks down, the current distribution in the device can be more uniform, thereby improving the breakdown voltage and avalanche tolerance of the device.
Description
Technical Field
The application belongs to the technical field of power devices, and particularly relates to a super-junction MOS device for improving avalanche resistance, a preparation method and a chip.
Background
The super junction MOS device breaks the silicon limit relation between the on voltage and the resistance of the conventional power MOSFET, has lower switching loss, and is widely applied to the fields of automobile electronics, consumer electronics, power supply, aerospace and the like. In the current research trend, the relationship between the specific on-resistance and the breakdown voltage of the super junction MOS device is continuously optimized, and it is generally expected that a higher breakdown voltage can be achieved under the same specific on-resistance.
Disclosure of Invention
In order to solve the technical problems, the embodiment of the application provides a super-junction MOS device for improving avalanche resistance, a preparation method and a chip thereof, and aims to improve the breakdown voltage and avalanche resistance of the existing super-junction MOS device.
A first aspect of an embodiment of the present application provides a superjunction MOS device for improving avalanche resistance, including:
An N-type substrate;
The first N column, the second N column and the third N column are arranged on the N-type substrate, and the third N column is arranged between the first N column and the second N column, wherein the doping concentration of the first N column and the second N column is larger than that of the third N column;
The first P column, the second P column, the third P column and the fourth P column are arranged on the N-type substrate, the second P column is arranged between the first P column and the first N column, the third P column is arranged between the second N column and the fourth P column, the doping concentration of the second P column is larger than that of the first P column, and the doping concentration of the third P column is larger than that of the fourth P column;
The first P-type base region is formed on the first P column, the second P column and the first N column;
the second P-type base region is formed on the third P column, the fourth P column and the second N column;
The gate dielectric layer is formed on the third N column and is positioned between the first P-type base region and the second P-type base region, and the gate polysilicon layer is wrapped by the gate dielectric layer;
the first P-type source region and the first N-type source region are formed on the first P-type base region;
The second P-type source region and the second N-type source region are formed on the second P-type base region;
The source electrode layer is in contact with the first P-type source region, the first N-type source region, the second P-type source region and the second N-type source region;
A gate layer in contact with the gate polysilicon layer;
And the drain electrode layer is formed on the back surface of the N-type substrate.
In some embodiments, N-type doped point regions are disposed in the first P-pillar and the fourth P-pillar.
In some embodiments, the superjunction MOS device further comprises:
the first transverse P column is arranged between the first P-type base region and the first P column and between the first P-type base region and the second P-type base region.
In some embodiments, the superjunction MOS device further comprises:
And the second transverse P column is arranged between the second P-type base region and the third P column and the fourth P column.
In some embodiments, the width of the first P-pillar is greater than the width of the second P-pillar, and/or
The width of the fourth P column is larger than the width of the third P column.
In some embodiments, the width of the third N-pillar is greater than the width of the first N-pillar and the second N-pillar.
In some embodiments, the third N-pillar has a width that is the same as a width of the gate dielectric layer.
In some embodiments, the second P-pillars have the same width as the first N-pillars, and/or,
The width of the third P column is the same as the width of the second N column.
The second aspect of the embodiment of the application also provides a preparation method of the super junction MOS device for improving avalanche resistance, which comprises the following steps:
an N-type drift region is epitaxially generated on the front surface of an N-type substrate, and after a groove is etched in a partial region of the N-type drift region, a P-type material is filled to form a third N column, a first P column and a fourth P column;
Etching grooves for multiple times on partial areas of the first P column and the fourth P column, and filling P-type materials and N-type materials to form a first N column, a second P column and a third P column, wherein the third N column is arranged between the first N column and the second N column, the second P column is arranged between the first P column and the first N column, the third P column is arranged between the second N column and the fourth P column, the doping concentration of the first N column and the second N column is larger than that of the third N column, the doping concentration of the second P column is larger than that of the first P column, and the doping concentration of the third P column is larger than that of the fourth P column;
Continuing to extend the N-type epitaxial material, performing an ion implantation process, forming a first P-type base region on the first P column, the second P column and the first N column, and forming a second P-type base region on the third P column, the fourth P column and the second N column;
sequentially injecting N-type doping ions and P-type doping ions into the first P-type base region and the second P-type base region to form a first P-type source region and a first N-type source region on the first P-type base region, and forming a second P-type source region and a second N-type source region on the second P-type base region;
Etching a groove between the first P-type base region and the second P-type base region, forming a gate dielectric layer and a gate polysilicon layer, wherein the gate dielectric layer is formed on the third N column and is positioned between the first P-type base region and the second P-type base region;
And forming a source electrode layer contacted with the first P type source region, the first N type source region, the second P type source region and the second N type source region, a gate electrode layer contacted with the gate polysilicon layer and a drain electrode layer contacted with the back surface of the N type substrate.
The third aspect of the embodiment of the present application further provides a chip, which includes the superjunction MOS device according to any one of the embodiments.
The embodiment of the application has the beneficial effects that the gate dielectric layer and the gate polysilicon layer are arranged on the third N column, the first N column with higher doping concentration is arranged between the third N column and the second P column, the second N column with higher doping concentration is arranged between the third N column and the third P column, the second P column with higher doping concentration is arranged between the first P column and the first N column, and the third P column with higher doping concentration is arranged between the second N column and the fourth P column, so that the electric field in the device is more uniform, the current distribution in the device can be more uniform when the device breaks down, and the breakdown voltage and avalanche tolerance of the device are improved.
Drawings
Fig. 1a is a schematic structural diagram of a super junction MOS device according to an embodiment of the present application;
Fig. 1b is a schematic structural diagram of a super junction MOS device according to an embodiment of the present application;
fig. 1c is a schematic structural diagram III of a super junction MOS device according to an embodiment of the present application;
fig. 1d is a schematic structural diagram of a super junction MOS device according to an embodiment of the present application;
Fig. 2a is a diagram of simulation results of breakdown voltages of a conventional superjunction MOSFET and a superjunction MOS device in an embodiment of the present application;
FIG. 2b is a graph of simulation results of output characteristics of a conventional super-junction MOSFET and a super-junction MOS device in an embodiment of the present application;
FIG. 2c is a graph of simulation results of transfer characteristic curves of a conventional super junction MOSFET and a super junction MOS device in an embodiment of the present application;
FIG. 2d is a graph of simulation results of reverse recovery characteristics of a conventional super junction MOSFET and a super junction MOS device in an embodiment of the present application;
FIG. 3a is a graph of current density simulation results for a conventional superjunction MOSFET device;
FIG. 3b is a graph of current density simulation results of the super junction MOS device shown in FIG. 1a in an embodiment of the present application;
fig. 4 is a diagram showing simulation results of electric field distribution of a conventional planar superjunction MOSFET and a superjunction MOS device according to an embodiment of the present application;
fig. 5a is a schematic diagram illustrating a relationship between a breakdown voltage and a doping concentration of an N column of a super junction MOS device according to an embodiment of the present application;
fig. 5b is a schematic diagram illustrating a relationship between an output characteristic curve of a super junction MOS device and a doping concentration of an N column in an embodiment of the present application;
Fig. 5c is a schematic diagram of the relationship between the output characteristic curve of the superjunction MOS device and the distances between the N pillar and the P pillar in the application embodiment;
Fig. 5d is a schematic diagram showing a relationship between an output characteristic curve of a superjunction MOS device and a concentration of an N-type doped point region in an embodiment of the present application;
fig. 6 is a schematic flow chart of a method for manufacturing a superjunction MOS device according to an embodiment of the present application;
fig. 7 is a schematic diagram of forming an N-type drift region on a front surface of an N-type substrate according to an embodiment of the present application;
FIG. 8 is a schematic diagram of forming a third N column, a first P column, and a fourth P column on the front surface of an N-type substrate according to an embodiment of the present application;
FIG. 9a is a schematic diagram of forming a first N pillar, a second P pillar, and a third P pillar on a front surface of an N-type substrate according to an embodiment of the present application;
FIG. 9b is a schematic diagram of forming N-type doped point regions in a first P column and a fourth P column according to an embodiment of the present application;
FIG. 10 is a schematic diagram of forming a first P-type base region, a second P-type base region, a first P-type source region, a second P-type source region, a first N-type source region, and a second N-type source region according to an embodiment of the present application;
Fig. 11 is a schematic diagram of forming a gate dielectric layer and a gate polysilicon layer in an embodiment of the application.
Detailed Description
In order to make the technical problems, technical schemes and beneficial effects to be solved more clear, the application is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application.
It will be understood that when an element is referred to as being "mounted" or "disposed" on another element, it can be directly on the other element or be indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or be indirectly connected to the other element.
It is to be understood that the terms "length," "width," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are merely for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus are not to be construed as limiting the application.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, the meaning of "a plurality" is one or more than one unless specifically defined otherwise.
When the super junction MOS device is in reverse conduction, the body diode is used for carrying out minority charge injection, the reverse recovery peak current is large, the reverse recovery performance is poor, and the super junction MOS device is limited to be applied to a system with higher frequency.
In order to solve the above technical problems, the embodiment of the present application provides a superjunction MOS device for improving avalanche tolerance, as shown in fig. 1a, where the superjunction MOS device in this embodiment includes an N-type substrate 110, a first N-pillar 121, a second N-pillar 122, a third N-pillar 120, a first P-pillar 131, a second P-pillar 133, a third P-pillar 134, a fourth P-pillar 132, a first P-type base region 141, a second P-type base region 142, a gate dielectric layer 171, a gate polysilicon layer 172, a first P-type source region 151, a first N-type source region 161, a second P-type source region 152, a second N-type source region 162, a source layer 173, a gate layer 174, and a drain layer 180.
The first N-pillar 121, the second N-pillar 122, and the third N-pillar 120 are disposed on the N-type substrate 110, and the third N-pillar 120 is disposed between the first N-pillar 121 and the second N-pillar 122, wherein a doping concentration of the first N-pillar 121 and the second N-pillar 122 is greater than a doping concentration of the third N-pillar 120. The first P-pillar 131, the second P-pillar 133, the third P-pillar 134 and the fourth P-pillar 132 are disposed on the N-type substrate 110, the second P-pillar 133 is disposed between the first P-pillar 131 and the first N-pillar 121, the third P-pillar 134 is disposed between the second N-pillar 122 and the fourth P-pillar 132, the doping concentration of the second P-pillar 133 is greater than the doping concentration of the first P-pillar 131, and the doping concentration of the third P-pillar 134 is greater than the doping concentration of the fourth P-pillar 132. A first P-type base region 141 is formed on the first P-pillar 131, the second P-pillar 133, and the first N-pillar 121, and a second P-type base region 142 is formed on the third P-pillar 134, the fourth P-pillar 132, and the second N-pillar 122. A gate dielectric layer 171 is formed on the third N-pillar 120 and is located between the first P-type base region 141 and the second P-type base region 142, wherein a gate polysilicon layer 172 is surrounded by the gate dielectric layer 171. The first P-type source region 151 and the first N-type source region 161 are formed on the first P-type base region 141, the second P-type source region 152 and the second N-type source region 162 are formed on the second P-type base region 142, the source layer 173 is in contact with the first P-type source region 151, the first N-type source region 161, the second P-type source region 152 and the second N-type source region 162, the gate layer 174 is in contact with the gate polysilicon layer 172, and the drain layer 180 is formed on the back surface of the N-type substrate 110.
In this embodiment, by disposing the gate dielectric layer 171 and the gate polysilicon layer 172 on the third N pillar 120, disposing the first N pillar 121 with higher doping concentration between the third N pillar 120 and the second P pillar 133, disposing the second N pillar 122 with higher doping concentration between the third N pillar 120 and the third P pillar 134, disposing the second P pillar 133 with higher doping concentration between the first P pillar 131 and the first N pillar 121, and disposing the third P pillar 134 with higher doping concentration between the second N pillar 122 and the fourth P pillar 132, the electric field in the device is more uniform, the current distribution in the device can be more uniform when the device breaks down, and the breakdown voltage and avalanche tolerance of the device are improved.
As shown in connection with fig. 1b, in some embodiments, N-type doped point regions (N-dots) may be provided within the first P-pillar 131 and the fourth P-pillar 132.
In this embodiment, the first N-type doped point region 123 is disposed in the first P column 131, the second N-type doped point region 124 is disposed in the fourth P column 132, and this design can change the resistances of the first P column 131 and the fourth P column 132, thereby affecting the extraction speed of holes in the device, improving the softness of reverse recovery of the device, reducing the reverse recovery time and reverse recovery charge of the device, so as to improve the reverse recovery performance of the device, and the design makes the electric field in the device more uniform, and the current distribution in the device can be more uniform when the device breaks down, thereby improving the breakdown voltage of the device.
In this embodiment of the present application, the first N-doped point region 123 may be located at an end of the first P-pillar 131 near the first P-base region 141 and is not in contact with the first P-base region 141. The second N-doped point region 124 may be located in the fourth P-pillar 132 near an end of the second P-base region 142 and not contact the second P-base region 142.
The static characteristics of the three structures of the conventional superjunction MOS device, the superjunction MOS device (without N-Dot) shown in fig. 1a provided by the embodiment of the present application, and the superjunction MOS device (with N-Dot) shown in fig. 1b provided by the embodiment of the present application, and the reverse recovery related parameters thereof are compared in table 1 below.
Wherein V （BR）DSS in table 1 is drain-source breakdown voltage, R DS(ON) is on-resistance, I D is source-drain saturation current, V th is threshold voltage, t rr is body diode reverse recovery time, Q rr is body diode reverse recovery charge, I RRM reverse recovery current, V GS (i.e., V gs) is turn-on voltage, I DS (i.e., I ds) is drain current, VDD is supply voltage, di/dt is current.
Table 1:
In addition, as shown in fig. 2a, 2b, 2c and 2d, the lower the reverse peak current of the superjunction MOS device, the lower the reverse recovery time, and the better the reverse recovery characteristic. Fig. 2a, fig. 2b, fig. 2c, fig. 2d, and fig. 4 are graphs of simulation results of conventional superjunction MOSFET devices, fig. 2 is a graph of simulation results of the superjunction MOS device (without N-Dot) shown in fig. 1a provided by the embodiment of the present application, and fig. 3 is a graph of simulation results of the superjunction MOS device (with N-Dot) shown in fig. 1b provided by the embodiment of the present application. The superjunction MOS device shown in fig. 1a does not include N-Dot (first N-type doped Dot region 123, second N-type doped Dot region 124). In the embodiments of the present application, in fig. 2a to 5d, id is drain current, vds is the voltage between drain and source, and Ids is the current between drain and source.
Referring to tables 1, 2a, 2b, 2c, 2d, 3a and 3b, the on-resistance, the saturation current and the threshold voltage of the three devices are substantially the same, and the gate dielectric layer 171 and the gate polysilicon layer 172 are disposed on the third N-pillar 120, the first N-pillar 121 with higher doping concentration is disposed between the third N-pillar 120 and the second P-pillar 133, the second N-pillar 122 with higher doping concentration is disposed between the third N-pillar 120 and the third P-pillar 134, the second P-pillar 133 with higher doping concentration is disposed between the first P-pillar 131 and the first P-pillar 121, and the third P-pillar 134 with higher doping concentration is disposed between the second N-pillar 122 and the fourth P-pillar 132, so that the current distribution is more uniform when the device breaks down, the breakdown voltage of the device is improved by improving the current distribution, and the avalanche tolerance of the device is improved. Where X in fig. 3a and 3b represents the depth coordinate of the device and Y represents the width coordinate of the device.
As can be seen from fig. 4, by disposing the first N-type doped point region 123 in the first P column 131 and disposing the second N-type doped point region 124 in the fourth P column 132, the resistances of the first P column 131 and the fourth P column 132 are changed, so as to affect the extraction speed of holes in the device, improve the softness of reverse recovery of the device, and make the electric field in the device more uniform, and when the device breaks down, the current distribution in the device can be more uniform, thereby improving the breakdown voltage of the device. In fig. 4, curve 1 is a simulation result diagram of a conventional superjunction MOSFET device, curve 2 is a simulation result diagram of a superjunction MOS device (without N-Dot) shown in fig. 1a provided by an embodiment of the present application, and curve 2 is a simulation result diagram of a superjunction MOS device (with N-Dot) shown in fig. 1b provided by an embodiment of the present application. Wherein the abscissa X in fig. 4 represents the depth coordinate of the device.
In the case of keeping the overall charge of the device structure shown in fig. 1a the same as that of the conventional superjunction MOS device structure, as shown in fig. 5a, the doping concentrations of the second P pillar 133, the first N pillar 121, the third P pillar 134, and the second N pillar 122 are increased, the breakdown voltage gradually increases when the concentration is less than 1.8e16 cm -3, and the breakdown voltage significantly decreases when the concentration exceeds 1.8e16 cm -3. As shown in connection with fig. 5b, when the concentration is greater than 1.2e16 cm -3, the forward on-resistance increases significantly.
As shown in fig. 5c, in the case where the overall charge of the device structure shown in fig. 1a is kept the same as that of the conventional superjunction MOS device structure, the breakdown voltage of the device is lower as the distance between the third N-pillar 120 and the first P-pillar 131 (i.e., the sum of the widths of the second P-pillar 133 and the first P-pillar 121) and the distance between the third N-pillar 120 and the fourth P-pillar 132 (i.e., the sum of the widths of the third P-pillar 134 and the second N-pillar 122) are changed, the breakdown voltage of the device is substantially unaffected by the distance between the third N-pillar 120 and the first P-pillar 131 and the distance between the third N-pillar 120 and the fourth P-pillar 132 when the distance between the third N-pillar 120 and the first P-pillar 131 is greater.
In some embodiments, the doping concentrations of the first N-pillar 121 and the second N-pillar 122 may be the same.
In some embodiments, the doping concentration of the first N-pillar 121 and the second N-pillar 122 may be 7.2e15 cm -3.
In some embodiments, the doping concentrations of the second P-pillar 133 and the third P-pillar 134 may be the same.
In some embodiments, the doping concentrations of the second P-pillar 133 and the third P-pillar 134 are the same as the doping concentrations of the first N-pillar 121 and the second N-pillar 122.
In some embodiments, the doping concentration of the second P-pillar 133 and the third P-pillar 134 may be 7.2e15 cm -3.
In some embodiments, the doping concentration of the third N-pillar 120 may be 5.4e15 cm -3.
In some embodiments, the doping concentration of the first P-pillar 131 and the fourth P-pillar 132 may be 5.4e15 cm -3.
In some embodiments, the doping concentration of the first N-type doped point region 123, the second N-type doped point region 124 may be 9e15 cm -3.
In some embodiments, the distance between the first N-type doped point region 123 and the first N-type source region 161 is 5um, and the distance between the second N-type doped point region 124 and the second N-type source region 162 is 5um.
In some embodiments, as shown in connection with fig. 1c, the superjunction MOS device further includes a first lateral P-pillar 213, the first lateral P-pillar 213 being disposed between the first P-type base region 141 and the first P-pillar 131, and between the first P-type base region 141 and the second P-pillar 133.
In this embodiment, one end of the first lateral P-pillar 213 contacts one end of the second P-pillar 133, and the other end of the second P-pillar 133 contacts the N-type substrate 110, which can adjust the charge balance above the first N-pillar 121 (in the direction close to the source), while reducing some hole injection, and improving the reverse recovery characteristics of the device.
In some embodiments, as shown in connection with fig. 1c, the superjunction MOS device further includes a second lateral P-pillar 214, the second lateral P-pillar 214 being disposed between the second P-type base region 142 and the third P-pillar 134, and between the second P-type base region 142 and the fourth P-pillar 132.
In this embodiment, one end of the second lateral P-pillar 214 contacts one end of the third P-pillar 134, and the other end of the third P-pillar 134 contacts the N-type substrate 110, which can adjust the charge balance above the second N-pillar 122 (in the direction close to the source), while reducing some hole injection, and improving the reverse recovery characteristics of the device.
In some embodiments, the width of the first P-pillars 131 is greater than the width of the second P-pillars 133.
In some embodiments, the width of the fourth P-pillar 132 is greater than the width of the third P-pillar 134.
In some embodiments, as shown in fig. 1c, a first N-type doped region 211 is disposed between the first lateral P-pillar 213 and the gate dielectric layer 171, and a second N-type doped region 212 is disposed between the second lateral P-pillar 214 and the gate dielectric layer 171.
In this embodiment, by providing the first N-type doped region 211 and the second N-type doped region 212, the charge in the contact region between the first N-type doped region 211 and the second N-type doped region 212 can be balanced, and the minority carrier lifetime can be reduced, thereby improving the reverse recovery charge.
In some embodiments, the doping concentration of the first N-type doped region 211 is greater than the doping concentration of the first N-pillar 121, and the doping concentration of the second N-type doped region 212 is greater than the doping concentration of the second N-pillar 122, thereby reducing minority carrier lifetime and improving reverse recovery charge of the device.
In some embodiments, the width of the third N-pillar 120 is greater than the width of the first N-pillar 121 and the second N-pillar 122.
In some embodiments, the width of the third N-pillar 120 is the same as the width of the gate dielectric layer 171.
In some embodiments, the width of the second P pillars 133 is the same as the width of the first N pillars 121.
In some embodiments, the width of the third P-pillars 134 is the same as the width of the second N-pillars 122.
In this embodiment, the doping concentrations of the second P pillar 133 and the first N pillar 121 between the first P pillar 131 and the third N pillar 120 are higher, the doping concentrations of the second N pillar 122 and the third P pillar 134 between the third N pillar 120 and the fourth P pillar 132 are higher, so that the first P pillar 131 and the third N pillar 120 are highly doped, the third N pillar 120 and the fourth P pillar 132 are highly doped, and the width of the second P pillar 133 is the same as the width of the first N pillar 121, and the width of the third P pillar 134 is the same as the width of the second N pillar 122.
In some embodiments, the concentration of N-type dopant ions in the first N-pillar 121 and the second N-pillar 122 is at least 100 times the doping concentration of N-type dopant ions in the third N-pillar 120.
In some embodiments, the concentration of the P-type dopant ions in the second P-pillar 133 is at least 100 times that in the first P-pillar 131.
In some embodiments, the concentration of P-type dopant ions in the third P-pillar 134 is at least 100 times the doping concentration of P-type dopant ions in the fourth P-pillar 132.
In some embodiments, since the front surface of the N-type substrate 110 has a larger thickness in the N-type drift region, a higher concentration of N-type dopant ions is implanted into the N-type drift region on a side far from the N-type substrate 110 during ion implantation, so, in order to equalize the electric field in the N-type drift region, the doping concentrations of N-type dopant ions in the first N-pillar 121 and the second N-pillar 122 gradually increase in the direction from the N-type substrate 110 to the P-type base region, and similarly, the concentrations of P-type dopant ions in the second P-pillar 133 and the third P-pillar 134 gradually increase in the direction from the N-type substrate 110 to the P-type base region.
In some embodiments, as shown in fig. 1d, a plurality of first N-type doped point regions 123 are disposed in the first P column 131, a plurality of second N-type doped point regions 124 are disposed in the fourth P column 132, the plurality of first N-type doped point regions 123 are disposed in parallel and spaced apart, the closer to the second P column 133, the smaller the spacing between adjacent first N-type doped point regions 123, the plurality of second N-type doped point regions 124 are disposed in parallel and spaced apart, and the closer to the third P column 134, the smaller the spacing between adjacent second N-type doped point regions 124.
In this embodiment, the current distribution between the N-type substrate 110 and the first P-type base region 141 can be adjusted by the plurality of first N-type doped point regions 123, and the current distribution between the N-type substrate 110 and the second P-type base region 142 can be adjusted by the plurality of second N-type doped point regions 124, so that the resistances of the first P-pillar 131 and the fourth P-pillar 132 can be adjusted, thereby balancing the extraction speed of holes in the device, improving the softness of reverse recovery of the device, and making the electric field in the device more uniform, and the current distribution in the device can be more uniform when the device breaks down.
Referring to fig. 5d, the positions of the first N-type doped point region 123 and the second N-type doped point region 124 have substantially no influence on the output characteristics of the device. The first N-type doped region 123 and the second N-type doped region 124 can improve the breakdown voltage to a certain extent when they are closer to the source and deteriorate the breakdown voltage to a certain extent when they are closer to the drain, but have a smaller overall influence. In addition, the concentrations of the first N-type doped point region 123 and the second N-type doped point region 124 have substantially no effect on the output characteristics of the device. When the doping concentration of the first N-type doped point region 123 and the second N-type doped point region 124 is greater than 1.2e16cm -3, the breakdown voltage of the device is significantly reduced.
The embodiment of the application also provides a preparation method of the super junction MOS device for improving avalanche resistance, which is shown in fig. 6, and comprises steps S100 to S600.
In step S100, an N-type drift region 120 'is epitaxially formed on the front surface of the N-type substrate 110, and after etching a trench in a partial region of the N-type drift region 120', a P-type material is filled to form a third N-pillar 120, a first P-pillar 131, and a fourth P-pillar 132.
As shown in fig. 7 and 8, the first P column 131 and the fourth P column 132 are located at both sides of the third N column 120, respectively. And, the widths of the first P pillar 131 and the fourth P pillar 132 are smaller than the width of the third N pillar 120. The first P-pillar 131, the fourth P-pillar 132, and the third N-pillar 120 are in contact with the N-type substrate 110.
In step S200, trenches are etched multiple times on the partial regions of the first and fourth P-pillars 131 and 132, and the P-type material and the N-type material are filled to form the first, second, and third P-pillars 121, 122, 133, and 134.
Referring to fig. 9a, in the present embodiment, the third N-pillar 120 is disposed between the first N-pillar 121 and the second N-pillar 122, the second P-pillar 133 is disposed between the first P-pillar 131 and the first N-pillar 121, the third P-pillar 134 is disposed between the second N-pillar 122 and the fourth P-pillar 132, and the doping concentrations of the first N-pillar 121 and the second N-pillar 122 are greater than the doping concentration of the third N-pillar 120. The doping concentration of the second P-pillar 133 is greater than the doping concentration of the first P-pillar 131, and the doping concentration of the third P-pillar 134 is greater than the doping concentration of the fourth P-pillar 132.
In an embodiment, in conjunction with fig. 9b, in the step S200, N-type doped point regions may also be formed in the first P-pillar 131 and the fourth P-pillar 132 by etching trenches, ion filling, and the like.
In this embodiment, as shown in fig. 1b, a first N-type doped point region 123 is disposed in the first P column 131, and a second N-type doped point region 124 is disposed in the fourth P column 132, so that the design can change the resistances of the first P column 131 and the fourth P column 132, thereby affecting the extraction speed of holes in the device, improving the softness of reverse recovery of the device, and making the electric field in the device more uniform, and the current distribution in the device can be more uniform when the device breaks down.
In some embodiments, as shown in fig. 1d, a plurality of first N-doped dot regions 123 may be further disposed in the first P column 131, a plurality of second N-doped dot regions 124 may be disposed in the fourth P column 132, the plurality of first N-doped dot regions 123 may be disposed in parallel and spaced apart, the closer to the second P column 133, the smaller the spacing between the adjacent first N-doped dot regions 123, the plurality of second N-doped dot regions 124 may be disposed in parallel and spaced apart, the closer to the third P column 134, and the smaller the spacing between the adjacent second N-doped dot regions 124.
In this embodiment, the current distribution between the N-type substrate 110 and the first P-type base region 141 can be adjusted by the plurality of first N-type doped point regions 123, and the current distribution between the N-type substrate 110 and the second P-type base region 142 can be adjusted by the plurality of second N-type doped point regions 124, so that the resistances of the first P-pillar 131 and the fourth P-pillar 132 can be adjusted, thereby balancing the extraction speed of holes in the device, improving the softness of reverse recovery of the device, and making the electric field in the device more uniform, and the current distribution in the device can be more uniform when the device breaks down.
In step S300, the N-type epitaxial material is continued to be epitaxially grown, and an ion implantation process is performed to form a first P-type base region 141 on the first P-pillar 131, the second P-pillar 133, and the first N-pillar 121, and a second P-type base region 142 on the third P-pillar 134, the fourth P-pillar 132, and the second N-pillar 122.
In step S400, N-type doping ions and P-type doping ions are sequentially implanted into the first P-type base region 141 and the second P-type base region 142 to form a first P-type source region 151 and a first N-type source region 161 on the first P-type base region 141, and a second P-type source region 152 and a second N-type source region 162 on the second P-type base region 142;
Referring to fig. 10, in some embodiments, the thickness of the first P-type base region 141 is greater than the thicknesses of the first P-type source region 151 and the first N-type source region 161, and the thicknesses of the first P-type source region 151 and the first N-type source region 161 are the same. The thickness of the second P-type base region 142 is greater than the thicknesses of the second P-type source region 152 and the second N-type source region 162, and the thicknesses of the second P-type source region 152 and the second N-type source region 162 are the same.
In some embodiments, the first P-type source region 151 and the first N-type source region 161 have the same width, and the second P-type source region 152 and the second N-type source region 162 have the same width.
In step S500, a trench is etched between the first P-type base region 141 and the second P-type base region 142, and a gate dielectric layer 171 and a gate polysilicon layer 172 are formed, and the gate dielectric layer 171 is formed on the third N pillar 120 and between the first P-type base region 141 and the second P-type base region 142.
In this embodiment, the gate polysilicon layer 172 is surrounded by the gate dielectric layer 171.
Referring to fig. 11, in one embodiment, the gate dielectric layer 171 is located between the first N-pillar 121 and the second N-pillar 122 and contacts the first N-pillar 121 and the second N-pillar 122, and the third N-pillar 120 has a depth smaller than the first N-pillar 121 and the second N-pillar 122, and the first N-pillar 121 and the second N-pillar 122 have the same depth.
In step S600, a source layer 173 is formed in contact with the first P-type source region 151, the first N-type source region 161, the second P-type source region 152, and the second N-type source region 162, a gate layer 174 is formed in contact with the gate polysilicon layer 172, and a drain layer 180 is formed in contact with the back surface of the N-type substrate 110.
Referring to fig. 1a and 1b, the gate dielectric layer 171 has a concave structure, and the gate polysilicon layer 172 is filled in the concave structure of the gate dielectric layer 171 and contacts the gate layer 174.
In this embodiment, by disposing the gate dielectric layer 171 and the gate polysilicon layer 172 on the third N pillar 120, disposing the first N pillar 121 with higher doping concentration between the third N pillar 120 and the second P pillar 133, disposing the second N pillar 122 with higher doping concentration between the third N pillar 120 and the third P pillar 134, disposing the second P pillar 133 with higher doping concentration between the first P pillar 131 and the first N pillar 121, and disposing the third P pillar 134 with higher doping concentration between the second N pillar 122 and the fourth P pillar 132, the reverse peak current of the device is reduced, the reverse recovery time and the reverse recovery charge of the device are reduced, and the reverse recovery performance of the device is improved.
In one embodiment of the present application, as shown in fig. 1c, in step S300, before the first P-type base region and the second P-type base region are generated, the first lateral P-pillar 213 and the second lateral P-pillar 214 may be formed, such that the first lateral P-pillar 213 is disposed between the first P-type base region 141 and the first P-pillar 131, and between the first P-type base region 141 and the second P-pillar 133, and the second lateral P-pillar 214 is disposed between the second P-type base region 142 and the third P-pillar 134, and between the second P-type base region 142 and the fourth P-pillar 132. A first N-type doped region 211 is disposed between the first lateral P-pillar 213 and the gate dielectric layer 171, and a second N-type doped region 212 is disposed between the second lateral P-pillar 214 and the gate dielectric layer 171.
In this embodiment, one end of the first lateral P-pillar 213 contacts one end of the second P-pillar 133, and the other end of the second P-pillar 133 contacts the N-type substrate 110, which can adjust the charge balance above the first N-pillar 121 (in the direction close to the source), while reducing some hole injection, and improving the reverse recovery characteristics of the device. One end of the second lateral P-pillar 214 contacts one end of the third P-pillar 134 and the other end of the third P-pillar 134 contacts the N-type substrate 110, which can adjust the charge balance above the second N-pillar 122 (in the direction closer to the source), while reducing some hole injection, improving the reverse recovery characteristics of the device. By providing the first and second N-doped regions 211, 212, charge in the contact region of the first and second N-doped regions 211, 212 can be balanced and minority carrier lifetime reduced, improving reverse recovery charge.
The embodiment of the application also provides a chip comprising the super junction MOS device of any one of the embodiments.
In this embodiment, the chip includes a chip substrate, and one or more superjunction MOS devices are disposed on the substrate, where the superjunction MOS devices may be prepared by the preparation method in any of the foregoing embodiments, or the superjunction MOS devices in any of the foregoing embodiments may be disposed on the chip substrate.
In a specific application embodiment, other related semiconductor devices can be integrated on the chip substrate, and the semiconductor device and the super junction MOS device in any of the above embodiments form an integrated circuit.
In one specific application embodiment, the chip may be a switching chip or a driving chip.
The embodiment of the application has the beneficial effects that the gate dielectric layer 171 and the gate polysilicon layer 172 are arranged on the third N column 120, the first N column 121 with higher doping concentration is arranged between the third N column 120 and the second P column 133, the second N column 122 with higher doping concentration is arranged between the third N column 120 and the third P column 134, the second P column 133 with higher doping concentration is arranged between the first P column 131 and the first N column 121, and the third P column 134 with higher doping concentration is arranged between the second N column 122 and the fourth P column 132, so that the electric field in the device is more uniform, the current distribution in the device can be more uniform when the device breaks down, and the breakdown voltage and avalanche tolerance of the device are improved.
It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-described division of each doped region and device is illustrated, and in practical application, the above-described function allocation may be performed by different doped regions and devices according to needs, i.e. the internal structure of the device is divided into different doped regions, so as to perform all or part of the above-described functions. The doped regions and the devices in the embodiments can be integrated in one unit, or each unit can exist alone physically, or two or more units can be integrated in one unit.
In addition, the specific names of the doped regions and the devices are only used for distinguishing the doped regions and the devices from each other, and are not used for limiting the protection scope of the application.
In the foregoing embodiments, the descriptions of the embodiments are emphasized, and in part, not described or illustrated in any particular embodiment, reference is made to the related descriptions of other embodiments.
In addition, each doped region in the embodiments of the present application may be integrated in one unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The foregoing embodiments are merely for illustrating the technical solution of the present application, but not for limiting the same, and although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that the technical solution described in the foregoing embodiments may be modified or substituted for some of the technical features thereof, and that these modifications or substitutions should not depart from the spirit and scope of the technical solution of the embodiments of the present application and should be included in the protection scope of the present application.
Claims (10)
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| CN104241376A (en) * | 2014-09-01 | 2014-12-24 | 矽力杰半导体技术(杭州)有限公司 | Super junction structure, preparation method of super junction structure and semiconductor device |
| CN117423723A (en) * | 2023-11-29 | 2024-01-19 | 芯长征微电子制造(山东)有限公司 | Power device capable of improving avalanche tolerance of super junction structure and preparation method |
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| CN115566038A (en) * | 2021-07-01 | 2023-01-03 | 深圳尚阳通科技有限公司 | Super junction device and manufacturing method thereof |
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| CN104241376A (en) * | 2014-09-01 | 2014-12-24 | 矽力杰半导体技术(杭州)有限公司 | Super junction structure, preparation method of super junction structure and semiconductor device |
| CN117423723A (en) * | 2023-11-29 | 2024-01-19 | 芯长征微电子制造(山东)有限公司 | Power device capable of improving avalanche tolerance of super junction structure and preparation method |
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