CN113517332A

CN113517332A - Complex super-junction semiconductor device based on cylindrical super-junction region and preparation method thereof

Info

Publication number: CN113517332A
Application number: CN202110632339.3A
Authority: CN
Inventors: 何艳静; 裴冰洁; 袁嵩; 江希; 弓小武
Original assignee: Xidian University
Current assignee: Xidian University
Priority date: 2021-06-07
Filing date: 2021-06-07
Publication date: 2021-10-19

Abstract

The invention discloses a complex super-junction semiconductor device based on a cylindrical super-junction region and a preparation method thereof. The device comprises a drain metal layer, an N+ substrate region, an N-type first buffer layer, a drain metal layer, an N ⁺ substrate region, an N-type first buffer layer, N-type second buffer layer, N-type epitaxial layer; a number of P-type pillar regions, arranged at intervals in the N-type epitaxial layer; a number of P ⁺ body regions, respectively arranged above each P-type pillar region, wherein each P Two N ⁺ contact regions and one P ⁺ contact region are arranged in the ⁺ body region, and the P ⁺ contact region is arranged between the two N ⁺ contact regions; the dielectric layer is arranged above the N-type epitaxial layer and partially covers the P ⁺ a body region; a gate electrode disposed within the dielectric layer and adjacent to the N ⁺ contact region; a source metal layer disposed on the dielectric layer, the N ⁺ contact region and the P ⁺ contact region. The invention adds two buffer layers in the device, and forms a soft recovery waveform by controlling the doping concentration of the two buffer layers, thereby reducing reverse recovery current and reverse recovery time to obtain high-speed switching and reduce loss.

Description

Complex super-junction semiconductor device based on cylindrical super-junction region and preparation method thereof

Technical Field

The invention belongs to the technical field of microelectronics, and particularly relates to a complex super-junction semiconductor device based on a cylindrical super-junction area and a preparation method thereof.

Background

The power semiconductor device is a basic and core device of power electronic technology, the breakdown voltage and the switching speed are improved due to the VDMOS structure, and the device structure is used up to now due to the advantages that the conducting direction is vertical to the silicon surface and the VDMOS structure is used as a multi-sub device.

The high withstand voltage performance of the power device requires that the VDMOS has a thicker and low-concentration drift region, but the low doping ensures that the carrier concentration of the drift degree of the device under the conduction condition is not high, so that the on-resistance is increased, and the on-state power consumption is improved. Researches show that the proportional relation of 2.5 power exists between the off-state breakdown voltage and the on-state on-resistance of the device, and in order to solve the contradiction, the concept of 'super junction' is provided. Based on achieving charge balance in the off state, a structure using alternating n-regions and p-regions instead of the original lightly doped region as a drift region is called a super junction. Under the forward bias mode, the highly doped n column in the super junction semiconductor device provides enough current carriers for conducting current, low on-resistance is guaranteed, and under the reverse mode, the depletion region extends between the n column and the p column along the transverse direction to form an intrinsic semiconductor-like structure, so that high reverse breakdown voltage can be obtained despite high doping concentration in the n region. The super junction semiconductor device is generally designed for high voltage applications, and the resistance in the N-type epitaxial layer controls the on-resistance, so that the super junction semiconductor device can be improved for better performance, and the IGBT is widely used as a high breakdown voltage switching element in an inverter circuit. IGBTs have characteristics of bipolar transistors such as high breakdown voltage and low on-voltage, and superior characteristics of being able to operate at high speed, which are important semiconductor elements supporting current power electronics, despite the speed lower than that of MOSFETs. Since one reverse breakdown voltage junction, i.e., the collector junction, of the IGBT generally cannot flow current in the opposite direction, when the IGBT is turned from the on state to the forward blocking state, a great reverse voltage may be generated to cause the device to break down, and thus, a diode may be connected in parallel with the IGBT.

However, this parallel configuration has limitations in increasing switching speed, such as increasing reverse recovery time and decreasing switching speed.

Disclosure of Invention

In order to solve the problems in the prior art, the invention provides a complex super-junction semiconductor device based on a cylindrical super-junction region and a preparation method thereof.

One embodiment of the present invention provides a complex super junction semiconductor device based on a cylindrical super junction region, including:

a drain metal layer;

N⁺the substrate region is arranged on the drain metal layer;

an N-type first buffer layer disposed on the N⁺A substrate region;

the N-type second buffer layer is arranged on the N-type first buffer layer;

the N-type epitaxial layer is arranged on the N-type second buffer layer, wherein the doping concentration of the first buffer layer is greater than that of the N-type epitaxial layer, and the doping concentration of the second buffer layer is less than that of the N-type epitaxial layer;

the P-type column regions are arranged in the N-type epitaxial layer at intervals;

a number of P⁺A body region respectively disposed above each of the P-type column regions and adjacent to the upper surface of the N-type epitaxial layer, wherein each of the P-type column regions is formed in a P-type region⁺Two N are arranged in the body region⁺Contact region, a P⁺A contact region, and the P⁺Contact regions are arranged between the two N⁺Between the contact zones;

a plurality of dielectric layers, each of the dielectric layersA dielectric layer disposed above the N-type epitaxial layer and partially covering the P⁺A body region;

a plurality of gates respectively disposed in each of the dielectric layers and adjacent to the N⁺A contact zone;

a source metal layer disposed on the dielectric layers and the N⁺Contact region and P⁺On the contact region with said N⁺Contact and said P⁺The contacts all form ohmic contacts.

In one embodiment of the present invention, said N⁺The thickness of the substrate region is 5-7 μm, and the doping concentration is 2 × 10¹⁸cm^-3～5×10¹⁸cm^-3。

In one embodiment of the present invention, the N-type first buffer layer has a thickness of 10 to 12 μm and a doping concentration of 1 × 10¹⁶cm^-3～1×10¹⁷cm^-3。

In one embodiment of the present invention, the N-type second buffer layer has a thickness of 4 to 6 μm and a doping concentration of 1 × 10¹⁵cm^-3～8×10¹⁵cm^-3。

In one embodiment of the invention, the thickness of the N-type epitaxial layer is 60-100 μm, and the doping concentration is 3 x 10¹⁵cm^-3～2×10¹⁶cm^-3。

In one embodiment of the present invention, a distance between the lower side of each of the P-type pillar regions and the second buffer layer is at least 3 μm.

In one embodiment of the present invention, said P⁺The depth of the body region in the P-type column region is 0.5-0.7 μm, and the doping concentration is 3 × 10¹⁸cm^-3～1×10¹⁹cm^-3(ii) a Said N is⁺Contact region at the P⁺The depth in the body region is 0.2-0.4 μm, and the doping concentration is 1 × 10¹⁹cm^-3～6×10¹⁹cm^-3(ii) a And said P⁺Contact region at the P⁺The depth in the body region is 0.2-0.4 μm, and the doping concentration is 2 × 10¹⁹cm^-3～1×10²⁰cm^-3。

Another embodiment of the present invention provides a method for manufacturing a complex super-junction semiconductor device based on a cylindrical super-junction region, including:

in N⁺Sequentially growing a first buffer layer and a second buffer layer on the substrate area;

growing an N-type epitaxial layer on the second buffer layer, wherein the doping concentration of the first buffer layer is greater than that of the N-type epitaxial layer, and the doping concentration of the second buffer layer is less than that of the N-type epitaxial layer;

forming a plurality of P-type column regions distributed at intervals in the N-type epitaxial layer;

growing a plurality of gates on the N-type epitaxial layer adjacent to each P-type column region;

forming P-type pillars on the substrate⁺A body region;

at each of the P⁺Two N are formed in the body region⁺Contact region, a P⁺A contact zone;

growing a plurality of dielectric layers on the N-type epitaxial layer, wherein the dielectric layers wrap all the grid electrodes;

in said N⁺A drain metal layer is formed below the substrate region, and two N dielectric layers are formed on the dielectric layers⁺Contact region, one said P⁺And forming a source metal layer on the contact region to finish the preparation of the complex super-junction semiconductor device based on the cylindrical super-junction region.

In one embodiment of the invention, a trench embedding method is adopted to embed N⁺And sequentially growing the first buffer layer and the second buffer layer on the substrate region.

In one embodiment of the invention, in said N⁺The substrate area is sequentially grown with the thickness of 10-12 mu m and the doping concentration of 1 multiplied by 10¹⁶cm^-3～1×10¹⁷cm^-3The first buffer layer has a thickness of 4-6 μm and a doping concentration of 1 × 10¹⁵cm^-3～8×10¹⁵cm^-3The thickness of the N-type epitaxial layer grown on the second buffer layer is 60 mum-100 μm, doping concentration of 3 × 10¹⁵cm^-3～2×10¹⁶cm^-3。

Compared with the prior art, the invention has the beneficial effects that:

the invention provides a cylindrical super-junction region-based complex super-junction semiconductor device, which is characterized in that two buffer layers, namely a first buffer layer and a second buffer layer, are additionally arranged in the device, and the two buffer layers are controlled to meet the following requirements: the doping concentration of the first buffer layer is greater than that of the N-type epitaxial layer, the doping concentration of the second buffer layer is less than that of the N-type epitaxial layer, so that reverse recovery time is prolonged by prolonging carrier discharge time, a soft recovery waveform is formed, and further reverse recovery current and reverse recovery time can be reduced by relaxing a hard recovery waveform during reverse recovery operation to obtain high-speed switching and reduce loss.

The present invention will be described in further detail with reference to the accompanying drawings and examples.

Drawings

Fig. 1 is a schematic structural diagram of a complex super-junction semiconductor device based on a cylindrical super-junction region according to an embodiment of the present invention;

fig. 2 is a schematic flow chart of a method for manufacturing a complex super-junction semiconductor device based on a cylindrical super-junction region according to an embodiment of the present invention;

fig. 3a to 3h are schematic structural diagrams of a method for manufacturing a complex super-junction semiconductor device based on a cylindrical super-junction region according to an embodiment of the present invention.

Description of reference numerals:

1-a drain metal layer; 2-N⁺A substrate region; a 3-N type first buffer layer; a 4-N type second buffer layer; 5-N type epitaxial layer; a 6-P type column region; 7-P⁺A body region; 8-N⁺A contact zone; 9-P⁺A contact zone; 10-a dielectric layer; 11-a gate; 12-a source metal layer; an upper surface of the 13-N type epitaxial layer; 14-N⁺A lower surface of the substrate region.

Detailed Description

The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.

Example one

Referring to fig. 1, fig. 1 is a schematic structural diagram of a complex super junction semiconductor device based on a cylindrical super junction region according to an embodiment of the present invention. The embodiment provides a complex super-junction semiconductor device based on a cylindrical super-junction region, which comprises:

a drain metal layer 1; n is a radical of⁺ A substrate region 2 disposed on the drain metal layer 1; an N-type first buffer layer 3 disposed on N⁺On the substrate region 2; an N-type second buffer layer 4 disposed on the N-type first buffer layer 3; the N-type epitaxial layer 5 is arranged on the N-type second buffer layer 4, wherein the doping concentration of the first buffer layer 3 is greater than that of the N-type epitaxial layer 5, and the doping concentration of the second buffer layer 4 is less than that of the N-type epitaxial layer 5; a plurality of P-type column regions 6 which are arranged in the N-type epitaxial layer 5 at intervals; a number of P⁺Body regions 7 respectively disposed over each of the P-type column regions 6 and adjacent to the upper surface of the N-type epitaxial layer 5, wherein each P-type column region is formed by a single P-type epitaxial layer⁺Two N are arranged in the body region 7⁺ Contact region 8, a P⁺Contact region 9, and P⁺The contact regions 9 are arranged at two N⁺Between the contact zones 8; several dielectric layers 10, each dielectric layer 10 is disposed above the N-type epitaxial layer 5 and partially covers the P⁺ A body region 7; a plurality of gates 11 respectively disposed in each dielectric layer 10 and adjacent to N⁺ A contact zone 8; a source metal layer 12 disposed on the dielectric layers 10, N⁺Contact regions 8 and P⁺On contact region 9 with N⁺Contacts 8 and P⁺The contacts 9 all form ohmic contacts. This embodiment has increased two-layer buffer layer in the device, first buffer layer, second buffer layer promptly, controls to satisfy between the two-layer buffer layer: the doping concentration of the first buffer layer is greater than that of the N-type epitaxial layer, the doping concentration of the second buffer layer is less than that of the N-type epitaxial layer, so that reverse recovery time is prolonged by prolonging carrier discharge time, a soft recovery waveform is formed, and further reverse recovery current and reverse recovery time can be reduced by relaxing a hard recovery waveform during reverse recovery operation to obtain high-speed switching and reduce loss.

Specifically, theIn short, the source metal layer 12 of the present embodiment covers two N⁺Upper surface of contact region 8, P⁺The upper surface of the contact region, as well as the upper and side surfaces of the dielectric layers 10, the source metal layer 12 and the two N⁺Contact region 8, P⁺The interface of the contact region is ohmic contact.

In this embodiment, the gates 11 are completely surrounded by dielectric layers 10, a gate dielectric layer being provided between each gate 11 and the upper surface 13 of the N-type epitaxial layer, all gates 11 and gate dielectric layers being provided within the dielectric layers 10, the purpose of the dielectric layers 10 being to encapsulate the gates and insulate them from the superjunction region.

In the present embodiment, each P-type column region 6 and the N-type epitaxial layer 5 form a P/N super junction region, and a depletion layer is formed at a contact position of each P-type column region 6 and the N-type epitaxial layer 5. The distance between the lower part of each P-type column region 6 and the second buffer layer 4 is at least 3 μm, so that the lower part of each P-type column region 6 and N⁺The distance between the lower surface 14 of the substrate region 2 and the N-type column region 6 is not more than 25 μm⁺The distance between the lower surfaces 14 of the substrate regions 2 is small and the on-state or forward resistance is determined by the resistance of the N-epi 5, since the P-type column regions 6 allow for a relatively high doping concentration in the N-epi 5 and a relatively low resistance of the N-epi 5 layer.

In this embodiment, P is provided under several gates 11 in the device⁺The surface of the body region 7 serves as a channel region for forming a channel-adjusting turn-on voltage.

In the present embodiment, P is set⁺The contact region 9 is a high-concentration injection region, and is used for reducing the base resistance of the parasitic NPN tube and preventing the parasitic NPN tube from being burnt due to the fact that the parasitic NPN tube is opened during reverse voltage resistance.

In the present embodiment, the growth of the N-type epitaxial layer 5 is by a method of epitaxially growing a single crystal semiconductor layer, in which a single crystal lattice of the grown semiconductor layer is grown in alignment with a single crystal of the base substrate.

In the present embodiment, in the first buffer layer 3 and the second buffer layer 4, the carrier bank is formed by adjusting the doping concentration and the thickness, so that even several P-type column regions are formed6 and the N-type epitaxial layer 5 form a P/N super junction MOSFET in a forward blocking state, no depletion layer reaches N⁺The substrate region 2, thereby making the reverse recovery waveform rise gently, without depleting the carriers in the N-type epitaxial layer 5 even in the reverse recovery operation. In this embodiment, the second buffer layer 4 and the first buffer layer 3 are sequentially provided below the N-type epitaxial layer 5, and the first buffer layer 3, the second buffer layer 4, and the N-type epitaxial layer must satisfy: the impurity concentration of the second buffer layer 4 is smaller than that of the N-type epitaxial layer 5, the impurity concentration of the first buffer layer 3 is greater than that of the N-type epitaxial layer 5, thereby making the carrier lifetime of the N-type epitaxial layer 5 shorter than that of the first buffer layer 3, the first buffer layer 3 functions as a carrier memory, and has an advantageous effect of extending the reverse recovery time by extending the carrier discharge time, thereby forming a soft recovery waveform, and further by relaxing the hard recovery waveform during the reverse recovery operation, the reverse recovery current and the reverse recovery time can be thus reduced to obtain high-speed switching and reduction of loss. In this embodiment, the first buffer layer 3 and the second buffer layer 4 are sequentially grown by a trench embedding method.

Preferably, N⁺The thickness of the substrate region 2 is 5-7 μm, and the high concentration of diazo doping is 2 × 10¹⁸cm^-3～5×10¹⁸cm^-3。

Preferably, the N-type first buffer layer 3 has a thickness of 10 to 12 μm and a doping concentration of 1 × 10¹⁶cm^-3～1×10¹⁷cm^-3。

Preferably, the N-type second buffer layer 4 has a thickness of 4 to 6 μm and a doping concentration of 1 × 10¹⁵cm^-3～8×10¹⁵cm^-3。

Preferably, the N-type epitaxial layer 5 has a thickness of 60 μm to 100 μm and a doping concentration of 3 × 10¹⁵cm^-3～2×10¹⁶cm^-3。

Preferably, the thickness of the gate dielectric layer formed on the upper surface 13 of the N-type epitaxial layer is 0.1 to 0.2 μm, and the thickness of the gate 11 is 0.2 to 0.3 μm.

Preferably, P⁺The depth of the body region 7 is 0.5-0.7 μm, and the doping concentration is 3 × 10¹⁸cm^-3～1×10¹⁹cm^-3。

Preferably, two N⁺The depth of the contact region 8 is 0.2-0.4 μm, and the doping concentration is 1 × 10¹⁹cm^-3～6×10¹⁹cm^-3And P⁺The contact region 9 has a depth of 0.2-0.4 μm and a doping concentration of 2 × 10¹⁹cm^-3～1×10²⁰cm^-3。

Preferably, the dielectric layer 10 is grown on the surface of the gate electrode 11 to have a thickness of 0.3 μm to 0.5 μm, and the gate electrode 11 is completely covered by the dielectric layer 10.

Preferably, the thickness of the source metal layer 12 is 0.3 μm to 1 μm.

Preferably, in N⁺The thickness of the drain metal layer 1 grown on the substrate 2 is 0.3-1 μm.

Preferably, the source metal layer 12 and the drain metal layer 1 are respectively composed of aluminum, copper, or an alloy of aluminum or copper (e.g., AlSi alloy, aluminum copper alloy, or aluminum copper alloy) or an alloy containing them as a main component.

In summary, in the complicated super-junction semiconductor device based on the cylindrical super-junction region of the embodiment, two buffer layers are added in the device, so that the doping concentrations of the second buffer layer 4 and the P/N super-junction region are smaller than the doping concentration of the first buffer layer 3, the first buffer layer 3 is used as a carrier memory, and a depletion layer is prevented from reaching the N layer⁺The substrate region 2 extends the carrier discharge time to extend the reverse recovery time, so that the reverse recovery waveform rises smoothly, thereby achieving high-speed switching and low reverse recovery loss.

Example two

On the basis of the first embodiment, please refer to fig. 2 and fig. 3a to fig. 3h, fig. 2 is a schematic flow chart of a method for manufacturing a complex super-junction semiconductor device based on a cylindrical super-junction region according to an embodiment of the present invention, fig. 3a to fig. 3h are schematic structural diagrams of a method for manufacturing a complex super-junction semiconductor device based on a cylindrical super-junction region according to an embodiment of the present invention, the present embodiment provides a method for manufacturing a complex super-junction semiconductor device based on a cylindrical super-junction region, and the method for manufacturing a complex super-junction semiconductor device based on a cylindrical super-junction region includes the following steps:

s1 at N⁺A first buffer layer 3 and a second buffer layer 4 are grown in sequence on the substrate region 2.

Specifically, referring to FIG. 3a again, the present embodiment adopts the trench embedding method to form a heavily doped 2 × 10 trench with a thickness of 5 μm to 7 μm¹⁸cm^-3～5×10¹⁸cm^-3N of (A)⁺The substrate layer 2 is epitaxially grown in sequence with the thickness of 10-12 mu m and the doping concentration of 1 multiplied by 10¹⁶cm^-3～1×10¹⁷cm^-3And an N-type first buffer layer 3 having a thickness of 4 to 6 μm and a doping concentration of 1 x 10¹⁵cm^-3～8×10¹⁵cm^-3The N-type second buffer layer 4. The buffer layer is usually grown by an epitaxial growth method which is too slow in epitaxial growth speed and requires high requirements for maintaining a pure epitaxial layer, and the conventional epitaxial growth method requires an additional process for maintaining N⁺The purity of the substrate region 2. Although the trench embedding method is adopted in the embodiment, the trench embedding is not so harsh relative to the environment required by epitaxial growth, the trench embedding method adopted in the embodiment can improve the formation speed of the first buffer layer 3 and the second buffer layer 4, reduce the defect density, stress and bending degree of epitaxial growth, and overcome the problems that the epitaxial growth speed is too slow and the requirement for maintaining a pure epitaxial layer is too high in the conventional method, and furthermore, the embodiment forms a carrier library by adjusting the doping concentration and thickness of the first buffer layer 3 and the second buffer layer 4, so as to be used for subsequently controlling the reverse recovery time and the switching speed of the device.

And S2, growing the N-type epitaxial layer 5 on the second buffer layer 4.

Specifically, referring to FIG. 3b again, in this embodiment, a single crystal semiconductor is epitaxially grown on the upper surface of the N-type first buffer layer 3 to a thickness of 60 μm to 100 μm and a doping concentration of 3 × 10¹⁵cm^-3～2×10¹⁶cm^-3And an N-type epitaxial layer 5. Wherein the single crystal lattice of the N-type epitaxial layer 5 and N are grown by a method of epitaxially growing a single crystal semiconductor layer⁺Single crystal aligned growth of the substrate region 2; in the preparation processThe requirements among the first buffer layer 3, the second buffer layer 4 and the N-type epitaxial layer 5 are as follows: the doping concentration of the first buffer layer 3 is greater than that of the N-type epitaxial layer 5, and the doping concentration of the second buffer layer 4 is less than that of the N-type epitaxial layer 5.

And S3, forming a plurality of P-type column regions 6 distributed at intervals in the N-type epitaxial layer 5.

Specifically, referring to fig. 3c, in the present embodiment, a plurality of P-type pillar regions 6 are formed in the N-type epitaxial layer 5 at intervals by an ion implantation method, each P-type pillar region 6 corresponds to a super junction region, and the forming of the plurality of P-type pillar regions 6 in the N-type epitaxial layer 5 at intervals specifically includes:

impurities of at least one P-type conductivity type are implanted into the surface of the N-type epitaxial layer 5 using a plurality of spaced implantation masks, and a plurality of spaced P-type column regions 6 are formed by diffusing the implanted impurities into the implanted regions. Wherein N is formed below each P-type column region 6⁺The distance between the lower surface 14 of the substrate region and the upper surface of the second buffer layer 4 cannot exceed 25 μm, i.e. the distance between the lower side of each P-type pillar region 6 and the upper surface of the second buffer layer is at least 3 μm. The P-type conductivity impurity includes, but is not limited to, boron and indium.

The present embodiment can control the lifetime of carriers by controlling the carrier concentration of the N-type buffer layer in order to accelerate the disappearance of carriers in the diode in the reverse recovery operation, reduce the peak current and the reverse recovery time during the reverse recovery, and reduce the loss during the reverse recovery. In this embodiment, the requirement on the uniformity of the concentration of the doping carriers of the second buffer layer 4 and the first buffer layer 3 is extremely high, and a conventional ion implantation or diffusion doping method is adopted, although the superconducting structure with two buffer layers can be added in this embodiment, the obtained super junction semiconductor device does not achieve the optimal effect. Therefore, the present embodiment employs a method of locally controlling the lifetime by adding a heavy metal (e.g., gold or platinum) that can be added to the second buffer layer 4 by ion implantation from the source region side surface and heat treatment and/or irradiating charged particles (e.g., protons), which enables uniform doping of the doping carriers in the second buffer layer 4; similarly, the first buffer layer 3 is formed by adding heavy metal or irradiating charged particles, and the heavy metal ions and/or charged particles are irradiated from the front surface of the first buffer layer 3, thereby achieving uniform doping of the doping carriers in the first buffer layer 3. The obtained super junction semiconductor device has the best effect.

S4, growing a number of gates 11 on the N-type epitaxial layer 5 adjacent to each P-type pillar region 6.

Specifically, referring to fig. 3d again, the present embodiment grows a plurality of gates 11 on the N-type epitaxial layer 5 adjacent to each P-type pillar region 6, specifically including: and etching a corresponding mask window on the N-type epitaxial layer 5 adjacent to each P-type column region 6 through a mask layer, and forming a gate dielectric layer with the thickness of 0.1-0.2 mu m and a plurality of gates 11 with the thickness of 0.2-0.3 mu m through a photoetching process.

S5, forming P regions above each P-type column region 6⁺And a body region 7.

Specifically, referring to fig. 3e again, in the embodiment, a self-aligned process is used to implant P-type ions between the two gates 11, and a high temperature annealing process is performed to push the P-type ions forward under the gates 11 and the N-type epitaxial layer 5, so as to form a plurality of P-type ions⁺Body regions 7 of each P⁺The depth of the body region 7 is 0.5-0.7 μm, and the doping concentration is 3 × 10¹⁸cm^-3～1×10¹⁹cm^-3。

S6, at each P⁺Two N's are formed in the body region 7⁺ Contact region 8, a P⁺Contact zone 9.

Specifically, referring to fig. 3f again, in the present embodiment, a corresponding mask window is formed through the mask layer, and an ion implantation process and an annealing process are performed through the mask window, at P⁺The depth of the body region 7 connected with the N-type epitaxial layer 5 is 0.2-0.4 μm, and the doping concentration is 1 × 10¹⁹cm^-3～6×10¹⁹cm^-3Two of N⁺Contact region 8 and a depth of 0.2-0.4 μm, a doping concentration of 2 × 10¹⁹cm^-3～1×10²⁰cm^-3P of⁺And removing the mask layer in the contact region 9.

S7, growing several dielectric layers 10 on the N-type epitaxial layer 5, and several dielectric layers 10 wrapping all the gates 11.

Specifically, referring to fig. 3g again, in this embodiment, a dielectric layer 10 is grown on the surface of the N-type epitaxial layer 5 and the gate 11, the dielectric layer 10 is etched to make the gate 11 be covered by the dielectric layer 10, and two N are exposed⁺ Contact region 8 and two N⁺P between contact regions 8⁺The contact region 9 forms a contact hole. Wherein, the thickness of the dielectric layer 10 grown on the surface of the gate 11 is 0.3 μm to 0.5 μm.

S8 at N⁺A drain metal layer 1 is formed below the substrate region 2, two N on several dielectric layers 10⁺ Contact region 8, a P⁺And forming a source metal layer 12 on the contact region 9 to complete the preparation of the cylindrical super-junction region-based complex super-junction semiconductor device.

Specifically, referring to fig. 3h again, the two exposed N of the present embodiment⁺Contact region 8, P⁺Contact region 9, P⁺And depositing metal electrodes with the thickness of 0.3-1 mu m on the surfaces of the body region 7 and the dielectric layer 10 to form a source metal layer 12. At the same time, in N⁺And growing a metal electrode with the thickness of 0.3-1 mu m on the substrate region 2 to form a drain metal layer 1. The drain metal layer 1 and the source metal layer 12 may be formed of aluminum, copper, or an alloy of aluminum or copper (e.g., AlSi alloy, aluminum copper alloy, or aluminum copper alloy) or an alloy containing them as a main component, respectively.

The method for manufacturing a complex super-junction semiconductor device based on a cylindrical super-junction region according to this embodiment may be implemented in the embodiment of the complex super-junction semiconductor device based on a cylindrical super-junction region described in the first embodiment, and the implementation principle and the technical effect are similar, and are not described herein again.

The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.

Claims

1. A complicated super junction semiconductor device based on a cylindrical super junction region, comprising:

a drain metal layer (1);

N⁺a substrate region (2) disposed on the drain metal layer (1);

an N-type first buffer layer (3) disposed on the N⁺On the substrate region (2);

an N-type second buffer layer (4) disposed on the N-type first buffer layer (3);

the N-type epitaxial layer (5) is arranged on the N-type second buffer layer (4), wherein the doping concentration of the first buffer layer (3) is greater than that of the N-type epitaxial layer (5), and the doping concentration of the second buffer layer (4) is less than that of the N-type epitaxial layer (5);

the P-type column regions (6) are arranged in the N-type epitaxial layer (5) at intervals;

a number of P⁺A body region (7) respectively disposed above each of the P-type column regions (6) and adjacent to an upper surface of the N-type epitaxial layer (5), wherein each of the P-type column regions is formed of a silicon nitride, and wherein the P-type column regions are formed of silicon nitride⁺Two N are arranged in the body region (7)⁺Contact region (8), P⁺A contact region (9), and said P⁺Contact areas (9) are arranged at the two N⁺Between the contact zones (8);

a plurality of dielectric layers (10), each dielectric layer (10) being arranged above the N-type epitaxial layer (5) and partially covering the P⁺A body region (7);

a plurality of gates (11) respectively disposed within each of the dielectric layers (10) and adjacent to the N⁺A contact zone (8);

a source metal layer (12) disposed on the dielectric layers (10), N⁺Contact zone (8) and P⁺On the contact region (9) with said N⁺Contact (8) and said P⁺The contacts (9) all form ohmic contacts.

2. The cylindrical super-junction region based complex super-junction semiconductor device according to claim 1, wherein the N is⁺The thickness of the substrate region (2) is 5-7 μm, and the doping concentration is 2 × 10¹⁸cm^-3～5×10¹⁸cm^-3。

3. The cylindrical super-junction region based complex super-junction semiconductor device as claimed in claim 1, wherein said N-type first buffer layer (3) has a thickness of 10 μm to 12 μm and a doping concentration of 1 x 10¹⁶cm^-3～1×10¹⁷cm^-3。

4. The cylindrical super-junction region based complex super-junction semiconductor device as claimed in claim 1, wherein the thickness of the N-type second buffer layer (4) is 4 μm to 6 μm, and the doping concentration is 1 x 10¹⁵cm^-3～8×10¹⁵cm^-3。

5. The cylindrical super-junction region based complex super-junction semiconductor device as claimed in claim 1, wherein the thickness of the N-type epitaxial layer (5) is 60 μm to 100 μm, and the doping concentration is 3 x 10¹⁵cm^-3～2×10¹⁶cm^-3。

6. The cylindrical super-junction region based complex super-junction semiconductor device according to claim 1, wherein a distance between a lower side of each of the P-type column regions (6) and the second buffer layer (4) is at least 3 μm.

7. The cylindrical super-junction region based complex super-junction semiconductor device according to claim 1, wherein the P is P⁺The depth of the body region (7) in the P-type column region (6) is 0.5-0.7 μm, and the doping concentration is 3 x 10¹⁸cm^-3～1×10¹⁹cm^-3(ii) a Said N is⁺Contact zone (8) at said P⁺The depth in the body region (7) is 0.2-0.4 μm, and the doping concentration is 1 × 10¹⁹cm^-3～6×10¹⁹cm^-3(ii) a And said P⁺Contact area (9) at said P⁺The depth in the body region (7) is 0.2-0.4 μm, and the doping concentration is 2 × 10¹⁹cm^-3～1×10²⁰cm^-3。

8. A method for preparing a complex super-junction semiconductor device based on a cylindrical super-junction area is characterized by comprising the following steps:

in N⁺A first buffer layer (3) and a second buffer layer (4) are sequentially grown on the substrate region (2);

growing an N-type epitaxial layer (5) on the second buffer layer (4), wherein the doping concentration of the first buffer layer (3) is greater than that of the N-type epitaxial layer (5), and the doping concentration of the second buffer layer (4) is less than that of the N-type epitaxial layer (5);

forming a plurality of P-type column regions (6) distributed at intervals in the N-type epitaxial layer (5);

growing a plurality of gates (11) on the N-type epitaxial layer (5) adjacent to each P-type column region (6);

forming P-type pillars (6) above the P-type pillars⁺A body region (7);

at each of the P⁺Two N's are formed in the body region (7)⁺Contact region (8), P⁺A contact zone (9);

growing a plurality of dielectric layers (10) on the N-type epitaxial layer (5), wherein the dielectric layers (10) wrap all the grid electrodes (11);

in said N⁺A drain metal layer (1) is formed below the substrate region (2), two of the N layers on the dielectric layers (10)⁺Contact zone (8), one said P⁺And forming a source metal layer (12) on the contact region (9) to finish the preparation of the complex super junction semiconductor device based on the cylindrical super junction region.

9. The method for manufacturing a cylindrical super-junction region based complex super-junction semiconductor device according to claim 8, wherein a trench embedding method is adopted to embed in the N⁺And the first buffer layer (3) and the second buffer layer (4) are sequentially grown on the substrate region (2).

10. The method for manufacturing a cylindrical super-junction region based complex super-junction semiconductor device according to claim 8, wherein N is⁺The substrate region (2) is sequentially grown with a thickness10-12 μm, and doping concentration of 1 × 10¹⁶cm^-3～1×10¹⁷cm^-3The first buffer layer (3) has a thickness of 4-6 μm and a doping concentration of 1 × 10¹⁵cm^-3～8×10¹⁵cm^-3The second buffer layer (4), the N-type epitaxial layer (5) grown on the second buffer layer (4) has a thickness of 60 to 100 [ mu ] m and a doping concentration of 3 x 10¹⁵cm^-3～2×10¹⁶cm^-3。