CN117497601B - Structure, manufacturing method and electronic equipment of planar silicon carbide transistor - Google Patents

Abstract

A planar silicon carbide transistor structure, a manufacturing method and electronic equipment belong to the technical field of semiconductors, and comprise two grid source structures which are symmetrical left and right, a substrate, a drift layer, a first active region and a plurality of second active regions, wherein the tangential planes which are symmetrical left and right are sagittal planes; the drift layer is arranged on the upper surface of the substrate; the two gate source structures and the first active region are both positioned on the upper surface of the drift layer and are arranged at intervals; the gate-source structure comprises a first well, a first active layer and a gate structure; the first well is arranged on the upper surface of the drift layer; the first trap is arranged at a preset distance from the sagittal plane; the first active layer is arranged in the first well and is positioned on the upper surface of the first well; the grid structure covers the top of the first well; the plurality of second active layers are arranged between the two grid structures; the substrate, the second active layer and the first well are of a first type; the drift layer, the first active region and the first active layer are of a second type; the conduction loss and the chip area are reduced, the reliability and the current density are increased, and the process is simplified.

Description

Structure, manufacturing method and electronic device of planar silicon carbide transistor

Technical Field

The present application belongs to the field of semiconductor technology, and in particular relates to a structure, a manufacturing method and an electronic device of a planar silicon carbide transistor.

Background technique

Silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) have become a strong competitor to silicon insulated gate bipolar transistors (IGBTs) in high-power applications such as electric vehicles and photovoltaic inverters due to their faster switching speeds, lower switching losses, and higher operating temperature ranges. In practical applications, MOSFETs require anti-parallel diodes to handle reverse currents, and silicon-based MOSFETs often use body diodes to reduce parasitic inductance and play a freewheeling role. However, for SiC MOSFETs, the material bandgap is wide, and the body diode turn-on voltage (about 2.7V) is much higher than that of silicon-based MOSFETs (about 1.5V), resulting in large conduction losses.

Related silicon carbide transistors integrate SiC MOSFET with SBD or JFET in anti-parallel to achieve reverse freewheeling, but they are usually connected in parallel on a plane, which increases the chip area. There are also related silicon carbide transistors that use a split gate to control the opening of the freewheeling channel in the reverse direction, but they have problems with gate reliability, complex process and low current density.

Therefore, the related silicon carbide transistors have defects such as large conduction loss, large chip area, poor reliability, complex process and low current density.

Summary of the invention

The purpose of the present application is to provide a structure, a manufacturing method and an electronic device of a planar silicon carbide transistor, aiming to solve the problems of large conduction loss, large chip area, poor reliability, complex process and low current density of related gallium nitride power devices.

The embodiment of the present application provides a structure of a planar silicon carbide transistor, including two left-right symmetrical gate-source structures, a substrate, a drift layer, and a first active region, wherein the left-right symmetrical section is a sagittal plane;

The drift layer is disposed on the upper surface of the substrate;

The two gate-source structures and the first active region are both located on the upper surface of the drift layer and are spaced apart from each other;

The gate-source structure comprises:

A first well disposed on the upper surface of the drift layer; wherein a preset distance is set between the first well and the sagittal plane;

A first active layer disposed in the first well and located on an upper surface of the first well;

a gate structure covering a top portion of the first well;

The structure of the planar silicon carbide transistor further includes:

A plurality of second active layers disposed between the two gate structures;

The substrate, the second active layer and the first well are of the first type; the drift layer, the first active region and the first active layer are of the second type.

In one embodiment, the structure of the planar silicon carbide transistor further includes:

Two second active regions are arranged on a side of the first well away from the sagittal plane.

In one embodiment, the structure of the planar silicon carbide transistor includes:

A third active region is located between the second active region and the first active region and on an upper surface of the drift layer.

In one embodiment, the structure of the planar silicon carbide transistor includes:

A charge storage region is arranged between the two first wells.

In one embodiment, the first type is P type, and the second type is N type; or

The first type is N type, and the second type is P type.

In one embodiment, it also includes:

a first metal layer covering the first active layer and the second active layer;

a second metal layer located on the upper surface of the first active area;

a third metal layer connected to the gate structure;

The first metal layer is a source electrode of the planar silicon carbide transistor, the second metal layer is a drain electrode of the planar silicon carbide transistor, and the third metal layer is a gate electrode of the planar silicon carbide transistor.

In one embodiment, the material of the gate structure includes silicon dioxide and polysilicon; the material of the second active layer includes polysilicon; and the material of the drift layer, the first active region, the first active layer and the first well includes silicon carbide.

The present application also provides a method for manufacturing a planar silicon carbide transistor, the method comprising:

forming a drift layer on the upper surface of the substrate;

Two left-right symmetrical first wells are formed on the upper surface of the first side of the drift layer; wherein the left-right symmetrical section is a sagittal plane, and a preset distance is set between the first well and the sagittal plane;

forming two first active layers respectively in the two first wells and on upper surfaces of the first wells, and forming a first active region on an upper surface of a second side of the drift layer;

forming two gate structures on top of the two first wells respectively;

A plurality of second active layers are formed between the two gate structures.

In one embodiment, after forming two left-right symmetrical first wells on the upper surface of the drift layer, the method further comprises:

Two second active regions are respectively formed on the sides of the two first wells away from the sagittal plane.

In one embodiment, after forming two second active regions on the two first wells away from the sagittal plane respectively, the method further comprises:

A third active region is formed between the second active region and the first active region and on an upper surface of the drift layer.

In one embodiment, after forming a plurality of second active layers between the two gate structures, the method further includes:

forming a first metal layer on an upper surface of the first active layer and an upper surface of the second active layer;

forming a second metal layer on the upper surface of the first active area;

A third metal layer connected to the gate structure is formed.

An embodiment of the present application also provides an electronic device, which includes the structure of the above-mentioned planar silicon carbide transistor.

Compared with the prior art, the embodiment of the present invention has the following beneficial effects: since the first active region is used as the drain, the first well is used as the gate, and the first active layer is used as the source. The second active layer and the drift layer form a heterojunction. When a forward voltage is applied to the planar silicon carbide transistor, the drain and the source are turned on, the heterojunction is reverse biased, and the depletion layer of the heterojunction expands and pinches off the freewheeling channel; when a reverse voltage is applied to the planar silicon carbide transistor, the drain and the source are turned off, the heterojunction is forward biased, and the depletion layer of the heterojunction expands and pinches off the freewheeling conduction, so that the reverse freewheeling effect can be achieved without the need to integrate the SiC MOSFET with a Schottky barrier diode (SBD) or a junction field-effect transistor (JFET) in anti-parallel connection, thereby reducing the conduction loss and chip area, increasing reliability and current density, and simplifying the process.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical invention in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

FIG1 is a schematic diagram of a structure of a planar silicon carbide transistor provided in an embodiment of the present application;

FIG2 is a schematic diagram of a freewheeling channel in a planar silicon carbide transistor according to an embodiment of the present application;

FIG3 is an energy band diagram of a planar silicon carbide transistor structure provided in one embodiment of the present application;

FIG4 is another schematic diagram of the structure of a planar silicon carbide transistor provided in an embodiment of the present application;

FIG5 is another schematic diagram of the structure of a planar silicon carbide transistor provided in an embodiment of the present application;

FIG6 is another energy band diagram of the structure of a planar silicon carbide transistor provided in one embodiment of the present application;

FIG7 is another schematic diagram of the structure of a planar silicon carbide transistor provided in an embodiment of the present application;

FIG8 is another schematic diagram of the structure of a planar silicon carbide transistor provided in an embodiment of the present application;

FIG9 is a schematic diagram of forming a drift layer in a method for manufacturing a planar silicon carbide transistor provided in an embodiment of the present application;

FIG10 is a schematic diagram of forming a first well in the method for manufacturing a planar silicon carbide transistor provided in an embodiment of the present application;

FIG11 is a schematic diagram of forming a first active layer and a first active region in a method for manufacturing a planar silicon carbide transistor provided in an embodiment of the present application;

FIG12 is a schematic diagram of forming a gate structure in a method for manufacturing a planar silicon carbide transistor provided in an embodiment of the present application;

FIG13 is a schematic diagram of forming a second active layer in the method for manufacturing a planar silicon carbide transistor provided in an embodiment of the present application;

FIG14 is a schematic diagram of forming a second active region in the method for manufacturing a planar silicon carbide transistor provided in an embodiment of the present application;

FIG. 15 is a schematic diagram of forming a third active region in the method for manufacturing a planar silicon carbide transistor provided in an embodiment of the present application.

Detailed ways

In order to make the technical problems, technical solutions and beneficial effects to be solved by this application more clearly understood, this application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain this application and are not used to limit this application.

It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

FIG. 1 shows the structure of a planar silicon carbide transistor provided by an embodiment of the present invention. For ease of description, only the parts related to the embodiment of the present invention are shown, which are described in detail as follows:

The structure of the planar silicon carbide transistor includes two left-right symmetrical gate-source structures, a substrate 10 , a drift layer 20 , a first active region 90 , and a plurality of second active layers 60 , and the left-right symmetrical section is a sagittal plane 100 .

The drift layer 20 is disposed on the upper surface of the substrate 10 .

The two gate-source structures and the first active region 90 are both located on the upper surface of the drift layer 20 and are spaced apart from each other.

The gate-source structure includes a first well 30 , a first active layer 40 and a gate structure 50 .

The first well 30 is disposed on the upper surface of the drift layer 20 ; wherein a preset distance is set between the first well 30 and the sagittal plane 100 .

The first active layer 40 is disposed in the first well 30 and is located on an upper surface of the first well 30 .

The gate structure 50 covers the top of the first well 30 .

The plurality of second active layers 60 are disposed between the two gate structures 50 .

The doping types of the substrate 10, the second active layer 60 and the first well 30 are of the first type, and the doping types of the drift layer 20, the first active region 90 and the first active layer 40 are of the second type. The first type and the second type are different.

It should be noted that the second active layer 60 is highly doped with a doping concentration above 1e19, a width of about 0.1 to 0.2 μm, and a freewheeling channel width of 0.1 to 0.2 μm. This structure can increase the freewheeling channel with a very small increase in the cell area.

The number of the second active layers 60 is more than two. The drawings in the specification of the present application illustrate that two second active layers 60 form a freewheeling channel. An embodiment of simply increasing the number of second active layers 60 and freewheeling channels is also within the protection scope of the present application.

In a specific implementation, the first active region 90 serves as a drain, the first well 30 serves as a gate, and the first active layer 40 serves as a source. The second active layer 60 and the drift layer 20 form a heterojunction. Taking the first type as P type and the second type as N type as an example, when a forward voltage is applied to the planar silicon carbide transistor, the source is connected to a low potential, the drain and the source are turned on, the heterojunction is reverse biased, and the depletion layer of the heterojunction expands to pinch off the freewheeling channel, as shown in the left half of FIG. 2. When a reverse voltage is applied to the planar silicon carbide transistor, the source is connected to a high potential, the drain and the source are turned off, the heterojunction is forward biased, and the depletion layer of the heterojunction expands to pinch off the freewheeling conduction, as shown in the right half of FIG. 2, so that the reverse freewheeling function can be achieved without the need to integrate the SiC MOSFET with the SBD or the junction field effect transistor JFET in anti-parallel connection, which reduces the conduction loss and chip area, increases the reliability and current density, and simplifies the process.

The heterojunction energy band diagram is shown in FIG3 . Due to the difference in bandgap width, the contact between silicon and silicon carbide will form a barrier difference in the conduction band. In order to prevent excessive forward leakage and affect the withstand voltage, the forward electron barrier ∆E-forward should be large enough. Here, the forward electron barrier ∆Ep-forward is about 0.7 eV. In order to increase the height of the forward electron barrier, it is possible to consider forming a Schottky contact on the second active layer 60. The contact between silicon and silicon carbide does not form a barrier difference in the valence band, so holes can pass freely.

As shown in FIG. 4 , the structure of the planar silicon carbide transistor further includes a second active region 70 .

The second active region 70 is disposed on a side of the first well 30 away from the sagittal plane 100 .

It should be noted that the doping type of the second active region 70 is the first type. The second active region 70 is heavily doped. The material of the second active region 70 may be silicon carbide.

By providing the second active region 70 , adjacent planar silicon carbide transistors are isolated from each other, thereby realizing the integration of cells of multiple planar silicon carbide transistors.

As shown in FIG. 5 , the structure of the planar silicon carbide transistor further includes a third active region 03 .

The third active region 03 is located between the second active region 70 and the first active region 90 and on the upper surface of the drift layer 20 .

It should be noted that the doping type of the third active region 03 is the first type. The third active region 03 is lightly doped. The material of the third active region 03 can be silicon carbide.

The third active region 03 and the drift layer 20 form a super junction structure, which improves the voltage resistance. In addition, for the super junction structure, due to the presence of a large-area semiconductor column in the drift region, there is a certain minority carrier storage effect, and the switching characteristics are poor. However, the heterojunction has no hole barrier, and holes can pass freely, thereby playing a role in quickly extracting holes and improving the switching frequency.

As shown in FIG. 6 , the structure of the planar silicon carbide transistor further includes a charge storage layer 80 (CSL).

The charge storage region 80 is disposed between the two first wells 30 .

It should be noted that the doping type of the charge storage region 80 is the second type. The doping concentration of the charge storage region 80 is greater than the doping concentration of the drift layer 20 and less than the doping concentration of the first active layer 40. The material of the charge storage region 80 is silicon carbide.

It should be noted that the CSL concentration should not exceed 1E17. As shown in FIG. 7 , a high concentration of SiC will make the heterojunction barrier thinner, making it easier for electrons to tunnel from the second active region 70 to the drift layer 20 , thereby increasing the forward leakage current and deteriorating the withstand voltage performance.

By providing the charge storage region 80 , the JFET effect between the first wells 30 is reduced, and the forward conduction current of the planar silicon carbide transistor is increased.

As an example and not limitation, the first type is P type and the second type is N type; or

The first type is N type, and the second type is P type.

As shown in FIG. 8 , the structure of the planar silicon carbide transistor further includes a first metal layer 01 , a second metal layer 02 and a third metal layer.

The first metal layer 01 covers the first active layer 40 and the second active layer 60 .

The second metal layer 02 is located on the upper surface of the first active region 90 .

The third metal layer is connected to the gate structure 50 .

It should be noted that the first metal layer 01 is the source electrode of the planar silicon carbide transistor, the second metal layer 02 is the drain electrode of the planar silicon carbide transistor, and the third metal layer is the gate electrode of the planar silicon carbide transistor.

As an example but not a limitation, the second active layer 60 and the first metal layer 01 are in Schottky contact, thereby increasing the potential barrier and reducing the leakage current when a forward voltage is applied to the planar silicon carbide transistor.

In a specific implementation, the material of the gate structure 50 includes silicon dioxide and polysilicon; the material of the second active layer 60 includes polysilicon; and the material of the drift layer 20 , the first active region 90 , the first active layer 40 and the first well 30 includes silicon carbide.

Corresponding to an embodiment of a planar silicon carbide transistor, the present invention also provides an embodiment of a method for manufacturing a planar silicon carbide transistor.

A method for manufacturing a planar silicon carbide transistor includes steps 401 to 405.

In step 401, as shown in FIG9 , a drift layer 20 is formed on the upper surface of a substrate 10;

The drift layer 20 is formed on the upper surface of the substrate 10 by sputtering or vapor deposition.

In step 402 , as shown in FIG. 10 , two left-right symmetrical first wells 30 are formed on the upper surface of the first side of the drift layer 20 ; wherein the left-right symmetrical section is the sagittal plane 100 , and a preset distance is set between the first well 30 and the sagittal plane 100 .

Two left-right symmetrical first wells 30 are formed on the upper surface of the first side of the drift layer 20 by ion implantation.

In step 403 , as shown in FIG. 11 , two first active layers 40 are formed in the two first wells 30 and on the upper surfaces of the first wells 30 , respectively, and a first active region 90 is formed on the upper surface of the second side of the drift layer 20 .

Two first active layers 40 are formed in the two first wells 30 and on the upper surfaces of the first wells 30 by ion implantation, and a first active region 90 is formed on the upper surface of the second side of the drift layer 20 .

In step 404 , as shown in FIG. 12 , two gate structures 50 are formed on the tops of the two first wells 30 , respectively.

Two gate structures 5050 are formed on the tops of the two first wells 30 respectively by thermal oxidation and polysilicon deposition.

In step 405 , as shown in FIG. 13 , a plurality of second active layers 60 are formed between two gate structures 50 .

A plurality of second active layers 60 are formed between the two gate structures 50 by vapor deposition and ion implantation.

In a specific implementation, step 402 also includes step 402-2 and step 403.

In step 402 - 2 , as shown in FIG. 14 , two second active regions 70 are respectively formed on the sides of the two first wells 30 away from the sagittal plane 100 .

Two second active regions 70 are respectively formed on the sides of the two first wells 30 away from the sagittal plane 100 by ion implantation.

In step 405 - 3 , as shown in FIG. 15 , a third active region 03 is formed between the second active region 70 and the first active region 90 and on the upper surface of the drift layer 20 .

The third active region 03 is formed between the second active region 70 and the first active region 90 and on the upper surface of the drift layer 20 by ion implantation.

In a specific implementation, step 405 also includes steps 406 to 408.

In step 406 , a first metal layer is formed on an upper surface of the first active layer and an upper surface of the second active layer.

In step 407 , a second metal layer is formed on the upper surface of the first active region.

In step 408 , a third metal layer connected to the gate structure is formed.

It is worth emphasizing that the first metal layer is the source electrode of the planar silicon carbide transistor, the second metal layer is the drain electrode of the planar silicon carbide transistor, and the third metal layer is the gate electrode of the planar silicon carbide transistor.

It is worth noting that the metal layer can be gold or palladium.

The embodiment of the present invention includes two left-right symmetrical gate-source structures, a substrate, a drift layer, a first active region and a plurality of second active regions, wherein the left-right symmetrical section is a sagittal plane; the drift layer is arranged on the upper surface of the substrate; the two gate-source structures and the first active region are all located on the upper surface of the drift layer and are arranged at intervals; the gate-source structure includes a first well, a first active layer and a gate structure; the first well is arranged on the upper surface of the drift layer; wherein a preset distance is arranged between the first well and the sagittal plane; the first active layer is arranged in the first well and is located on the upper surface of the first well; the gate structure covers the top of the first well; a plurality of second active layers are arranged between the two gate structures; the substrate, the second active layer and the first well are of the first type; the drift layer, the first active region and the first active layer are of the second type; the conduction loss and the chip area are reduced, the reliability and the current density are increased, and the process is simplified.

It should be understood that the size of the serial numbers of the steps in the above embodiments does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.

The embodiments described above are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, a person skilled in the art should understand that the technical solutions described in the aforementioned embodiments may still be modified, or some of the technical features may be replaced by equivalents. Such modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims (9)

1. A planar silicon carbide transistor structure, characterized in that it comprises two left-right symmetrical gate-source structures, a substrate, a drift layer and a first active region, wherein the left-right symmetrical section is a sagittal plane; The drift layer is disposed on the upper surface of the substrate; The two gate-source structures and the first active region are both located on the upper surface of the drift layer and are spaced apart from each other; The gate-source structure comprises: A first well disposed on the upper surface of the drift layer; wherein a preset distance is set between the first well and the sagittal plane; A first active layer disposed in the first well and located on an upper surface of the first well; a gate structure covering a top portion of the first well; The structure of the planar silicon carbide transistor further includes: A plurality of second active layers disposed between the two gate structures; The substrate, the second active layer and the first well are of the first type; the drift layer, the first active region and the first active layer are of the second type; Also includes: a first metal layer covering the drift layer, the first active layer and the second active layer; a second metal layer located on the upper surface of the first active area; a third metal layer connected to the gate structure; The first metal layer is a source electrode of the planar silicon carbide transistor, the second metal layer is a drain electrode of the planar silicon carbide transistor, and the third metal layer is a gate electrode of the planar silicon carbide transistor; An upper surface of the drift layer is exposed between the plurality of second active layers, and the first metal layer is in direct contact with the exposed upper surface of the drift layer; The material of the second active layer includes polysilicon; the material of the drift layer includes silicon carbide; A heterojunction is formed between the second active layer and the drift layer. 2. The structure of the planar silicon carbide transistor according to claim 1, characterized in that the structure of the planar silicon carbide transistor further comprises: Two second active regions are arranged on a side of the first well away from the sagittal plane. 3. The structure of the planar silicon carbide transistor according to claim 2, characterized in that the structure of the planar silicon carbide transistor comprises: A third active region is located between the second active region and the first active region and on an upper surface of the drift layer. 4. The structure of the planar silicon carbide transistor according to claim 1, wherein the first type is P type and the second type is N type; or The first type is N type, and the second type is P type. 5. The structure of a planar silicon carbide transistor according to any one of claims 1 to 4, characterized in that the material of the gate structure includes silicon dioxide and polysilicon; and the material of the first active region, the first active layer and the first well includes silicon carbide. 6. A method for manufacturing a planar silicon carbide transistor, characterized in that the manufacturing method comprises: forming a drift layer on the upper surface of the substrate; Two left-right symmetrical first wells are formed on the upper surface of the first side of the drift layer; wherein the left-right symmetrical section is a sagittal plane, and a preset distance is set between the first well and the sagittal plane; forming two first active layers respectively in the two first wells and on upper surfaces of the first wells, and forming a first active region on an upper surface of a second side of the drift layer; forming two gate structures on top of the two first wells respectively; forming a plurality of second active layers between the two gate structures; forming a first metal layer on an upper surface of the drift layer, an upper surface of the first active layer, and an upper surface of the second active layer; forming a second metal layer on an upper surface of the first active region; forming a third metal layer connected to the gate structure; An upper surface of the drift layer is exposed between the plurality of second active layers, and the first metal layer is in direct contact with the exposed upper surface of the drift layer; The material of the second active layer includes polysilicon; the material of the drift layer includes silicon carbide; The first metal layer is a source electrode of the planar silicon carbide transistor, the second metal layer is a drain electrode of the planar silicon carbide transistor, and the third metal layer is a gate electrode of the planar silicon carbide transistor; A heterojunction is formed between the second active layer and the drift layer. 7. The method for manufacturing a planar silicon carbide transistor according to claim 6, characterized in that after forming two left-right symmetrical first wells on the upper surface of the drift layer, the method further comprises: Two second active regions are respectively formed on the sides of the two first wells away from the sagittal plane. 8. The method for manufacturing a planar silicon carbide transistor according to claim 6, characterized in that after forming two second active regions on the two first wells at the sides away from the sagittal plane respectively, the method further comprises: A third active region is formed between the second active region and the first active region and on an upper surface of the drift layer. 9. An electronic device, characterized in that the electronic device comprises the structure of the planar silicon carbide transistor according to any one of claims 1 to 5.