JP3479375B2 - Metal oxide semiconductor device in which a pn junction is formed with a thin film transistor made of a metal oxide semiconductor such as cuprous oxide, and methods for manufacturing the same - Google Patents
Metal oxide semiconductor device in which a pn junction is formed with a thin film transistor made of a metal oxide semiconductor such as cuprous oxide, and methods for manufacturing the sameInfo
- Publication number
- JP3479375B2 JP3479375B2 JP06827095A JP6827095A JP3479375B2 JP 3479375 B2 JP3479375 B2 JP 3479375B2 JP 06827095 A JP06827095 A JP 06827095A JP 6827095 A JP6827095 A JP 6827095A JP 3479375 B2 JP3479375 B2 JP 3479375B2
- Authority
- JP
- Japan
- Prior art keywords
- metal oxide
- oxide semiconductor
- thin film
- metal
- film transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/674—Thin-film transistors [TFT] characterised by the active materials
- H10D30/6755—Oxide semiconductors, e.g. zinc oxide, copper aluminium oxide or cadmium stannate
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/67—Thin-film transistors [TFT]
- H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D99/00—Subject matter not provided for in other groups of this subclass
Landscapes
- Shift Register Type Memory (AREA)
- Bipolar Transistors (AREA)
- Thin Film Transistor (AREA)
- Dram (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は，亜酸化銅等の金属酸化
物半導体による薄膜トランジスタとｐｎ接合を形成した
金属酸化物半導体装置およびそれらの製造方法に関する
ものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a metal oxide semiconductor device in which a pn junction is formed with a thin film transistor made of a metal oxide semiconductor such as cuprous oxide, and a manufacturing method thereof.
【０００２】薄膜トランジスタは液晶ディスプレイ，集
積回路，ファクシミリ制御回路等の半導体エレクトロニ
クスの分野において広く使用されている。本発明は，こ
のような薄膜トランジスタおよびｐｎ接合を有する薄膜
半導体装置を金属酸化物半導体により構成したものであ
る。Thin film transistors are widely used in the field of semiconductor electronics such as liquid crystal displays, integrated circuits and facsimile control circuits. The present invention configures a thin film semiconductor device having such a thin film transistor and a pn junction with a metal oxide semiconductor.
【０００３】[0003]
【従来の技術】液晶ディスプレイ等に使用されるトラン
ジスタは，画素毎に付けられたスイッチング用の薄膜ト
ランジスタと画面全体を制御する高移動度のトランジス
タの２種類のトランジスタを必要とする。従来は，この
ようなトランジスタを得るためにアモルファスシリコン
に形成した画素スイッチ用薄膜トランジスタと単結晶シ
リコンに形成した画面制御用のトランジスタ集積回路を
同一基板に貼り合わせるという方法が取られていた。そ
のため配線が複雑になり，液晶ディスプレイのコストを
押し上げる要因になっていた。2. Description of the Related Art A transistor used in a liquid crystal display or the like requires two kinds of transistors, a switching thin film transistor provided for each pixel and a high mobility transistor for controlling the entire screen. Conventionally, in order to obtain such a transistor, a method of attaching a pixel switch thin film transistor formed on amorphous silicon and a screen control transistor integrated circuit formed on single crystal silicon to the same substrate has been used. As a result, the wiring becomes complicated, which has been a factor in increasing the cost of the liquid crystal display.
【０００４】そこで，画素スイッチ用薄膜トランジスタ
の製造時に，ディスプレイ用のガラス基板に画面制御用
のトランジスタを形成するための様々な方法が開発され
てきた。例えば，レーザ熱処理を用いてポリシリコンを
作り，それを用いて高移動度の薄膜トランジスタを作る
方法等である。しかし，この方法は大面積化に必ずしも
有効ではなく安価なガラス基板を使用して低温で作成で
きる薄膜トランジスタの製造方法の開発が望まれてい
る。Therefore, various methods have been developed for forming a screen control transistor on a glass substrate for a display when manufacturing a pixel switch thin film transistor. For example, there is a method of forming polysilicon by using laser heat treatment and forming a high mobility thin film transistor using the polysilicon. However, this method is not necessarily effective for increasing the area, and it is desired to develop a method for manufacturing a thin film transistor that can be manufactured at a low temperature using an inexpensive glass substrate.
【０００５】[0005]
【発明が解決しようとする課題】従来のシリコン半導体
薄膜を使用した薄膜トランジスタは上記のように，安価
なガラス基板を使用して大面積にわたって低温で形成す
ることは困難であった。また，半導体集積回路の微細化
は年々進み，新しい構造のデバイスの開発が必要とされ
ている。As described above, it has been difficult to form a thin film transistor using a conventional silicon semiconductor thin film over a large area at a low temperature by using an inexpensive glass substrate. In addition, miniaturization of semiconductor integrated circuits is advancing year by year, and it is necessary to develop devices with new structures.
【０００６】本発明は，このような課題を解決すること
のできる新しい構造の金属酸化物半導体による薄膜トラ
ンジスタと金属酸化物半導体にｐｎ接合を形成した薄膜
半導体装置およびそれら製造方法を提供する。そして，
従来はあまり省みられなかった亜酸化銅等の金属酸化物
半導体に新しい観点を見出し，半導体集積回路に新しい
技術をもたらすものである。The present invention provides a thin film transistor using a metal oxide semiconductor having a new structure, a thin film semiconductor device having a pn junction formed in the metal oxide semiconductor, and a method for manufacturing the same, which can solve the above problems. And
We have found a new perspective on metal oxide semiconductors such as cuprous oxide, which has not been largely omitted in the past, and brought new technologies to semiconductor integrated circuits.
【０００７】[0007]
【課題を解決するための手段】亜酸化銅，酸化亜鉛，酸
化アルミニム等の金属酸化物が半導体であることは周知
のことである。そして，例えば，亜酸化銅の場合，銅板
をアルゴンと酸素ガスを用いてスパッタすることや，銅
板を単純に熱酸化することなどによって得ることができ
る。金属酸化物半導体は，このように簡単に作れ，か
つ，大面積化も容易であることから太陽電池への応用が
考えられてきたが，亜酸化銅などでは金属酸化物中の過
剰酸素による欠陥の作るアクセプタの密度の制御が少な
くとも従来はできなかったので，ｐｎ接合ができず，そ
のため，亜酸化銅等の金属酸化物半導体は半導体研究の
主流から忘れさられ，半導体装置として実用化をされて
いなかった。It is well known that metal oxides such as cuprous oxide, zinc oxide and aluminum oxide are semiconductors. Then, for example, in the case of cuprous oxide, it can be obtained by sputtering a copper plate using argon and oxygen gas, or by simply thermally oxidizing the copper plate. Metal oxide semiconductors have been considered to be applied to solar cells because they are easy to make and can easily be made large in area. However, in cuprous oxide, defects due to excess oxygen in metal oxides have been considered. Since the density of the acceptors made by the company could not be controlled at least in the past, a pn junction could not be formed. Therefore, metal oxide semiconductors such as cuprous oxide were forgotten from the mainstream of semiconductor research and were put to practical use as semiconductor devices. Didn't.
【０００８】ところで，この金属酸化物半導体にも注目
すべき長所があり，亜酸化銅の場合，低温で作成したに
もかかわらずそのキャリヤ移動度は数１０ｃｍ2 ／Ｖｓ
と比較的に大きいものである。さらに，このような金属
酸化物半導体は，金属膜を後から低温酸化しても得るこ
とができる。つまり，金属薄膜の一部を局所的に金属酸
化物半導体に変えることかできる。このことは，亜酸化
銅等の金属酸化物を用いた薄膜トランジスタ等の電子デ
バイスの製作工程を簡略することができるばかりか，新
しい超微細構造のデバイスの製作を容易ならしめるもの
で，シリコン等の金属酸化物半導体以外の半導体を用い
たのでは 実現できないことである。By the way, this metal oxide semiconductor also has an advantage to be noted. In the case of cuprous oxide, its carrier mobility is several tens cm 2 / Vs even though it is prepared at a low temperature.
And is relatively large. Further, such a metal oxide semiconductor can be obtained by oxidizing the metal film at a low temperature later. That is, a part of the metal thin film can be locally changed to the metal oxide semiconductor. This not only simplifies the manufacturing process of electronic devices such as thin film transistors using metal oxides such as cuprous oxide, but also facilitates the manufacture of new ultrafine structure devices such as silicon. This cannot be achieved by using semiconductors other than metal oxide semiconductors.
【０００９】本発明は，このような金属酸化物半導体に
より薄膜トランジスタを作成するようにした。また，亜
酸化銅等の金属酸化物半導体の一部で知られている過剰
な酸素による欠陥に対して水素等を導入することで欠陥
を制御して，キャリヤ密度および導電型を制御するよう
にし，そのように制御された金属酸化物半導体に対し
て，不純物をドープし良好なｐｎ接合が得られるように
した。さらに逆に酸素が不足することで欠陥が生じてい
る酸化亜鉛等の金属酸化物半導体に対しては酸素，水素
等を導入することにより欠陥を制御して，キャリヤ密度
および導電型を制御するようにし，そのように制御され
た金属酸化物半導体に対して，不純物をドープし良好な
ｐｎ接合が得られるようにした。In the present invention, a thin film transistor is made of such a metal oxide semiconductor. In addition, by introducing hydrogen or the like into defects due to excess oxygen, which is known in some metal oxide semiconductors such as cuprous oxide, defects are controlled, and carrier density and conductivity type are controlled. The metal oxide semiconductor thus controlled is doped with impurities so that a good pn junction can be obtained. On the contrary, for metal oxide semiconductors such as zinc oxide where defects are caused by lack of oxygen, the defects are controlled by introducing oxygen, hydrogen, etc. to control carrier density and conductivity type. The metal oxide semiconductor thus controlled was doped with impurities so that a good pn junction could be obtained.
【００１０】図１は本発明の基本構成(1) を薄膜トラン
ジスタをゲート電極を持つ構造の場合について例示的に
示し，その製造方法の原理を説明するものである。図１
(a)， (b)において，１は基板である。FIG. 1 exemplifies the basic structure (1) of the present invention in the case of a structure in which a thin film transistor has a gate electrode, and explains the principle of a manufacturing method thereof. Figure 1
In (a) and (b), 1 is a substrate.
【００１１】２は電極金属である。３は絶縁膜である。
４は金属膜であって，銅，亜鉛等の酸化処理をすること
により半導体となるものである。金属膜の膜厚は，例え
ば，０．３μｍ程度であり，酸化処理後は０．６μｍ程
度の薄膜である。Reference numeral 2 is an electrode metal. Reference numeral 3 is an insulating film.
Reference numeral 4 denotes a metal film, which becomes a semiconductor by oxidizing copper, zinc or the like. The film thickness of the metal film is, for example, about 0.3 μm, and is a thin film of about 0.6 μm after the oxidation treatment.
【００１２】５は金属膜４を酸化処理することにより生
成した金属酸化物半導体である。図１ (a)の構造に対し
て，保護膜（図示せず）を形成して引き出し電極を形成
することにより，例えば電極金属２をゲート電極とする
薄膜トランジスタを作成することができる。Reference numeral 5 is a metal oxide semiconductor produced by oxidizing the metal film 4. By forming a lead-out electrode by forming a protective film (not shown) on the structure of FIG. 1A, for example, a thin film transistor having the electrode metal 2 as a gate electrode can be manufactured.
【００１３】図１ (b)は図１ (a)の構造の製造方法を示
す。図示の番号の順に製造方法を説明する。
(1) 絶縁物，シリコン半導体等の基板１に電極金属２
を形成し，絶縁膜３で被覆する。FIG. 1 (b) shows a method of manufacturing the structure of FIG. 1 (a). The manufacturing method will be described in the order of the numbers shown. (1) Electrode metal 2 on substrate 1 of insulator, silicon semiconductor, etc.
Are formed and covered with the insulating film 3.
【００１４】(2) 絶縁膜３の上に，例えば，銅，亜鉛
等の金属膜４を形成する。
(3) 金属膜４の一部の領域をイオン注入，熱酸化，プ
ラズマ酸化等で酸化処理する。(2) A metal film 4 of, for example, copper or zinc is formed on the insulating film 3. (3) Partial region of the metal film 4 is oxidized by ion implantation, thermal oxidation, plasma oxidation or the like.
【００１５】さらに，必要ならば，金属酸化物半導体領
域に対して，水素を導入する等で金属酸化物半導体の過
剰な酸素による欠陥を制御して，キャリヤ密度および導
電型を制御するようにする。あるいは，酸素が不足した
ことにより欠陥を生じている場合には，酸素もしくは水
素等を導入することにより欠陥を制御して，キャリヤ密
度および導電型を制御するようにする。Further, if necessary, hydrogen is introduced into the metal oxide semiconductor region to control defects in the metal oxide semiconductor due to excess oxygen, thereby controlling the carrier density and conductivity type. . Alternatively, when a defect is caused by lack of oxygen, the defect is controlled by introducing oxygen or hydrogen, and the carrier density and conductivity type are controlled.
【００１６】図２は本発明の基本構成(2) であり，ｐｎ
接合を持つ金属酸化物半導体についての原理的構造と製
造方法を説明するものである。図２ (a)は原理的構造で
あり，図２ (b)はその製造方法の原理を示す。FIG. 2 shows a basic configuration (2) of the present invention, which is pn
The principle structure and manufacturing method of a metal oxide semiconductor having a junction will be described. Fig. 2 (a) shows the principle structure, and Fig. 2 (b) shows the principle of the manufacturing method.
【００１７】図２ (a)において，１１は基板である１３
は金属酸化物半導体であって，第１の導電型の半導体で
ある。In FIG. 2A, 11 is a substrate 13
Is a metal oxide semiconductor, which is a semiconductor of the first conductivity type.
【００１８】１５は接合部である。１６は金属酸化物半
導体であって，第２の導電型の半導体である。図２ (a)
に対して，保護膜，電極を形成することによりダイオー
ドとし，あるいは接合の数を増やしてトランジスタとす
る等で半導体装置とすることができる。Reference numeral 15 is a joint. Reference numeral 16 is a metal oxide semiconductor, which is a second conductivity type semiconductor. Figure 2 (a)
On the other hand, a semiconductor device can be obtained by forming a protective film and electrodes to form a diode, or increasing the number of junctions to form a transistor.
【００１９】図２ (b)は図２ (a)の原理的構造の製造方
法である。図２(b) において，１１は基板である。FIG. 2 (b) shows a method of manufacturing the principle structure of FIG. 2 (a). In FIG. 2 (b), 11 is a substrate.
【００２０】１２は金属膜であって，銅，亜鉛等の酸化
処理することにより半導体となるものである。１３は金
属酸化物半導体（第１の導電体）である。Reference numeral 12 is a metal film, which becomes a semiconductor by oxidizing copper, zinc or the like. Reference numeral 13 is a metal oxide semiconductor (first conductor).
【００２１】１４は真性半導体化領域であって，金属酸
化物半導体１３に水素等を照射し，金属酸化物半導体
（第１の導電体）１３の過剰な酸素に対して欠陥を除去
し，真性半導体化した領域である。あるいは酸素が不足
して欠陥を生じている場合には酸素もしくは水素等を導
入して欠陥を除去し，真性半導体化したものである。Reference numeral 14 denotes an intrinsic semiconductor region, which irradiates the metal oxide semiconductor 13 with hydrogen or the like to remove defects from excess oxygen in the metal oxide semiconductor (first conductor) 13, This is a semiconductorized region. Alternatively, when oxygen is insufficient and a defect is generated, oxygen or hydrogen or the like is introduced to remove the defect and make it an intrinsic semiconductor.
【００２２】１５は接合部である。１６は第２の導電型
の金属酸化物半導体であって，真性半導体化領域１４に
第２導電型とする不純物（例えば，塩素等）をドープし
た金属酸化物半導体装置である。Reference numeral 15 is a joint portion. Reference numeral 16 denotes a second conductivity type metal oxide semiconductor, which is a metal oxide semiconductor device in which the intrinsic semiconductor region 14 is doped with an impurity (for example, chlorine) of the second conductivity type.
【００２３】図２ (b)により，図２ (a)の薄膜半導体装
置の製造方法について説明する。
(1) 基板１１に金属膜１２を形成する（例えば，厚さ
０．３μｍ）。
(2) 金属膜１２を酸化処理し，第１の導電体型の金属
酸化物半導体１３とする。A method of manufacturing the thin film semiconductor device of FIG. 2A will be described with reference to FIG. (1) The metal film 12 is formed on the substrate 11 (for example, the thickness is 0.3 μm). (2) The metal film 12 is oxidized to form the first conductor type metal oxide semiconductor 13.
【００２４】(3) 金属酸化物半導体１３の酸素の過不
足による欠陥を除去する等で真性半導体化する。
(4) 真性半導体化領域１４に第２の導電型の不純物を
ドープし，第１の導電型の金属酸化物半導体１３とｐｎ
接合を形成する。(3) The metal oxide semiconductor 13 is made into an intrinsic semiconductor by removing defects due to excess and deficiency of oxygen. (4) The intrinsic conductivity region 14 is doped with impurities of the second conductivity type, and the metal oxide semiconductor 13 of the first conductivity type and the pn
Form a bond.
【００２５】[0025]
【作用】本発明によれば，低温処理により高移動度の薄
膜トランジスタおよびｐｎ接合を持つ金属酸化物薄膜半
導体を低コストで製造することができる。また，後述す
るが，金属化酸化物半導体は高温の熱処理にも耐えると
ともに高温アニールにより移動度も高くなるので，高温
熱処理する集積回路技術に対しても新しい適用を可能と
するものである。According to the present invention, a thin film transistor having a high mobility and a metal oxide thin film semiconductor having a pn junction can be manufactured at low cost by low temperature treatment. Further, as will be described later, the metallized oxide semiconductor withstands high-temperature heat treatment and has high mobility due to high-temperature annealing, so that it can be newly applied to integrated circuit technology for high-temperature heat treatment.
【００２６】なお，図１の本発明の基本構成(1) では，
ゲート電極を持つ構造の薄膜トランジスタについて説明
したが，メタルベーストランジスタ等の他の構造の薄膜
トランジスタに対しても適用できるものである。また，
図１の本発明の基本構成によれば金属酸化物半導体の幅
をトンネル電流が流れる程度にすることができるので，
この点からも本発明によれば，微小電流で高速動作する
新しい集積回路技術を切り開くことができるものであ
る。In the basic configuration (1) of the present invention shown in FIG.
Although the thin film transistor having a structure having a gate electrode has been described, the present invention can be applied to a thin film transistor having another structure such as a metal base transistor. Also,
According to the basic configuration of the present invention shown in FIG. 1, the width of the metal oxide semiconductor can be set to the extent that a tunnel current flows.
From this point as well, according to the present invention, a new integrated circuit technology that operates at high speed with a small current can be opened up.
【００２７】[0027]
【実施例】本発明の金属酸化物半導体として亜酸化銅を
使用する場合について実施例を説明する。EXAMPLE An example of using cuprous oxide as the metal oxide semiconductor of the present invention will be described.
【００２８】図３は本発明で使用する酸化物半導体の特
性の例を示す図である。図３は，アルゴン中で，銅薄膜
を室温でスパッタ法により堆積した後，その銅薄膜を２
５０°Ｃ前後の温度で熱酸化して得られた亜酸化銅半導
体のキャリヤ密度をホール効果により求まる移動度の関
係を実測した結果を示したものである。FIG. 3 is a diagram showing an example of characteristics of the oxide semiconductor used in the present invention. Figure 3 shows that after depositing a copper thin film by sputtering at room temperature in argon,
It shows the result of actually measuring the relationship of the mobility obtained by the Hall effect for the carrier density of the cuprous oxide semiconductor obtained by thermal oxidation at a temperature of about 50 ° C.
【００２９】この時，亜酸化銅の極性は，ｐ型である。
キャリヤ密度は１０16ｃｍ-3以下と小さく，移動度は数
１０ｃｍ2 ／Ｖ・ｓである。このキャリヤは過剰酸素に
よる欠陥が作るアクセプタから供給されているものであ
るが，この方法で作られた亜酸化銅のキャリヤ密度は低
いので，酸素に作用して過剰酸素の欠陥を除去できる水
素，ナトリウム，カリウム，銅，亜鉛などを１０11から
１０12ｃｍ-2ほどイオン注入することで容易にキャリヤ
密度の制御が可能である。イオン注入のドープ量がこの
ように低いので，イオン注入によって発生する欠陥も少
なく抑えることができ，４００°Ｃ程度の以下の低温の
熱処理でも，十分にイオン注入による欠陥を除去するこ
とができる。At this time, the polarity of cuprous oxide is p-type.
The carrier density is as small as 10 16 cm −3 or less, and the mobility is several 10 cm 2 / V · s. This carrier is supplied from an acceptor created by defects due to excess oxygen, but since the carrier density of cuprous oxide created by this method is low, hydrogen that can act on oxygen to remove defects of excess oxygen, It is possible to easily control the carrier density by ion-implanting sodium, potassium, copper, zinc or the like at about 10 11 to 10 12 cm -2 . Since the doping amount of the ion implantation is so low, the defects generated by the ion implantation can be suppressed, and the defects caused by the ion implantation can be sufficiently removed even by the low temperature heat treatment of about 400 ° C. or less.
【００３０】本発明は，このような亜酸化銅等の酸化物
半導体の持つ性質に着目し，これを用いて低温で薄膜ト
ランジスタを製造するようにしたものである。なお，本
発明は，亜酸化銅のみならず，酸化亜鉛，酸化アルミニ
ウム，酸化タンタル等の他の金属酸化物半導体に対して
も適用できるものである。The present invention focuses on the properties of such an oxide semiconductor such as cuprous oxide, and uses this to manufacture a thin film transistor at a low temperature. The present invention can be applied not only to cuprous oxide but also to other metal oxide semiconductors such as zinc oxide, aluminum oxide and tantalum oxide.
【００３１】図４は本発明の実施例１であって，薄膜ト
ランジスタである。図４において，２１はガラス基板で
ある（図１ (a)の基板１に相当する）。FIG. 4 shows Example 1 of the present invention, which is a thin film transistor. In FIG. 4, 21 is a glass substrate (corresponding to the substrate 1 in FIG. 1A).
【００３２】２２はゲート電極である（図１ (a)の電極
金属２に相当する）。２３はゲート絶縁膜である（図１
(a)の絶縁膜３に相当する）。２４，２４’は金属膜で
あって，ソース，ドレイン電極である。Reference numeral 22 is a gate electrode (corresponding to the electrode metal 2 in FIG. 1 (a)). Reference numeral 23 is a gate insulating film (see FIG. 1).
It corresponds to the insulating film 3 in (a)). 24 and 24 'are metal films, which are source and drain electrodes.
【００３３】２５は金属酸化物半導体であって，金属膜
２４，２４’を酸化処理して得られた金属半導体であ
る。２６は絶縁膜である。Reference numeral 25 is a metal oxide semiconductor, which is obtained by oxidizing the metal films 24 and 24 '. Reference numeral 26 is an insulating film.
【００３４】図４において，絶縁膜２６，金属酸化物半
導体２５の表面にさらに絶縁保護膜（図５工程(6) 参
照）を形成し，ソース，ドレイン電極２４，２４’に接
続する電極を引き出すことによりゲート電極２２を持つ
薄膜トランジスタとする。In FIG. 4, an insulating protective film (see step (6) in FIG. 5) is further formed on the surfaces of the insulating film 26 and the metal oxide semiconductor 25, and the electrodes connected to the source and drain electrodes 24 and 24 'are drawn out. As a result, a thin film transistor having the gate electrode 22 is obtained.
【００３５】図５は図４の薄膜トランジスタの製造方法
を示す。
工程(1) ガラス基板２１にクロムあるいはアルミニュ
ーム等の金属を堆積し，それをフォトレジスト加工によ
り，ゲート電極となるように成型する。この工程で，ま
ず，第１のパターンマスクを用いる。また，本発明で
は，全て低温度で処理するのでここに使用するガラスは
高価格の高融点ガラスである必要はない。FIG. 5 shows a method of manufacturing the thin film transistor of FIG. Step (1) A metal such as chromium or aluminum is deposited on the glass substrate 21 and is formed into a gate electrode by photoresist processing. In this step, first, the first pattern mask is used. Further, in the present invention, since all the processing is performed at a low temperature, the glass used here does not need to be a high-priced glass having a high melting point.
【００３６】工程(2) 全体にシリコン酸化膜あるいは
シリコン窒化膜等のゲート絶縁膜を堆積する。
工程(3) 銅等の金属酸化物半導体となる薄膜の金属膜
２４，２４’を堆積し，フォトレジスト加工により，ソ
ース，ドレイン部を含めたトランジスタのパターン，お
よびソース，ドレインからの接続配線部のパターン（図
示せず）も含めて成型する。この時，第２のパターンマ
スクを用いる。A gate insulating film such as a silicon oxide film or a silicon nitride film is deposited on the entire step (2). Step (3) Deposit thin metal films 24 and 24 ′ that will be a metal oxide semiconductor such as copper, and perform photoresist processing to form transistor patterns including source and drain parts, and connection wiring parts from the source and drain parts. The pattern (not shown) is also molded. At this time, the second pattern mask is used.
【００３７】工程(4) 次の酸化工程のマスクとなる
膜，例えばシリコン窒化膜などを全体に堆積する。この
時，フォトレジスト膜を用いることもできる。そして，
これらの膜を堆積した後に，ガラス基板２１の裏面より
露光し，工程(1) で作成したゲート電極のパターンをマ
スクとしてフォトレジスト膜を露光し，その膜にフォト
レジスト加工により孔を開ける。この工程で，薄膜トラ
ンジスタのチャネル部とゲート電極２２を自己整合させ
る。Step (4) A film serving as a mask for the next oxidation step, for example, a silicon nitride film is deposited on the entire surface. At this time, a photoresist film may be used. And
After these films are deposited, the back surface of the glass substrate 21 is exposed to light, the photoresist film is exposed using the pattern of the gate electrode formed in step (1) as a mask, and holes are formed in the film by photoresist processing. In this step, the channel portion of the thin film transistor and the gate electrode 22 are self-aligned.
【００３８】工程(5) では，２００°Ｃから４００°Ｃ
程度の間の低温で全体を熱酸化，もしくはプラズマ酸化
などをすることにより，開口から露出した金属膜２４を
酸化し，金属酸化物半導体に変化させる（工程(4) で絶
縁膜２６には孔を開けられている）。In step (5), the temperature is from 200 ° C to 400 ° C.
The metal film 24 exposed from the opening is oxidized by thermal oxidation or plasma oxidation of the whole at a low temperature of about a certain degree to change into a metal oxide semiconductor (the insulating film 26 has a hole in the step (4)). Have been opened).
【００３９】工程(6) 形成されたトランジスタの全体
をシリコン窒化膜等の絶縁膜で被覆し，かつフォトレジ
スト加工により電極取り出し部に孔を開ける。この時，
第３のマスクパターンを用いる。Step (6) The formed transistor is entirely covered with an insulating film such as a silicon nitride film, and a hole is formed in the electrode extraction portion by photoresist processing. At this time,
A third mask pattern is used.
【００４０】上記のように，本実施例によればマスクパ
ターンを３枚で薄膜トランジスタを製造することができ
る。なお，上記の工程において，工程(5) の金属膜の酸
化は，酸素イオン注入の他，熱酸化，プラズマ酸化，酸
素イオン照射，レーザ 酸素ドーピング等の手段により
行うことができる。As described above, according to this embodiment, a thin film transistor can be manufactured with three mask patterns. In the above process, the oxidation of the metal film in the process (5) can be performed by means of oxygen ion implantation, thermal oxidation, plasma oxidation, oxygen ion irradiation, laser oxygen doping and the like.
【００４１】また，酸素欠陥を除去することによりキャ
リヤ密度，導電型を制御したり，あるいは不純物ドーピ
ングによりｐ，ｎ型の導電型の制御，抵抗率等の制御を
する必要がある場合には，工程（５）と工程（６）の間
で，イオン注入法，イオンドーピング法，熱拡散法，プ
ラズマ熱酸化法，あるいはレーザドーピング法等の手段
で行うことができる。Further, when it is necessary to control the carrier density and conductivity type by removing oxygen defects, or to control the p and n conductivity types and the resistivity by impurity doping, Between step (5) and step (6), it can be performed by means such as an ion implantation method, an ion doping method, a thermal diffusion method, a plasma thermal oxidation method, or a laser doping method.
【００４２】このとき，酸素過剰による欠陥（亜酸化銅
の場合）を補償する目的で水素，リチウム，ナトリウ
ム，カリウム，銅，インジウム，亜鉛等の１種もしくは
複数種の不純物を金属酸化物半導体に導入し，その導体
のキャリヤ密度および導電型を制御することができる。
酸素を照射した場合には欠陥が増え抵抗を増加させる。At this time, one or more kinds of impurities such as hydrogen, lithium, sodium, potassium, copper, indium and zinc are added to the metal oxide semiconductor for the purpose of compensating for defects (in the case of cuprous oxide) due to excess oxygen. Can be introduced to control the carrier density and conductivity type of the conductor.
When irradiated with oxygen, defects increase and resistance increases.
【００４３】さらに，上記のようにキャリヤ密度および
導電型が制御された金属酸化物半導体に弗素，塩素，リ
ン，砒素，アンチモン等の元素を導入することで導電型
を制御することもできる。Further, the conductivity type can be controlled by introducing an element such as fluorine, chlorine, phosphorus, arsenic or antimony into the metal oxide semiconductor whose carrier density and conductivity type are controlled as described above.
【００４４】図６は本実施例１の方法で作成された薄膜
トランジスタの特性の例である。図６の特性の薄膜トラ
ンジスタは次のようなものである。金属酸化物半導体は
亜酸化銅である。ゲート絶縁膜はシリコン酸化膜であ
り，ゲート電極は低抵抗の結晶シリコンである。FIG. 6 shows an example of characteristics of the thin film transistor manufactured by the method of the first embodiment. The thin film transistor having the characteristics shown in FIG. 6 is as follows. The metal oxide semiconductor is cuprous oxide. The gate insulating film is a silicon oxide film, and the gate electrode is low resistance crystalline silicon.
【００４５】亜酸化銅は，銅薄膜を室温でアルゴンガス
を用いたスパッタ法により約８０秒ほどの時間で堆積し
た銅薄膜を３５０°Ｃで約１８分間，熱酸化することに
より作られている。この薄膜トランジスタにおいては，
チャネル長Ｌ＝５０μｍ，チャネル幅１７５μｍであ
る。図６は薄膜トランジスタのソース・ドレイン間電流
ＩDSの平方根をゲート・ソース間電圧ＶGSの関数として
その特性を示している。この傾きから移動度を求めるこ
とができる。図６の例は移動度が約１００ｃｍ2／Ｖｓ
である。Cuprous oxide is produced by thermally oxidizing a copper thin film deposited at 350 ° C. for about 18 minutes at room temperature by a sputtering method using argon gas for about 80 seconds. . In this thin film transistor,
The channel length L = 50 μm and the channel width 175 μm. FIG. 6 shows the characteristics of the square root of the source-drain current I DS of the thin film transistor as a function of the gate-source voltage V GS . The mobility can be obtained from this inclination. In the example of FIG. 6, the mobility is about 100 cm 2 / Vs
Is.
【００４６】本発明によれば，移動度が数１０ｃｍ2 ／
Ｖｓから１００ｃｍ2 ／Ｖｓ近くまでの大きなものが得
られる。図７は本発明の実施例２であり，メタルベース
トランジスタに本発明を適用したものである。According to the present invention, the mobility is several tens cm 2 /
Large ones from Vs to near 100 cm 2 / Vs can be obtained. 7 is a second embodiment of the present invention, in which the present invention is applied to a metal base transistor.
【００４７】図７ (a)はメタルベーストランジスタの構
造であり，図７ (b)，図７ (c)はその製造方法を説明す
るものである。図７ (a)において，３０は基板である。FIG. 7 (a) shows the structure of a metal base transistor, and FIGS. 7 (b) and 7 (c) explain the manufacturing method thereof. In FIG. 7A, reference numeral 30 is a substrate.
【００４８】３０’は金属膜（亜酸化銅）である。３１
は金属酸化物半導体であって，亜酸化銅（ｐ型）であり
エミッタである。３２は金属ベースであって，銅である
（厚さ約１０Å〜５０Å）。30 'is a metal film (cuprous oxide). 31
Is a metal oxide semiconductor, is cuprous oxide (p-type), and is an emitter. 32 is a metal base and is copper (thickness is about 10Å to 50Å).
【００４９】３３は金属酸化物半導体であって，亜酸化
銅（ｐ型）でありコレクタである。図７ (a)において，
電極配線は図示を省略されている。図７ (b)により，図
７ (a)のメタルベーストランジスタの製造方法を説明す
る。金属膜として銅を使用するものとする。
(1) 基板（ガラス，石英，シリコン等）３０に銅を厚
さ約０．３μｍ程度にスパッタ法により形成する。A metal oxide semiconductor 33 is cuprous oxide (p-type) and a collector. In Figure 7 (a),
The electrode wiring is not shown. A method of manufacturing the metal base transistor of FIG. 7A will be described with reference to FIG. Copper is used as the metal film. (1) Copper is formed on a substrate (glass, quartz, silicon, etc.) 30 to a thickness of about 0.3 μm by a sputtering method.
【００５０】(2) 電気炉中で銅３０”の表面を熱酸化
し，厚さ０．１μｍだけ銅３０”を消費して約０．２μ
ｍの厚さの亜酸化銅の膜３１’を形成する。このとき，
２５０°Ｃで約１５分ぐらい乾燥酸素中で熱酸化する。(2) Thermally oxidize the surface of copper 30 ″ in an electric furnace to consume copper 0.2 ″ with a thickness of 0.1 μm.
A cuprous oxide film 31 'having a thickness of m is formed. At this time,
Thermally oxidize in dry oxygen at 250 ° C for about 15 minutes.
【００５１】(3) これに再度，銅を室温で堆積する。
膜厚は約０．１μｍである。
(4) 再び，電気炉中で，新たに堆積した銅の表面のう
ちのほとんど全ての部分を熱酸化して亜酸化銅に変え
る。このとき，酸化時間を微妙に制御して極く薄い銅の
膜３２’（厚さ０．００１〜０．００５μｍ）を残して
メタルベーストランジスタのベースとする。この時の熱
酸化条件は，２００°Ｃ，１６０分前後である。(3) Copper is again deposited at room temperature on this.
The film thickness is about 0.1 μm. (4) Again, in the electric furnace, almost all of the newly deposited copper surface is thermally oxidized and converted to cuprous oxide. At this time, the oxidation time is delicately controlled to leave the extremely thin copper film 32 '(thickness 0.001 to 0.005 .mu.m) as the base of the metal base transistor. The thermal oxidation conditions at this time are 200 ° C. and about 160 minutes.
【００５２】図７ (b)における酸化の過程において，図
７ (c)(2) に示すように，亜酸化銅３３’の表面を窒化
シリコン膜で被覆すると，図７ (c)(3) のようにベース
電極の取り出し口を容易にすることができる。In the process of oxidation in FIG. 7 (b), as shown in FIG. 7 (c) (2), when the surface of the cuprous oxide 33 'is covered with a silicon nitride film, the result of FIG. 7 (c) (3) As described above, it is possible to easily take out the base electrode.
【００５３】図８は本発明の実施例３である。図８は，
ゲート電極を備える薄膜トランジスタにおいてソース・
ドレイン電極間の金属絶縁体半導体の幅をトンネル電流
が流れる程度に狭くし，ゲート電圧によってトンネル電
流を制御するようにしたものである。FIG. 8 shows a third embodiment of the present invention. Figure 8 shows
In a thin film transistor having a gate electrode, the source
The width of the metal insulator semiconductor between the drain electrodes is narrowed to the extent that a tunnel current flows, and the tunnel current is controlled by the gate voltage.
【００５４】図８ (a)は構造であり，図８ (b)はその特
性の例である。
図８ (a)
１２１は基板であって，ガラス，シリコン等である。FIG. 8A shows the structure, and FIG. 8B shows an example of its characteristics. Reference numeral 121 in FIG. 8A is a substrate, which is made of glass, silicon, or the like.
【００５５】１２２はゲート電極である。１２３はゲー
ト絶縁膜である。１２４，１２４’は金属膜であって，
ソース電極，ドレイン電極となるものである。122 is a gate electrode. Reference numeral 123 is a gate insulating film. 124 and 124 'are metal films,
It will be the source electrode and the drain electrode.
【００５６】１２５は金属酸化物半導体である。１２６
はギャップであって，金属酸化物半導体の１２５の最小
幅（金属膜１２４と金属膜１２４’の間の最小幅）であ
って，金属膜（ドレイン電極）１２４と金属膜（ソース
電極）１２４’間の金属酸化物半導体１２５にトンネル
電流が流れる程度のものである。例えば，約０．００５
〜０．０１μｍ程度である。Reference numeral 125 is a metal oxide semiconductor. 126
Is a gap, which is the minimum width of the metal oxide semiconductor 125 (the minimum width between the metal film 124 and the metal film 124 ′), and the metal film (drain electrode) 124 and the metal film (source electrode) 124 ′. A tunnel current flows through the metal oxide semiconductor 125 between them. For example, about 0.005
Is about 0.01 μm.
【００５７】このようにすることにより，ゲート電極１
２２の電圧によるソース・ドレイン間電流ＩDSの急峻な
立ち上がり特性を得ることができる。そのため，動作が
高速化し，微小電流で動作することができる。By doing so, the gate electrode 1
It is possible to obtain a steep rise characteristic of the source-drain current I DS due to the voltage of 22. Therefore, the operation speed is increased, and it is possible to operate with a small current.
【００５８】図８ (b)は図８ (a)の薄膜トランジスタの
特性の例である。横軸はソース電極１２４’とドレイン
電極１２４間の電圧ＶDSであり, 縦軸はソース電極１２
４’とドレイン電極１２４間の電流ＩDSである。パラメ
ータはゲート電圧ＶGS（ソース電極１２４’とゲート電
極１２４間電圧）である。FIG. 8 (b) shows an example of characteristics of the thin film transistor of FIG. 8 (a). The horizontal axis is the voltage V DS between the source electrode 124 'and the drain electrode 124, and the vertical axis is the source electrode 12'.
It is a current I DS between 4 ′ and the drain electrode 124. The parameter is the gate voltage V GS (voltage between the source electrode 124 ′ and the gate electrode 124).
【００５９】例えば，ゲート電圧をＶGS’としておいて
ＶDSをしだいに大きくするとＶDS’の電圧でソース電極
１２４’とドレイン電極１２４の間にトンネル電流が流
れ，図８ (b)のように立ち上がり特性の急峻な特性が得
られる（ＶGSで制御することもできる）。For example, if the gate voltage is set to V GS ′ and V DS is gradually increased, a tunnel current flows between the source electrode 124 ′ and the drain electrode 124 at the voltage of V DS ′, as shown in FIG. 8B. A steep rise characteristic can be obtained (it can also be controlled by V GS ).
【００６０】図９ (a)は図９の本発明の実施例３の製造
方法を示す図である。図９ (a)，図９ (b)，図９ (c)に
おいて，１２１は基板である。FIG. 9 (a) is a diagram showing a manufacturing method of the third embodiment of the present invention shown in FIG. In FIGS. 9 (a), 9 (b) and 9 (c), 121 is a substrate.
【００６１】１２２はゲート電極である。１２３はゲー
ト絶縁膜である。１２４，１２４’は金属膜であって，
ソース電極，ドレイン電極となるものである。Reference numeral 122 is a gate electrode. Reference numeral 123 is a gate insulating film. 124 and 124 'are metal films,
It will be the source electrode and the drain electrode.
【００６２】１２５は金属酸化物半導体である。１２８
はマスク用絶縁膜であって，窒化シリコン等の膜であ
る。図９ (a)の(2) は，エッチングによりマスク用絶縁
膜１２８に開口を設けた後の状態を示す。Reference numeral 125 is a metal oxide semiconductor. 128
Is an insulating film for a mask and is a film of silicon nitride or the like. FIG. 9A (2) shows a state after the opening is provided in the mask insulating film 128 by etching.
【００６３】１３０はフォトレジストマスクである。図
９ (a)において，
(1) 基板１２１にゲート電極を形成し，さらにその全
面をゲート絶縁膜１２３で被覆する（厚さ約０．０２μ
ｍ）。その上に，銅，亜鉛，アルミニュウム等の金属膜
１２４をスパッタ法等で形成する（厚さ約０．０５μ
ｍ）。
(2) 金属膜１２４の全面にマスク用絶縁膜１２８形成
する。その上にフォトレジストを塗布しマスクを使用し
て露光し，フォトレジストマスク１３０を作る。そし
て，フォトレジストマスク１３０によりマスク用絶縁膜
をエッチングし，図９ (a)の(2) のような開口部を持つ
マスク用絶縁膜１２８を作成する。このとき，エッチン
グ特性により図８ (b)のように上部で広く，下部で狭い
開口が得られるので，エッチング時間を調整することに
より，マスク用絶縁膜１２８の開口の下部をリソグラフ
ィの限界より狭くすることができる。Reference numeral 130 is a photoresist mask. In FIG. 9A, (1) a gate electrode is formed on the substrate 121, and the entire surface is covered with a gate insulating film 123 (thickness: about 0.02 μm).
m). A metal film 124 of copper, zinc, aluminum or the like is formed thereon by sputtering or the like (thickness: about 0.05 μm).
m). (2) A mask insulating film 128 is formed on the entire surface of the metal film 124. A photoresist is applied thereon and exposed using a mask to form a photoresist mask 130. Then, the mask insulating film is etched by the photoresist mask 130 to form a mask insulating film 128 having an opening as shown in FIG. 9 (a) (2). At this time, as shown in FIG. 8B, a wide opening is obtained in the upper part and a narrow opening is obtained in the lower part due to the etching characteristics. Therefore, by adjusting the etching time, the lower part of the opening of the mask insulating film 128 is narrower than the limit of lithography. can do.
【００６４】(3) (2) の状態において，マスク用絶縁
膜１２８をマスクとして金属膜１２４を酸化し，マスク
用絶縁膜を除去する。このとき，酸化の形状は，図９
(c)に示すように開口部の上部で広く，下部で狭い形状
となる。この性質を利用して，金属酸化物半導体１２５
の最小幅をトンネル電流が流れる程度の狭いものとする
ことができる。(3) In the state of (2), the metal film 124 is oxidized by using the mask insulating film 128 as a mask, and the mask insulating film is removed. At this time, the shape of the oxidation is shown in FIG.
As shown in (c), the shape is wide at the top of the opening and narrow at the bottom. Utilizing this property, the metal oxide semiconductor 125
The minimum width of can be narrow enough to allow the tunnel current to flow.
【００６５】図１０は本発明の実施例４であって，金属
酸化物半導体によりバイポーラトランジスタを構成した
別の実施例である。本発明は，金属絶縁物半導体の酸素
の過不足による欠陥を補償する目的で金属絶縁物半導体
に不純物を導入することにより，キャリヤ密度および導
電型を制御し，半導体装置へ適用できるようにしたもの
である。例えば，不純物として水素，リチウム，ナトリ
ウム，カリウム，銅，インジウム等を金属酸化物半導体
に導入することにより亜酸化銅等の金属酸化物半導体の
過剰な酸素による結果を除去し，キャリヤ密度，導電型
を制御することができる。そのようにキャリヤ密度およ
び導電型を制御した金属半導体に対して，さらに，弗
素，塩素，リン，砒素，アンチモン等の元素を導入する
ことで導電型を制御することにより良好なｐｎ接合を作
成することができる。FIG. 10 is a fourth embodiment of the present invention, which is another embodiment in which a bipolar transistor is made of a metal oxide semiconductor. The present invention controls carrier density and conductivity type by introducing impurities into a metal insulator semiconductor for the purpose of compensating for defects due to excess or deficiency of oxygen in the metal insulator semiconductor, and can be applied to a semiconductor device. Is. For example, by introducing hydrogen, lithium, sodium, potassium, copper, indium, or the like as impurities into a metal oxide semiconductor, the result of excess oxygen in a metal oxide semiconductor such as cuprous oxide can be removed. Can be controlled. By introducing elements such as fluorine, chlorine, phosphorus, arsenic, and antimony into the metal semiconductor whose carrier density and conductivity type are controlled as described above, a good pn junction is formed by controlling the conductivity type. be able to.
【００６６】図１０において，６０は基板であって，ガ
ラス，石英，シリコン等である。６０’は金属膜（銅）
である。In FIG. 10, reference numeral 60 denotes a substrate, which is glass, quartz, silicon or the like. 60 'is a metal film (copper)
Is.
【００６７】６１は金属酸化物半導体（ｐ型）であっ
て，亜酸化銅でありコレクタである。６２は金属酸化物
半導体（ｎ型）であって，亜酸化銅でありベースであ
る。６３は金属酸化物半導体（ｐ型）であって，亜酸化
銅でありエミッタである。Reference numeral 61 is a metal oxide semiconductor (p-type), which is cuprous oxide and is a collector. Reference numeral 62 denotes a metal oxide semiconductor (n-type), which is cuprous oxide and is a base. 63 is a metal oxide semiconductor (p-type), which is cuprous oxide and is an emitter.
【００６８】図１０において，電極の引き出し線は省略
されている。図１０のバイポーラトランジスタの製造方
法について説明する。
(1) 基板（ガラス，シリコン等）６０に室温で銅をス
パッタ法により堆積する。膜厚は下部に電極として０．
２μｍの銅を残したまま，全て厚さ０．８μｍの亜酸化
銅とするため，０．６μｍ程度である。In FIG. 10, the lead lines of the electrodes are omitted. A method of manufacturing the bipolar transistor of FIG. 10 will be described. (1) Copper is deposited on a substrate (glass, silicon, etc.) 60 at room temperature by a sputtering method. The film thickness is 0.
The thickness is about 0.6 μm because the thickness of the cuprous oxide is 0.8 μm while leaving the copper of 2 μm.
【００６９】(2) ２５０°Ｃ，６時間程度乾燥酸素中
で熱酸化し，０．８μｍの亜酸化銅の膜を作る。２５０
°Ｃでは絶縁体である酸化銅（本発明者等の研究により
ＣｕＯ）が亜酸化銅（Ｃｕ2 Ｏ）の代わりに作られてし
まうことはないことが明きらかにされている。３５０°
Ｃ以上の熱酸化では絶縁性の酸化銅が表面に生じる）。(2) Thermal oxidation is performed in dry oxygen at 250 ° C. for about 6 hours to form a 0.8 μm cuprous oxide film. 250
At ° C, it has been clarified that copper oxide (CuO), which is an insulator, is not produced in place of cuprous oxide (Cu 2 O) as a result of research conducted by the present inventors. 350 °
Insulating copper oxide is generated on the surface by thermal oxidation of C or more).
【００７０】(3) この亜酸化銅をアルゴンの雰囲気中
で８００°Ｃ，３０分の熱処理をすることにより特性を
向上させる（本発明者等の研究により，２５０°Ｃの熱
酸化で作られた亜酸化銅は８００°Ｃの熱処理にも耐え
られ，さらにモビリティ等の特性も向上することが明ら
かにされている（図１１参照））。(3) The characteristics of this cuprous oxide are improved by heat-treating it at 800 ° C. for 30 minutes in an atmosphere of argon (according to the study by the present inventors, it was produced by thermal oxidation at 250 ° C. It has been clarified that cuprous oxide can withstand a heat treatment at 800 ° C and further improve characteristics such as mobility (see Fig. 11)).
【００７１】(4) Ｌｉ，Ｎａ，Ｋなどの金属，Ｉｎな
どの銅サイトに入って不足銅成分を補う元素をイオン注
入し，その後のアルゴン雰囲気中８００°Ｃ，３０分の
熱処理により，ｎ型亜酸化銅を形成する。この時，ｎ型
を形成する不純物としては他に，Ｓｅ，Ｓ，Ｆ，Ｃｌ，
Ｂｒ，Ｉ等が考えられる。また，Ｐ，Ｓｉ，Ａｓ等も考
えられる。(4) Metals such as Li, Na, and K, and elements such as In that enter copper sites to compensate for the deficient copper component are ion-implanted, and then heat-treated in an argon atmosphere at 800 ° C. for 30 minutes to obtain n. Form type cuprous oxide. At this time, Se, S, F, Cl,
Br, I, etc. are considered. Further, P, Si, As, etc. are also conceivable.
【００７２】(5) さらに(4) で作られたｎ型層の表面
部を再度ｐ型に反転する目的でイオン注入を行う。その
後，８００°Ｃ，３０分の熱処理を行う。
・なお，上記において，(3) ，(4) ，(5) は，図１０
(b)のようにイオン注入しておき１回の熱処理で行うこ
とができる。(5) Further, ion implantation is performed for the purpose of reversing the surface portion of the n-type layer formed in (4) to p-type again. After that, heat treatment is performed at 800 ° C. for 30 minutes.・ In the above, (3), (4), and (5) are shown in FIG.
As in (b), ion implantation can be performed and heat treatment can be performed once.
【００７３】また，工程(4) までとしてダイオードとし
ても良い。図１１は本発明で使用する亜酸化銅のアニー
ル温度による亜酸化銅の特性変化を示す図である。A diode may be used up to the step (4). FIG. 11 is a diagram showing changes in the characteristics of cuprous oxide depending on the annealing temperature of cuprous oxide used in the present invention.
【００７４】図１１は，アニール時間３０分として，ア
ニール温度により亜酸化銅のホール移動度，キャリヤ密
度，抵抗の変化をアニール前とアニール後により比較し
たものである。横軸はアニール温度である。FIG. 11 is a comparison of changes in hole mobility, carrier density and resistance of cuprous oxide before and after annealing with annealing temperature of 30 minutes. The horizontal axis is the annealing temperature.
【００７５】図１１に示すように，亜酸化銅はアニール
温度によりアニール前に比較して良好な特性に変化する
ことが示されている。特に，８００°Ｃ程度の高温でも
アニールに耐え，移動度も高くなることから，高温処理
の半導集積回路としても利用できることが示されてい
る。As shown in FIG. 11, it is shown that cuprous oxide changes to better characteristics depending on the annealing temperature as compared with that before annealing. In particular, since it withstands annealing even at a high temperature of about 800 ° C. and has a high mobility, it can be used as a semiconductor integrated circuit for high-temperature processing.
【００７６】図１２は本発明の実施例５であって，その
ようにして，金属酸化物半導体により，バイポーラトラ
ンジスタを構成したものである。図１２において，４１
は基板である。FIG. 12 shows a fifth embodiment of the present invention, in which a bipolar transistor is made of a metal oxide semiconductor in this way. In FIG. 12, 41
Is the substrate.
【００７７】４２は金属酸化物半導体（ｐ型）であっ
て，コレクタである。４３は絶縁膜１である。４４は金
属酸化物半導体であって，ｎ型のベースである。Reference numeral 42 denotes a metal oxide semiconductor (p-type), which is a collector. 43 is the insulating film 1. A metal oxide semiconductor 44 is an n-type base.
【００７８】４５は電極線１であって，金属酸化物半導
体（ｎ型）（ベース）４４の引き出し線である。４６は
絶縁膜２である。Reference numeral 45 is an electrode line 1, which is a lead line of a metal oxide semiconductor (n type) (base) 44. 46 is the insulating film 2.
【００７９】４７は金属酸化物半導体（ｐ型）であっ
て，エミッタである。４８は電極配線２であって，エミ
ッタ４７の引き出し線である。図１２の実施例５のバイ
ポーラトランジスタの製造方法について説明する。Reference numeral 47 denotes a metal oxide semiconductor (p-type), which is an emitter. Reference numeral 48 denotes an electrode wiring 2 which is a lead line of the emitter 47. A method of manufacturing the bipolar transistor of the fifth embodiment shown in FIG. 12 will be described.
【００８０】(1) 基板４１上に金属酸化物半導体（ｐ
型）４２を形成する。さらに，金属酸化物半導体４２上
に絶縁膜１（４３）を形成する。
(2) 絶縁膜１（４３）をエッチングしてベース領域形
成用の開口５０を設け，前述した方法により金属酸化物
半導体層４２の表面に不純物をドープし，導電型をｎ型
としてｐｎ接合を形成する。さらに，ベース引き出し電
極線４５を配線する。(1) A metal oxide semiconductor (p
A mold 42 is formed. Further, the insulating film 1 (43) is formed on the metal oxide semiconductor 42. (2) The insulating film 1 (43) is etched to provide an opening 50 for forming a base region, the surface of the metal oxide semiconductor layer 42 is doped with impurities by the above-described method, and the conductivity type is set to n type to form a pn junction. Form. Further, the base lead electrode line 45 is wired.
【００８１】(3) (2) の状態で全面に絶縁膜１（４
３）を設け，エッチングによりエミッタ領域形成用の開
口５１を設け，前述の導電型の制御方法によりベース領
域の一部の導電型をｐ型にすることによりｐｎ接合を形
成する。その後，エミッタ引き出し電極４７を設ける。(3) In the state of (2), the insulating film 1 (4
3) is provided, an opening 51 for forming the emitter region is provided by etching, and a part of the conductivity type of the base region is made p-type by the above-described conductivity type control method to form a pn junction. After that, the emitter extraction electrode 47 is provided.
【００８２】以後，表面保護膜（図示せず）等を形成し
てバイポーラトランジスタとする。なお，上記におい
て，亜酸化銅等の金属酸化物半導体が，もともと内部に
含む元素またはある種の物質を，中性子照射による核反
応，もしくは水素原子照射による核反応など，結果的に
元素またはある種の物質が酸素に変化する反応により，
金属の一部または全部が反応して形成されるようにして
も良い。Thereafter, a surface protective film (not shown) or the like is formed to form a bipolar transistor. In addition, in the above, a metal oxide semiconductor such as cuprous oxide originally contains an element or a certain kind of substance, and as a result, a nuclear reaction by neutron irradiation or a nuclear reaction by hydrogen atom irradiation results in an element or a certain kind of substance. By the reaction that the substance of
You may make it a part or all of metal react and form.
【００８３】[0083]
【発明の効果】本発明によれば，低温処理により高移動
度の薄膜トランジスタを大面積に作成することができ
る。また製造コストも低くすることができる。According to the present invention, a thin film transistor having high mobility can be formed in a large area by low temperature treatment. Also, the manufacturing cost can be reduced.
【００８４】さらに，本発明によれば金属酸化物半導体
にｐｎ接合を良好に作成することができ，ｐｎ接合を持
つ金属酸化物薄膜半導体を低コストで製造することがで
きる。Further, according to the present invention, a pn junction can be favorably formed in a metal oxide semiconductor, and a metal oxide thin film semiconductor having a pn junction can be manufactured at low cost.
【００８５】また，本発明によれば，金属薄膜の一部を
トンネル電流が流せるほどの微小な幅の金属酸化物半導
体を得ることが可能なので，全く新しい原理で動作する
超微細トランジスタを製作し，超ＬＳＩの集積度を飛躍
的に高めかつ信号処理時間も飛躍的に速めた超ＬＳＩを
製作することができる。Further, according to the present invention, it is possible to obtain a metal oxide semiconductor having such a small width that a tunnel current can flow through a part of a metal thin film. Therefore, an ultrafine transistor operating on a completely new principle is manufactured. , It is possible to manufacture an ultra-LSI that dramatically increases the degree of integration of the ultra-LSI and dramatically increases the signal processing time.
【図１】本発明の基本構成(1) を示す図である。FIG. 1 is a diagram showing a basic configuration (1) of the present invention.
【図２】本発明の基本構成(2) を示す図である。FIG. 2 is a diagram showing a basic configuration (2) of the present invention.
【図３】本発明で使用する金属酸化物半導体の特性の例
を示す図である。FIG. 3 is a diagram showing an example of characteristics of a metal oxide semiconductor used in the present invention.
【図４】本発明の実施例１を示す図である。FIG. 4 is a diagram showing a first embodiment of the present invention.
【図５】本発明の実施例１の製造方法を示す図である。FIG. 5 is a diagram showing a manufacturing method according to the first embodiment of the present invention.
【図６】本発明の実施例１の特性の例を示す図である。FIG. 6 is a diagram showing an example of characteristics of the first embodiment of the present invention.
【図７】本発明の実施例２を示す図である。FIG. 7 is a diagram showing a second embodiment of the present invention.
【図８】本発明の実施例３を示す図である。FIG. 8 is a diagram showing Embodiment 3 of the present invention.
【図９】本発明の実施例３の製造方法を示す図である。FIG. 9 is a diagram showing a manufacturing method according to a third embodiment of the present invention.
【図１０】本発明の実施例４を示す図である。FIG. 10 is a diagram showing Embodiment 4 of the present invention.
【図１１】本発明実施例のアニール温度による亜酸化銅
の変化を示す図である。FIG. 11 is a diagram showing changes in cuprous oxide depending on the annealing temperature in the example of the present invention.
【図１２】本発明の実施例５を示す図である。FIG. 12 is a diagram showing Embodiment 5 of the present invention.
１：基板 ２：電極金属 ３：絶縁膜 ４：金属膜 ５：金属酸化物半導体 １１：基板 １２：金属膜 １３：金属酸化物半導体（第１の導電型） １４：真性半導体化領域 １５：接合部（ｐｎ接合） １６：金属酸化物半導体（第２の導電型） 1: substrate 2: Metal electrode 3: Insulating film 4: Metal film 5: Metal oxide semiconductor 11: substrate 12: Metal film 13: Metal oxide semiconductor (first conductivity type) 14: Intrinsic semiconductor region 15: junction (pn junction) 16: Metal oxide semiconductor (second conductivity type)
Claims (8)
することにより半導体化した金属酸化物半導体とを備え
ることを特徴とする金属酸化物半導体による薄膜トラン
ジスタ。1. A thin film transistor made of a metal oxide semiconductor, comprising a metal oxide semiconductor which is made into a semiconductor by oxidizing a formed metal thin film on a substrate.
ート電極上に絶縁膜を介して設けられた金属酸化物半導
体の薄膜と，該金属酸化物半導体薄膜に接続された電極
とを備えることを特徴とする請求項１に記載の金属酸化
物半導体による薄膜トランジスタ。2. A gate electrode provided on a substrate, a thin film of a metal oxide semiconductor provided on the gate electrode via an insulating film, and an electrode connected to the metal oxide semiconductor thin film. The thin film transistor using the metal oxide semiconductor according to claim 1.
して得た金属酸化物半導体の最小幅をトンネル電流が流
れる程度の幅とすることを特徴とする請求項２に記載の
金属酸化物半導体による薄膜トランジスタ。3. The minimum width of a metal oxide semiconductor obtained by oxidizing a part of a metal film provided on the insulating film is set to a width at which a tunnel current flows. Thin film transistor using a metal oxide semiconductor.
導体構造であることを特徴とする請求項１に記載の金属
酸化物半導体による薄膜トランジスタ。4. The thin film transistor according to claim 1, which has a metal oxide semiconductor-metal-metal oxide semiconductor structure.
酸化処理することにより第１の導電型を持つ金属酸化物
半導体とし，該金属酸化物半導体に第２の導電型不純物
を導入して第１の導電型と第２の導電型の接合を形成
し，半導体装置とすることを特徴とするｐｎ接合を形成
した金属酸化物半導体装置。5. A metal thin film is provided on a substrate, the metal thin film is oxidized to obtain a metal oxide semiconductor having a first conductivity type, and an impurity of a second conductivity type is introduced into the metal oxide semiconductor. A metal oxide semiconductor device having a pn junction, wherein a first conductivity type junction and a second conductivity type junction are formed to form a semiconductor device.
水素，リチウム，ナトリウム，カリウム，銅，亜鉛，イ
ンジウムの１種もしくは複数種の不純物を金属酸化物半
導体に導入し，その金属酸化物半導体のキャリヤ密度お
よび導電型を制御することを特徴とする請求項１，２，
３，４に記載の金属酸化物半導体による薄膜トランジス
タもしくは請求項５に記載のｐｎ接合を形成した金属酸
化物半導体装置の製造方法。6. The purpose of compensating for defects due to excess oxygen,
Claims characterized by introducing one or more impurities of hydrogen, lithium, sodium, potassium, copper, zinc and indium into a metal oxide semiconductor to control the carrier density and conductivity type of the metal oxide semiconductor. Items 1, 2,
A method of manufacturing a thin film transistor using the metal oxide semiconductor according to any one of claims 3 and 4 or a metal oxide semiconductor device having a pn junction according to claim 5.
酸素，水素もしくは周期律表における酸素と同じ族の元
素の１種もしくは複数種の不純物を金属酸化物半導体に
導入し，その金属酸化物半導体のキャリヤ密度および導
電型を制御することを特徴とする請求項１，２，３，４
に記載の金属酸化物半導体による薄膜トランジスタもし
くは請求項５に記載のｐｎ接合を形成した金属酸化物半
導体装置の製造方法。7. The purpose of compensating for defects due to lack of oxygen,
Characterized by introducing one or more impurities of oxygen, hydrogen, or an element of the same group as oxygen in the periodic table into a metal oxide semiconductor to control the carrier density and conductivity type of the metal oxide semiconductor. Claims 1, 2, 3, 4
A method of manufacturing a thin film transistor using the metal oxide semiconductor according to claim 5 or a metal oxide semiconductor device having a pn junction according to claim 5.
金属酸化物半導体にイオウ、セレン，弗素，塩素，リ
ン，砒素，アンチモンの元素を導入することで導電型を
制御することを特徴とする請求項６もしくは７に記載の
金属酸化物半導体による薄膜トランジスタもしくはｐｎ
接合を形成した金属酸化物半導体装置の製造方法。8. The conductivity type is controlled by introducing elements such as sulfur, selenium, fluorine, chlorine, phosphorus, arsenic, and antimony into a metal oxide semiconductor whose carrier density and conductivity type are controlled. Item 6 or 7, a thin film transistor or pn made of the metal oxide semiconductor
A method for manufacturing a metal oxide semiconductor device having a junction formed therein.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06827095A JP3479375B2 (en) | 1995-03-27 | 1995-03-27 | Metal oxide semiconductor device in which a pn junction is formed with a thin film transistor made of a metal oxide semiconductor such as cuprous oxide, and methods for manufacturing the same |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP06827095A JP3479375B2 (en) | 1995-03-27 | 1995-03-27 | Metal oxide semiconductor device in which a pn junction is formed with a thin film transistor made of a metal oxide semiconductor such as cuprous oxide, and methods for manufacturing the same |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08264794A JPH08264794A (en) | 1996-10-11 |
| JP3479375B2 true JP3479375B2 (en) | 2003-12-15 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP06827095A Expired - Lifetime JP3479375B2 (en) | 1995-03-27 | 1995-03-27 | Metal oxide semiconductor device in which a pn junction is formed with a thin film transistor made of a metal oxide semiconductor such as cuprous oxide, and methods for manufacturing the same |
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| JP (1) | JP3479375B2 (en) |
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