JP2007073558A - Thin film transistor manufacturing method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an oxidation property on a surface of an oxide semiconductor thin film mainly composed of zinc oxide ZnO in a gate insulating film manufacturing process of a thin film transistor having a top gate structure and using an oxide semiconductor thin film mainly composed of zinc oxide ZnO. By performing plasma treatment with gas, the surface of the semiconductor thin film is cleaned with oxygen termination and a gate insulating film is formed, thereby forming a good interface between the gate insulating film and the semiconductor thin film. Providing a method for manufacturing high-performance thin film transistors with reduced leakage current.
A method of manufacturing a top gate thin film transistor using an oxide mainly composed of zinc oxide ZnO as a semiconductor thin film, the gate covering the entire surface of the semiconductor thin film after patterning the semiconductor thin film Prior to processing for forming the insulating film with a silicon-based insulating film, the entire surface of the semiconductor thin film is subjected to a surface treatment in a plasma atmosphere using an oxidizing gas, and the gate is continuously formed in vacuum following the surface treatment. A method for manufacturing a thin film transistor, comprising forming an insulating film.
[Selection] Figure 2

Description

  The present invention relates to a method for manufacturing a top gate thin film transistor, and more particularly, by subjecting an oxide surface layer mainly composed of zinc oxide ZnO, which is a semiconductor thin film of a thin film transistor, to plasma treatment before forming the gate insulating film, The present invention relates to a manufacturing method capable of forming a high-performance thin film transistor in which a clean interface is formed between a semiconductor thin film and a semiconductor thin film to reduce drain-source leakage current and improve transfer characteristics.

It has long been known that oxides such as zinc oxide (ZnO) or magnesium zinc oxide (ZnMgO) have excellent semiconductor (active layer) properties, and in recent years thin film transistors (hereinafter abbreviated as TFT), light-emitting devices, transparent Research and development of thin film semiconductors using these oxides has been activated with the aim of applying electronic devices such as conductive films.
In particular, TFTs using zinc oxide (ZnO) as a semiconductor thin film have electron mobility compared to amorphous silicon TFTs using amorphous silicon (a-Si: H), which is mainly used in conventional liquid crystal displays, as a semiconductor layer. Therefore, active development is underway for reasons such as large TFT, excellent TFT characteristics and low temperature process.

  Conventionally reported TFTs using zinc oxide (ZnO) as a semiconductor thin film (ZnO-TFT) are mainly bottom-gate TFTs.

  Patent Document 1, Patent Document 2, and the like can be exemplified as those that disclose a bottom gate type ZnO-TFT.

  As shown in FIG. 5, the bottom gate type ZnO-TFT disclosed in Patent Document 1 includes a substrate 101, a gate electrode 102, a gate insulating film 103, a zinc oxide semiconductor thin film 104, a source electrode 105, a drain electrode 106, and a protective film 107. These components are stacked in this order.

  As shown in FIG. 6A, the bottom gate type ZnO-TFT disclosed in Patent Document 2 includes a substrate 108, a gate electrode 109, a gate insulating film 110, a source electrode 111, a drain electrode 112, and a zinc oxide semiconductor thin film 113. Each of these components is stacked in this order. Actually, in the final manufacturing process, as shown in FIG. 6B, the protective film 114 is formed by covering the zinc oxide semiconductor thin film 113.

  The bottom gate structure disclosed in these documents is a structure in which a gate electrode and a gate insulating film are formed from the substrate side, and a zinc oxide semiconductor thin film is formed covering the upper surface thereof. Since the process compatibility with the currently commercialized bottom gate structure amorphous silicon TFT is high, it is also widely used in ZnO-TFT.

However, from the viewpoint of the crystallinity of zinc oxide used as a channel layer (semiconductor layer), when a polycrystalline thin film is formed on a substrate, the region near the interface with the base formed at the initial stage of film formation is a crystal defect. There is a feature that crystallinity is improved as thin film formation proceeds.
A portion used as an active layer in a thin film transistor is a very thin region near the gate insulating film in the semiconductor layer, and crystallinity in this region greatly affects TFT characteristics of the thin film transistor such as mobility.
In a bottom-gate thin film transistor, a semiconductor layer is stacked on a gate insulating film because of its structure. Therefore, an initial region of film formation with insufficient crystallinity must be used as an active layer, and sufficient mobility is achieved. Had the problem of not being able to get.
In view of these problems, a top gate structure having a structure in which a gate insulating film is provided above a semiconductor layer can use a region with good crystallinity above the semiconductor layer as an active layer, and high mobility is expected. be able to.

As an example of the top gate type ZnO-TFT, there is a structure as shown in FIG.
In this top gate structure, a source / drain electrode 116, a semiconductor thin film 117, a gate insulating film 118, and a gate electrode 119 are laminated on a substrate 115 in this order.
The gate insulating film is often formed with a thickness of 200 to 500 nm by plasma enhanced chemical vapor deposition (PCVD).

A top gate type TFT (ZnO-TFT) using zinc oxide as a semiconductor active layer is formed on the semiconductor thin film patterned into the shape of the active layer, and at the same time as forming a good gate insulating film, the gate insulating film and the zinc oxide Control of the interface with the active layer is essential. In the case of a bottom gate type amorphous silicon TFT, SiN is often used as a gate insulating film. For example, a plasma chemical vapor deposition (PCVD) method capable of easily increasing the area is used, and a substrate temperature is 250 to 300 ° C. The film is formed using a mixed gas such as SiH ₄ + NH ₃ + H ₂ or SiH ₄ + NH ₃ + N ₂ + H ₂ .

  However, when the gate insulating film is deposited at the above substrate temperature using the plasma chemical vapor deposition (PCVD) method or other deposition methods after the patterning of the ZnO semiconductor thin film, the interface characteristics due to the adsorption of impurities. However, TFTs fabricated under the above conditions were not able to withstand application to liquid crystal displays and the like, resulting in problems such as deterioration of the leakage current and increased leakage current due to reduction of the ZnO surface due to the reducing atmosphere in gate insulating film formation.

As another example of the top gate type ZnO-TFT, Patent Document 3 is disclosed. In this document, in a transistor in which an oxide semiconductor film containing zinc oxide ZnO as a main component is used for a channel layer, a base film in which the oxide semiconductor film is formed over a base substrate, the oxide semiconductor film, A thin film transistor is disclosed in which a gate insulating film and a gate electrode are formed in this order, and the gate insulating film and the zinc oxide thin film are processed in the same shape as the gate electrode.
In the top gate type ZnO-TFT disclosed in Patent Document 3, it is possible to pattern process the gate insulating film and zinc oxide together after forming the gate electrode.

JP 2005-033172 A Japanese Patent Laid-Open No. 2004-349583 JP 2003-298062 A

  The transistor disclosed in Patent Document 3 does not provide a technique capable of preventing damage to the surface of an oxide semiconductor thin film mainly composed of zinc oxide ZnO and contamination due to impurities in the process of forming the semiconductor thin film and the gate insulating film. In the subsequent gate insulating film formation process, the resistance of the semiconductor thin film is lowered due to the damage of the semiconductor film surface in the previous period and the reductive desorption reaction in a reducing atmosphere, resulting in lower resistance, increased leakage current, and mobility. It had a problem such as a drop in

  In the process of forming the oxide semiconductor thin film mainly composed of zinc oxide ZnO and the gate insulating film, a protective film was formed on the upper surface of the oxide semiconductor thin film and patterned as a means for preventing damage to the zinc oxide semiconductor thin film. Means for applying a shape process such as patterning to the oxide semiconductor thin film containing zinc oxide ZnO as a main component by a method such as wet etching using the protective film as a mask, and laminating the gate insulating film without removing the protective film; Conceivable. However, when the zinc oxide semiconductor layer is formed using this means, the etching solution causes a so-called overhang in which the oxide semiconductor thin film is eroded to the inner side of the protective film, and the subsequent lamination process of the gate insulating film However, there is a problem that a void is generated between the gate insulating film and the semiconductor thin film. Therefore, an insulating film and a semiconductor thin film are formed by directly covering the oxide thin film layer mainly composed of zinc oxide ZnO with a gate insulating film and not damaging the oxide thin film layer mainly composed of zinc oxide ZnO. There has been a demand for a method for forming a good interface with the above.

  An object of the present invention is to form a gate insulating film of a thin film transistor having a top gate structure and using an oxide semiconductor thin film mainly composed of zinc oxide ZnO on the surface of the oxide semiconductor thin film mainly composed of zinc oxide ZnO. By performing plasma treatment with oxidizing gas, the semiconductor thin film surface is cleaned while oxygen-terminated to form a gate insulating film, thereby forming a good interface between the gate insulating film and the semiconductor thin film. The present invention provides a method for producing a high-performance thin film transistor in which the occurrence of short circuit and leakage current are reduced.

  The invention according to claim 1 is a method of manufacturing a top gate type thin film transistor using an oxide mainly composed of zinc oxide ZnO as a semiconductor thin film, and after patterning the semiconductor thin film, the entire surface of the semiconductor thin film Before the processing for forming the gate insulating film to cover the surface with the silicon-based insulating film, the entire surface of the semiconductor thin film is subjected to a surface treatment in a plasma atmosphere using an oxidizing gas, and the surface treatment is continuously performed in a vacuum. Then, the present invention relates to a method for manufacturing a thin film transistor, wherein the gate insulating film is formed.

  According to a second aspect of the present invention, the patterning of the semiconductor thin film includes a step of etching the semiconductor thin film directly using a photoresist as a mask without forming an insulating film on the semiconductor thin film. 1 relates to a method for producing the thin film transistor according to 1.

  According to a third aspect of the present invention, as the patterning of the semiconductor thin film, an insulating film covering the entire upper surface of the semiconductor thin film is formed, and after patterning with a photoresist is performed on the insulating film, the semiconductor thin film is etched. 2. The method of manufacturing a thin film transistor according to claim 1, further comprising a step of removing the insulating film after etching the semiconductor thin film.

  The invention according to claim 4 relates to a method of manufacturing a thin film transistor according to claims 2 and 3, wherein the etching of the semiconductor thin film is dry etching.

The invention according to claim 5 relates to a method of manufacturing a thin film transistor according to any one of claims 1 to 4, wherein oxygen or nitrous oxide (N ₂ O) is used as the oxidizing gas.

  The invention according to claim 6 is characterized in that when oxygen is used as the oxidizing gas, at least one kind of gas of He, Ar, Xe, Kr is used in combination with oxygen. The present invention relates to a method for manufacturing a thin film transistor.

  According to the first aspect of the present invention, before the gate insulating film is formed, the entire surface of the semiconductor thin film made of an oxide containing zinc oxide ZnO as a main component is subjected to surface treatment in a plasma atmosphere using an oxidizing gas. The gate insulating film is continuously formed in vacuum following the surface treatment, thereby efficiently removing impurities such as moisture adhering to the surface of the semiconductor thin film and simultaneously terminating the surface of the semiconductor thin film with oxygen. A thin film transistor with low leakage current can be provided by purifying the interface between the thin film and the gate insulating film and at the same time preventing reductive desorption on the ZnO surface.

  According to the second aspect of the present invention, the shape of the semiconductor thin film is processed directly by etching using a photoresist as a mask without forming an insulating film, thereby facilitating the manufacturing method and the high productivity thin film transistor. Can be provided.

  According to the invention of claim 3, the semiconductor thin film is shaped by forming an insulating film covering the entire upper surface of the semiconductor thin film, patterning the insulating film with a photoresist, and then etching the semiconductor thin film. After the etching of the semiconductor thin film, the insulating film is removed to protect the surface of the semiconductor thin film and prevent a void from being formed between the zinc oxide semiconductor thin film and the gate insulating film. It is possible to provide a thin film transistor with excellent TFT characteristics that has a good interface with an insulating film while preventing damage to a chemical solution used on the surface in a photolithography process.

  According to the fourth aspect of the present invention, by using dry etching as an etching method, fine processing can be performed and a highly accurate thin film transistor can be provided.

According to the invention of claim 5, by using oxygen or nitrous oxide (N ₂ O) as the oxidizing gas, the surface of the zinc oxide is more effectively oxygen-terminated, and good between the gate insulating films. A thin film transistor having an interface with low leakage current and high current driving capability can be provided.

  According to the invention of claim 6, it is possible to increase the amount of oxygen radicals generated by mixing at least one kind of gas of He, Ar, Xe, and Kr in the oxidizing gas atmosphere. In addition, the effect of removing organic contamination on the zinc oxide surface is improved. In addition, the sputter effect on the zinc oxide surface by the added gas removes metal and ionic impurities that could not be removed only by the oxidizing gas, and more excellent interfacial cleanliness. A thin film transistor with high driving capability can be provided.

  A thin film transistor according to an embodiment of the present invention will be described below with reference to FIG.

  A thin film transistor 100 according to an embodiment of the present invention includes a substrate 1, a source electrode 2, a drain electrode 3, a semiconductor thin film 4, a gate insulating film 6, a contact portion 7, a gate electrode 8, and a display electrode 9. These components are laminated to form.

As shown in FIG. 1A, the thin film transistor 100 is formed on a substrate 1 made of glass (non-alkali glass containing SiO ₂ and Al ₂ O ₃ as main components).
The material of the substrate 1 is not limited to glass, and any material can be used as long as it is an insulating material such as plastic or metal foil coated with an insulating material.

A source electrode 2 and a drain electrode 3 are stacked on the substrate 1. The source / drain electrodes 2 are arranged with a space in a part of the upper surface of the substrate 1.
The source electrode 2 and the drain electrode 3 are formed of, for example, a conductive oxide such as indium tin oxide (ITO) or n ⁺ ZnO, a metal, or a metal at least partially covered with the conductive oxide. .
The metal used for the source electrode 2 and the drain electrode 3 is a single layer or laminate of Ti, Cr, Ta, Mo, W, Al, Cu, Ni, or an alloy, Ti, Cr, Ta, Mo, W An alloy containing at least one of Al, Cu, Si, and Ni is used. Specific examples of this alloy include alloys such as TiW, TaW, MoW, MoSi, AlCu, AlSi, and NiSi.
As an example of forming the source electrode 2 and the drain electrode 3 with a metal at least partially covered with the conductive oxide, a structure as shown in FIG. A structure formed directly from a conductive oxide is also conceivable.
The thicknesses of these two electrodes are not particularly limited. For example, in order to prevent disconnection at a step portion of the semiconductor thin film 4 formed on the source electrode 2 and the drain electrode 3, a thickness of 30 nm to 150 nm is preferable. In the structure 1 (b), a conductive oxide such as indium tin oxide (ITO) or n ⁺ ZnO is thinner than the semiconductor thin film 3 (for example, about 40 nm). It is desirable to form the film thickness thinner than the semiconductor thin film 4 (for example, about 40 nm).

The semiconductor thin film 4 is laminated on the substrate 1 and the source / drain electrodes 2.
The semiconductor thin film 4 is disposed so as to form a channel between the source and drain electrodes 2, and current is supplied from the source electrode and emitted from the drain electrode.
The semiconductor thin film 4 is formed from an oxide semiconductor thin film mainly composed of zinc oxide (ZnO).
Although the thickness of this semiconductor thin film 4 is not specifically limited, For example, it forms in about 25-200 nm, Preferably, it forms in about 50-100 nm.

FIG. 1B is a diagram showing an example of a junction portion between the source electrode 2 or the drain electrode 3 and the semiconductor thin film 4, and a wiring in which titanium (Ti) is laminated on aluminum (Al) is formed. A structure is shown in which a portion of this stack is covered with indium tin oxide (ITO).
In FIG. 1B, the source electrode 2 or the drain electrode 3 is formed from an aluminum layer 11, a titanium layer 12, and an indium tin oxide (ITO) layer 13, and the semiconductor thin film 4 is indicated by reference numeral 14.
An aluminum layer 11 is provided on the substrate 10, and at least the upper surface thereof is covered with a titanium layer 12. An indium tin oxide (ITO) layer 13 is present covering a part of the titanium layer 12 and a part on the substrate. A part of the indium tin oxide (ITO) layer 13 is in contact with the semiconductor thin film 14.
With this structure, the titanium layer 12 and the indium tin oxide are in contact with aluminum (Al) and an oxide semiconductor, which cannot obtain a good ohmic contact because an oxide layer is originally formed on the aluminum. By interposing between the (ITO) layer 13, the contact resistance between aluminum (Al) and the oxide semiconductor can be reduced, and aluminum (Al) having a low wiring resistance can be used as an electrode.

  The gate insulating film 6 is laminated so as to reliably cover the surface and side surfaces of the source / drain electrode 2 and the semiconductor thin film 3. The thickness of the gate insulating film 6 is, for example, 200 to 400 nm, and preferably about 300 nm.

  The gate insulating film 6 is formed by, for example, a plasma chemical vapor deposition (PCVD) method, as will be described later in the method for manufacturing the thin film transistor 100 of the present invention. At this time, the film formation by plasma enhanced chemical vapor deposition (PCVD) method may be performed at a substrate temperature of 250 ° C. or lower which does not cause reduction of an oxide semiconductor thin film mainly composed of zinc oxide or desorption of a ZnO component. desirable.

  The contact portion 7 is formed of the same material as a gate electrode 8 described later in a contact hole portion formed by photolithography and etching in order to take out the source electrode 2 and the drain electrode 3 to the outside.

The gate electrode 8 is formed on the gate insulating film 6. The gate electrode 8 serves to control the electron density in the semiconductor thin film 4 by a gate voltage applied to the thin film transistor.
The gate electrode 8 is made of a metal film such as Cr or Ti and has a thickness of 50 to 100 nm, for example.

The display electrode 9 is formed to apply a voltage to the liquid crystal used in the liquid crystal display via a thin film transistor. Since this electrode requires high transmittance for visible light, it is formed of indium tin oxide (ITO), which is a conductive oxide thin film.
Although the thickness of the display electrode 9 is not specifically limited, For example, it forms in 50-100 nm.

  As a method for manufacturing a thin film transistor (TFT) according to the present invention, a first embodiment (see FIG. 2) and a second embodiment (see FIG. 3) will be described as examples.

  A first embodiment of a method of manufacturing a thin film transistor (TFT) according to the present invention will be described below with reference to FIG.

The first embodiment of the thin film transistor manufacturing method according to the present invention includes the following steps.
The first step is a step of laminating the source electrode 2 and the drain electrode 3 on the substrate 1. The second step is a step of laminating the semiconductor thin film 4 that covers the entire surface of the substrate 1, the source electrode 2, and the drain electrode 3. The third step is a step of patterning the semiconductor thin film 4. The fourth step is a step of performing a surface treatment in a plasma atmosphere using an oxidizing gas on the surface of the semiconductor thin film patterned by the third step. The fifth step is a step of forming the gate insulating film 6 so as to cover the entire surface of the semiconductor thin film 4, the source electrode 2 and the drain electrode 3, and the substrate 1 that have been subjected to the above processing. The sixth step is a step of forming a contact hole in the gate insulating film 6. The seventh step is a step of forming the gate electrode 8, the contact portion 7 and the display electrode 9 in this order on the gate insulating film.

  Hereinafter, a first embodiment of a method of manufacturing a thin film transistor (TFT) according to the present invention will be specifically described.

As shown in FIG. 2A, a metal such as Ti or Cr is formed to a thickness of, for example, 100 nm on the entire surface of the glass substrate 1 by magnetron sputtering or the like, and the source electrode 2 and the drain electrode 3 are formed by photolithography. . Although not shown, in this case, a conductive oxide such as n ⁺ ZnO or indium tin oxide (ITO) is laminated so as to cover the upper surface of the metal as a part of the source / drain metal film Is also included.

  An intrinsic ZnO thin film as a semiconductor thin film 4 is formed on the entire surface of the glass substrate 1, the source electrode 2 and the drain electrode 3 by a magnetron sputtering method with a film thickness of about 50 to 100 nm, for example.

A pattern is formed on the semiconductor thin film 4 with a photoresist and directly etched. As an etching method, after etching a ZnO thin film using wet etching with an aqueous solution of HNO ₃ , HCl, oxalic acid or the like, or dry etching using CH ₄ or the like, oxygen or tetrafluoride is used without using a resist stripping solution. A method of removing the photoresist by a dry process by ashing with a mixed gas of carbonized carbon (CF ₄ ) and oxygen can be exemplified.
Among the methods described above, it is preferable to use dry etching using a gas such as CH ₄ . This is because zinc oxide ZnO, which is the main component of the semiconductor thin film 4, has weak acid resistance, so that the photoresist is removed by a dry process after dry etching to reduce resist peeling damage at the same time as fine processing by dry etching. This is because productivity can be improved.
By the above method, the patterned semiconductor thin film 4 can be formed as shown in FIG. 2B without damaging the semiconductor thin film interface with the resist stripping solution.

After patterning the semiconductor thin film 4, as shown in FIG. 2 (3), an oxidizing gas such as oxygen (O ₂ ) or nitrous oxide (N ₂ O) is used on the surface of the semiconductor thin film 4. Surface treatment is performed in a plasma atmosphere.
When performing the surface treatment in a plasma atmosphere using an oxidizing gas, it is preferable to use at least one kind of rare gas such as He, Ar, Xe, Kr or the like together with the oxidizing gas. The reason for this is that by mixing the rare gas, generation of oxygen radicals from the oxidizing gas can be promoted, and cleaning can be performed efficiently. In particular, when oxygen is used as the oxidizing gas, it is more preferable to use these rare gases in combination since the generation of oxygen radicals can be dramatically increased.

  Since the surface of the semiconductor thin film 4 subjected to the above treatment is cleaned by plasma treatment, impurities such as water, gas molecules, and metals are removed, and at the same time, the surface of the zinc oxide is terminated with oxygen. Become. As a result, it is possible to prevent deterioration of the gate insulating film-ZnO interface characteristics due to adhesion of moisture and impurities, and damage to the ZnO semiconductor thin film accompanying the formation of the gate insulating film.

After the surface treatment is performed on the semiconductor thin film 4 in a plasma atmosphere using an oxidizing gas, the entire surface of the substrate 1, the source electrode 2, the drain electrode 3, and the semiconductor thin film 4 is formed as shown in FIG. A gate insulating film 6 is formed so as to cover it. A method for forming the gate insulating film 6 is not particularly limited, but a plasma enhanced chemical vapor deposition (PCVD) method that facilitates technical development on a large-area substrate is preferably used.
The step of forming the gate insulating film 6 is performed in the same apparatus continuously in a vacuum after the above-described treatment with the oxidizing gas. This is because the surface of the zinc oxide can be kept clean and at the same time the zinc oxide semiconductor thin film can be placed in an oxidizing atmosphere by the oxidizing gas, and oxygen or zinc can be desorbed from the semiconductor during the gate insulating film formation process. This is for deterrence.
The gate insulating film 6 is formed of a silicon-based insulating film, for example, SiOx, SiON, SiNx or the like. In particular, the gate insulating film 6 is formed at least as a semiconductor because it can be continuously formed from the substrate temperature rise by oxygen atmosphere treatment and oxygen plasma treatment. The layer in contact with the thin film 4 is preferably SiOx, SiON, or a film obtained by doping oxygen with N ₂ O in SiNx.
The gate insulating film 6 is formed with a thickness of 100 to 400 nm, for example. Of course, the gate insulating film can also be formed by stacking SiN having a high dielectric constant on an insulating film such as SiOx or SiON.
The formation of the gate insulating film 6 is not limited to the plasma enhanced chemical vapor deposition (PCVD) method, but various physical vapor deposition (PVD) methods such as sputtering, electron cyclotron resonance (ECR) sputtering, and electron cyclotron resonance. It can be carried out by any method such as various chemical vapor deposition (CVD) methods such as chemical vapor deposition (ECR-CVD) and inductively coupled plasma chemical vapor deposition (ICP-CVD).

Finally, as shown in FIG. 2 (5), a gate electrode 8 made of a metal film such as Cr or Ti is formed on the gate insulating film 6 to a thickness of 100 nm by DC sputtering, and the source electrode is made of the same material as the gate electrode 8. 2 and a contact portion 7 which is an electrode for taking out the drain electrode 3 to the outside through a contact hole is formed.
Thereafter, a display electrode 9 made of indium tin oxide (ITO) or the like is formed with a thickness of 50 nm by DC sputtering to complete the TFT array.

  A second embodiment of the thin film transistor (TFT) manufacturing method according to the present invention will be described below with reference to FIG.

The second embodiment of the thin film transistor manufacturing method according to the present invention includes the following steps.
The first step is a step of laminating the source electrode 2 and the drain electrode 3 on the substrate 1. The second step is a step of laminating the semiconductor thin film 4 covering the entire surface of the substrate 1, the source electrode 2 and the drain electrode 3. The third step is a step of forming an insulating film 5 that covers the entire surface of the semiconductor thin film 4. The fourth step is a step of patterning the semiconductor thin film 4 covered with the insulating film 5. The fifth step is a step of removing the patterned insulating film 5. The sixth step is a step of performing a surface treatment in a plasma atmosphere using an oxidizing gas on the surface of the semiconductor thin film exposed in the fifth step. The seventh step is a step of forming the gate insulating film 6 so as to cover the entire surface of the semiconductor thin film 4, the source electrode 2 and the drain electrode 3, and the substrate 1 that have been subjected to the above processing. The eighth step is a step of forming a contact hole in the gate insulating film 6. The ninth step is a step of forming the gate electrode 8, the contact portion 7, and the display electrode 9 in this order on the gate insulating film.

  Hereinafter, a second embodiment of the method for manufacturing a thin film transistor (TFT) according to the present invention will be described in detail.

As shown in FIG. 3A, a metal such as Ti or Cr is formed to a thickness of, for example, 100 nm on the entire surface of the glass substrate 1 by magnetron sputtering or the like, and the source electrode 2 and the drain electrode 3 are formed by photolithography. . Although not shown, in this case, a conductive oxide such as n ⁺ ZnO or indium tin oxide (ITO) is laminated so as to cover the upper surface of the metal as a part of the source / drain metal film Of course included.

  After forming the source electrode 2 and the drain electrode 3, an intrinsic ZnO thin film as a semiconductor thin film 4 is formed on the entire surface of the glass substrate 1, the source electrode 2 and the drain electrode 3 by a magnetron sputtering method with a film thickness of about 50 to 100 nm, for example. Form.

After the formation of the semiconductor thin film 4, an insulating film 5 is formed over the entire surface of the semiconductor thin film 4. The insulating film 5 is formed of SiOx or SiNx, for example, with a thickness of about 50 nm.
The insulating film 5 is etched by dry etching using a mixed gas of sulfur hexafluoride (SF ₆ ) and O ₂ , and then the semiconductor thin film 4 is patterned by wet etching or dry etching using the insulating film as a mask. The photoresist is removed by wet stripping with a photoresist stripping solution or dry ashing with oxygen or a mixed gas of carbon tetrafluoride (CF ₄ ) and oxygen. At this time, the insulating film 5 functions as a ZnO protective film during resist peeling.
Various etching methods can be used for patterning the insulating film 5 and the semiconductor thin film 4 described above. Among these, dry etching using a gas such as CH ₄ is preferably used. This is because zinc oxide ZnO, which is the main component of the semiconductor thin film 4, has low acid resistance, so that the photoresist is continuously removed by a dry process after dry etching, thereby reducing resist peeling damage at the same time as fine processing by dry etching. This is because productivity can be improved.

  By the above-described method, as shown in FIG. 3B, the patterned insulating film 5 and semiconductor thin film 4 can be formed.

After removing the photoresist, the patterned insulating film 5 is removed by dry etching. Dry etching is performed using a mixed gas of sulfur hexafluoride (SF ₆ ) and O ₂ . For this reason, the insulating film 5 is desirably formed of a compound having a large etching rate difference from that of the zinc oxide ZnO thin film in dry etching, that is, a compound having high etching selectivity, and SiNx is more desirable than SiOx.

After patterning the semiconductor thin film 4 by the above method, as shown in FIG. 3C, an oxidizing gas such as oxygen (O ₂ ) or nitrous oxide (N ₂ O) is applied to the surface of the semiconductor thin film 4. Surface treatment is performed in a plasma atmosphere using
When performing the surface treatment in a plasma atmosphere using an oxidizing gas, it is preferable to use at least one kind of rare gas such as He, Ar, Xe, Kr or the like together with the oxidizing gas. The reason for this is that by mixing the rare gas, generation of oxygen radicals from the oxidizing gas can be promoted, and cleaning can be performed efficiently. In particular, when oxygen is used as the oxidizing gas, it is more preferable to use these rare gases in combination since the generation of oxygen radicals can be dramatically increased.

  Since the surface of the semiconductor thin film 4 subjected to the above treatment is cleaned by plasma treatment, impurities such as water, gas molecules, and metals are removed, and at the same time, the surface of the zinc oxide is terminated with oxygen. Become. As a result, it is possible to prevent deterioration of the gate insulating film-ZnO interface characteristics due to adhesion of moisture and impurities, and damage to the ZnO semiconductor thin film accompanying the formation of the gate insulating film.

After the semiconductor thin film 4 is subjected to plasma treatment with an oxidizing gas, gate insulation is performed so as to cover the entire surface of the substrate 1, the source electrode 2, the drain electrode 3, and the semiconductor thin film 4 as shown in FIG. A film 6 is formed. A method for forming the gate insulating film 6 is not particularly limited, but a plasma enhanced chemical vapor deposition (PCVD) method that facilitates technical development on a large-area substrate is preferably used.
This step of forming the gate insulating film 6 is performed continuously in the same apparatus after the treatment with the above-described oxidizing gas. This is because the surface of the zinc oxide can be kept clean and at the same time the zinc oxide semiconductor thin film can be placed in an oxidizing atmosphere by the oxidizing gas, and oxygen or zinc can be desorbed from the semiconductor during the gate insulating film formation process. This is because it can be suppressed.
The gate insulating film 6 is formed of a silicon-based insulating film, for example, SiOx, SiON, SiNx or the like. In particular, the gate insulating film 6 is formed at least as a semiconductor because it can be continuously formed from the substrate temperature rise by oxygen atmosphere treatment and oxygen plasma treatment. The layer in contact with the thin film 4 is preferably SiOx, SiON, or a film obtained by doping oxygen with N ₂ O in SiNx.
The gate insulating film 6 is formed with a thickness of 100 to 400 nm, for example. Of course, the gate insulating film can also be formed by stacking SiN having a high dielectric constant on an insulating film such as SiOx or SiON.
The formation of the gate insulating film 6 is not limited to the plasma enhanced chemical vapor deposition (PCVD) method, but various physical vapor deposition (PVD) methods such as sputtering, electron cyclotron resonance (ECR) sputtering, and electron cyclotron resonance. It can be carried out by any method such as various chemical vapor deposition (CVD) methods such as chemical vapor deposition (ECR-CVD) and inductively coupled plasma chemical vapor deposition (ICP-CVD).

Finally, as shown in FIG. 3 (5), a gate electrode 8 made of a metal film such as Cr or Ti is formed on the gate insulating film 6 to a thickness of 100 nm by DC sputtering, and the source electrode is made of the same material as the gate electrode 8. 2 and a contact portion 7 which is an electrode for taking out the drain electrode 3 to the outside through a contact hole is formed.
Thereafter, a display electrode 9 made of indium tin oxide (ITO) or the like is formed with a thickness of 50 nm by DC sputtering to complete the TFT array.

Test example

Hereinafter, the effect of the present invention will be made clearer by comparing the characteristics of the test example of the transistor obtained by the method according to the present invention and the characteristics of the comparative example.

(Test example)
A transistor (see FIG. 1) based on the manufacturing method according to the present invention was prepared by the following method (see FIG. 2).
A source electrode 2 and a drain electrode 3 made of indium tin oxide (ITO) were formed to a thickness of 40 nm on a substrate 1 made of alkali-free glass mainly composed of SiO ₂ and Al ₂ O ₃ .
A zinc oxide (ZnO) thin film having a thickness of 50 nm was formed as a semiconductor thin film 4 on the entire surface of the substrate 1, the source electrode 2 and the drain electrode 3 by RF magnetron sputtering.
An insulating film 5 was formed on the entire upper surface of the semiconductor thin film 4 with SiNx. This insulating film was formed at 225 ° C., and the film was formed to a thickness of 50 nm by plasma enhanced chemical vapor deposition (PCVD) using SiH ₄ + N ₂ O gas. Further, a photoresist was coated on the insulating film 5, and the insulating film 5 was dry-etched using a CF ₄ + O ₂ gas using the patterned photoresist as a mask.
Wet etching was performed on the ZnO semiconductor thin film 4 with a 0.2% HNO ₃ solution. The photoresist was removed, and the insulating film 5 (SiNx) used as an etching mask for zinc oxide was removed. The insulating film 5 was removed by dry etching using SF ₆ + O ₂ gas.
After removing the insulating film, the substrate was transferred to a plasma enhanced chemical vapor deposition (PCVD) apparatus, and surface treatment was performed on the zinc oxide semiconductor thin film in a plasma atmosphere containing oxygen (O ₂ ) and Ar. Thereby, a zinc oxide semiconductor film having a cleaned surface was obtained.
Next, a gate insulating film 6 made of SiOx was formed to a thickness of 300 nm over the entire surface of the substrate 1, the source electrode 2, the drain electrode 3, and the ZnO semiconductor thin film 4 so as to cover the zinc oxide semiconductor thin film.
The gate insulating film 6 was formed by plasma enhanced chemical vapor deposition (PCVD) using SiH ₄ + N ₂ O gas in succession to the surface treatment and in vacuum at a substrate temperature of 250 ° C. When the gate insulating film is formed, the substrate is heated to the set temperature in the process chamber. At this time, the substrate is heated in an oxygen plasma atmosphere, so that oxygen or zinc is desorbed from the zinc oxide thin film during the substrate heating process. After the substrate temperature reached the set temperature, SiOx as the second insulating film was subsequently formed by plasma enhanced chemical vapor deposition (PCVD).
After forming the second insulating film, contact holes were opened on the source electrode 2 and the drain electrode 3 by dry etching using photolithography and CF ₄ + O ₂ gas.
A gate electrode 8 made of Cr is formed on the gate insulating film 6 to a thickness of 100 nm, a contact portion 7 is formed of the same material, and then a display electrode 9 made of indium tin oxide (ITO) is formed on the gate electrode 8. A transistor was formed by forming a 100 nm thickness on the part.

(Comparative example)
As a comparative example, in the above-described method, the process until the step of removing the first insulating film was performed in the same way as in the test example, and then plasma treatment was not performed before the gate insulating film was formed, and the SiOx as the gate insulating film was plasma-chemically processed. It was formed by the vapor deposition (PCVD) method. The manufacturing process after the formation of the gate insulating film is the same as the test example.

(Transfer characteristics evaluation test)
Using the transistors of the test example and the comparative example, the magnitude of the drain current accompanying the change in the gate voltage was measured to evaluate the transfer characteristics.
The result is shown in FIG.

As apparent from FIG. 4, the off-state current (Vgs <0) of the transistor in the test example was one digit or more smaller than the off-state current in the comparative example.
This is because the transistor of the test example was able to suppress zinc or oxygen desorption from zinc oxide by heating the substrate in an oxygen plasma atmosphere while the temperature of the substrate during film formation of the gate insulating film was increased. This is because the reduction reaction of the surface and side surfaces of the layer is suppressed, and the leakage current between the source and drain electrodes is reduced by reducing the resistance of zinc oxide.

  Further, as apparent from FIG. 4, the rise of the transistor in the test example is steeper than that of the comparative example, and the on-current (Ids at Vgs = 10 V) is also large. This is because the transistor in the test example heated the substrate in an oxygen plasma atmosphere during the temperature rise of the substrate when forming the gate insulating film, so that the zinc oxide surface was kept clean and at the same time the surface of the zinc oxide was oxygenated. This is because the reduction reaction of the surface and side surfaces of the zinc oxide semiconductor layer is suppressed and the interface defect density between the zinc oxide and the gate insulating film is reduced.

  As described in the above test example, the thin film transistor (TFT) and the manufacturing method thereof according to the present invention are excellent in the effect of suppressing a short circuit between the source and drain electrodes or a leakage current, and have a transistor exhibiting excellent TFT characteristics. It turns out that it is what you provide.

  As described above, by using the present invention, a method for manufacturing a high-performance thin film transistor in which leakage current between a drain and a source of a thin film transistor is reduced by preventing damage to a semiconductor layer and forming a clean interface is provided. be able to.

(A) is sectional drawing which shows the form of one Example of the thin-film transistor (TFT) in this invention, (b) is the source electrode or drain electrode in one embodiment of the thin-film transistor (TFT) in this invention, a semiconductor thin film, It is sectional drawing which showed an example of the junction part. It is sectional drawing which shows the 1st Example of the manufacturing method of the thin-film transistor (TFT) in this invention. It is sectional drawing which shows the 2nd Example of the manufacturing method of the thin-film transistor (TFT) in this invention. It is a figure which shows the transfer characteristic of the transistor of a test example and a comparative example. It is sectional drawing which shows an example of the zinc oxide thin-film transistor (ZnO-TFT) with the conventional bottom gate structure. It is sectional drawing which shows the other example of the zinc oxide thin-film transistor (ZnO-TFT) with the conventional bottom gate structure, (b) is sectional drawing which shows the last process of manufacture of this ZnO-TFT. It is sectional drawing which shows the thin-film transistor (TFT) with the conventional top gate structure.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Substrate 2 Source electrode 3 Drain electrode 4 Semiconductor thin film 5 Insulating film 6 Gate insulating film 7 Contact part 8 Gate electrode 9 Display electrode 10 Substrate 11 Aluminum layer 12 Titanium layer 13 Indium tin oxide (ITO) layer 14 Semiconductor thin film 100 Thin film transistor

Claims (6)

A method of manufacturing a top gate type thin film transistor using an oxide mainly composed of zinc oxide ZnO as a semiconductor thin film, wherein after the semiconductor thin film is patterned, a gate insulating film covering the entire surface of the semiconductor thin film is formed by silicon Prior to processing to form the system insulating film, the entire surface of the semiconductor thin film layer is subjected to surface treatment in a plasma atmosphere using an oxidizing gas, and the gate insulating film is continuously formed in vacuum following the surface treatment. A method for manufacturing a thin film transistor, comprising: forming a thin film transistor. 2. The method of manufacturing a thin film transistor according to claim 1, wherein the patterning of the semiconductor thin film includes a step of etching the semiconductor thin film directly using a photoresist as a mask without forming an insulating film on the semiconductor thin film. As the patterning of the semiconductor thin film, an insulating film covering the entire upper surface of the semiconductor thin film is formed, and after the insulating film is subjected to pattern processing with a photoresist, the semiconductor thin film is etched, and after etching of the semiconductor thin film, 2. The method of manufacturing a thin film transistor according to claim 1, further comprising a step of removing the insulating film. 4. The method of manufacturing a thin film transistor according to claim 2, wherein the etching of the semiconductor thin film is dry etching. 5. The method of manufacturing a thin film transistor according to claim 1, wherein oxygen or nitrous oxide (N ₂ O) is used as the oxidizing gas. 6. The method of manufacturing a thin film transistor according to claim 5, wherein when oxygen is used as the oxidizing gas, at least one of He, Ar, Xe, and Kr is used in combination with oxygen.

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