KR102222438B1 - Semiconductor device and display device - Google Patents

Abstract

There is provided a highly reliable semiconductor device in which yield reduction is prevented due to electrostatic discharge damage. The gate electrode layer, the gate insulating layer over the gate electrode layer, the oxide insulating layer over the gate insulating layer, the oxide semiconductor layer contacting the oxide insulating layer over the oxide insulating layer and overlapping the gate electrode layer, and electrically connected to the oxide semiconductor layer. A semiconductor device comprising a source electrode layer and a drain electrode layer is provided. The gate insulating layer includes a silicon film containing nitrogen. The oxide insulating layer contains one or more metal elements selected from constituent elements of the oxide semiconductor layer. The thickness of the gate insulating layer is thicker than that of the oxide insulating layer.

Description

Semiconductor device and display device {SEMICONDUCTOR DEVICE AND DISPLAY DEVICE}

An embodiment of the present invention disclosed in this specification and the like relates to a semiconductor device and a method of manufacturing the semiconductor device.

In this specification and the like, a semiconductor device generally means a device that can function by using semiconductor properties, and an electro-optical device, a light emitting display device, a semiconductor circuit, and an electronic device are all semiconductor devices.

Attention has been focused on a technique for forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface. Such transistors are applied to a wide range of electronic devices such as integrated circuits (ICs) or image display devices (also simply referred to as display devices). Silicon-based semiconductor materials are widely known as materials for semiconductor thin films that can be applied to transistors. As another material, oxide semiconductors are attracting attention.

For example, a technique for forming a transistor using zinc oxide or an In-Ga-Zn-based oxide semiconductor as an oxide semiconductor is disclosed (see Patent Documents 1 and 2).

Japanese Laid-Open Patent Publication No. 2007-123861 Japanese Laid-Open Patent Publication No. 2007-96055

Considering the development cost and speed for mass production of semiconductor devices having oxide semiconductors, the current mass production technology for practical use, i.e., transistor structure, process conditions, and production equipment for silicon-based semiconductor materials such as amorphous silicon or polycrystalline silicon It is preferable to use wild, etc.

However, the mechanism of carrier generation in the oxide semiconductor is significantly different from the carrier generation mechanism in the silicon-based semiconductor material. The physical properties of the oxide semiconductor greatly affect the properties or reliability of the transistor.

In particular, when the gate insulating layer used for the silicon-based semiconductor material is used for the oxide semiconductor, the gate insulating layer does not provide excellent interfacial properties with the oxide semiconductor. Accordingly, there has been a demand for development of a gate insulating layer suitable for use in a semiconductor device including an oxide semiconductor.

For a semiconductor device including a transistor formed using a silicon-based semiconductor material such as amorphous silicon or polycrystalline silicon, a glass substrate of the eighth generation (2160 mm width x 2460 mm length) or later may be used. Therefore, such a semiconductor device has advantages of high productivity and low cost. However, when such a glass substrate is used, a problem of electrostatic discharge (ESD) damage occurs due to high insulating properties and a large area. This problem must be considered indispensably even when an oxide semiconductor material is used.

In view of this technical background, the object of an embodiment of the present invention is to be highly reliable and electrically through a small number of changes in transistor structure, process conditions, production equipment, etc. from mass production technology that has been applied in actual use. It is to provide a stable semiconductor device.

Another object of an embodiment of the present invention is to provide a semiconductor device in which a yield decrease due to electrostatic discharge damage is prevented.

One embodiment of the disclosed invention includes a silicon film containing nitrogen and at least one metal element selected from constituent elements of the oxide semiconductor layer, which are sequentially stacked between the gate electrode layer and the oxide semiconductor layer from the side adjacent to the gate electrode layer. A structure including an oxide insulating layer containing them is a semiconductor device.

A silicon film containing nitrogen has a higher relative dielectric constant than a silicon oxide film, and thus requires a thicker thickness for equivalent capacitance. Therefore, when a silicon film containing nitrogen is used as the gate insulating layer, the physical thickness of the gate insulating layer can be increased, which makes it possible to reduce a decrease in withstand voltage, and preferably increase withstand voltage. Accordingly, it is possible to reduce electrostatic discharge damage to a semiconductor device including such a gate insulating layer.

It is preferable that the thickness of the silicon film containing nitrogen is 325 nm or more and 550 nm or less, more preferably 355 nm or more and 550 nm or less. As the silicon film containing nitrogen, a silicon nitride film is preferably used.

A silicon film containing nitrogen has actually been used as a gate insulating layer for a silicon-based semiconductor material such as amorphous silicon or polycrystalline silicon, and thus the same process conditions, production devices, and the like can be employed. Therefore, the use of a silicon film containing nitrogen as the gate insulating layer enables transistors having an oxide semiconductor to be mass-produced at low cost.

When an oxide insulating layer containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer is provided in contact with the oxide semiconductor layer, the interface between the oxide insulating layer and the oxide semiconductor layer can be maintained in a good state, and deteriorated. Can be prevented. In particular, the trapping of carriers at the interface between the oxide insulating layer and the oxide semiconductor layer is reduced, so that photodeterioration of the transistor (e.g., negative bias temperature stress degradation) can be reduced, thereby obtaining a highly reliable transistor. I can.

That is, according to an embodiment of the present invention, a stacked structure of a silicon film containing nitrogen, an oxide insulating layer containing one or more metal elements selected from constituent elements of the oxide semiconductor layer, and the oxide semiconductor layer is formed of silicon-based semiconductor materials. Is formed using in part mass production techniques applied to actual use for; It is possible to provide a semiconductor device with new advantageous effects different from those of semiconductor devices formed using silicon-based semiconductor materials. In particular, for example, the following structures may be employed.

An embodiment of the present invention is a gate electrode layer, a gate insulating layer over the gate electrode layer, an oxide insulating layer over the gate insulating layer, an oxide semiconductor over the oxide insulating layer and in contact with the oxide insulating layer, and overlapping the gate electrode layer. A semiconductor device comprising a layer, and a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer. The gate insulating layer includes a silicon film containing nitrogen. The oxide insulating layer contains one or more metal elements selected from constituent elements of the oxide semiconductor layer. The thickness of the gate insulating layer is thicker than that of the oxide insulating layer.

In the semiconductor device described above, it is preferable that the ends of the oxide semiconductor layer and the oxide insulating layer are oriented with each other. In this specification and the like, "to be oriented" includes "substantially oriented". For example, the ends of the layer A and the ends of the layer B included in the laminated structure etched using the same mask are considered to be oriented to each other.

In addition to the lamination structure of an oxide insulating layer containing one or more metal elements selected from constituent elements of the oxide semiconductor layer, and a silicon film containing nitrogen provided in contact with the oxide semiconductor layer under the oxide semiconductor layer, an oxide semiconductor layer A stacked structure in contact with the oxide semiconductor layer above may also be provided. This structure enables the semiconductor device to have more stable electrical properties and/or to be prevented from damage due to electrostatic discharge.

That is, another embodiment of the present invention is a gate electrode layer, a gate insulating layer over the gate electrode layer, a first oxide insulating layer over the gate insulating layer, the first oxide insulating layer and in contact with the first oxide insulating layer, An oxide semiconductor layer overlapping the gate electrode layer, a source electrode layer and a drain electrode layer electrically connected to the oxide semiconductor layer, a second oxide insulating layer covering the source electrode layer and the drain electrode layer and contacting a portion of the oxide semiconductor layer, and a second 2 A semiconductor device comprising a protective insulating layer over an oxide insulating layer. Each of the gate insulating layer and the protective insulating layer includes a silicon film containing nitrogen. The first oxide insulating layer and the second oxide insulating layer each contain one or more metal elements selected from constituent elements of the oxide semiconductor layer. The thickness of the gate insulating layer is thicker than that of the first oxide insulating layer. The thickness of the protective insulating layer is thicker than that of the second oxide insulating layer.

In the semiconductor device described above, it is preferable that the ends of the oxide semiconductor layer and the first oxide insulating layer are oriented with each other.

In one of the semiconductor devices described above, it is preferable that the thickness of the gate insulating layer is 325 nm or more and 550 nm or less. As the gate insulating layer, a silicon nitride film is preferably used.

It is preferable that the oxide insulating layer in contact with the oxide semiconductor layer includes a region containing oxygen in excess of the stoichiometric composition (oxygen excess region). Supply of oxygen to the oxide semiconductor layer becomes possible by making the oxide insulating layer in contact with the oxide semiconductor layer contain an oxygen-excessive region. Vacancies of oxygen in the oxide semiconductor act as donors that generate electrons that are carriers in the oxide semiconductor. A highly reliable transistor can be obtained by supplying oxygen to the oxide semiconductor layer to fill voids in oxygen.

The semiconductor device according to an embodiment of the present invention is manufactured by a manufacturing method having a small number of changes from a mass production technology that has been applied to actual use, and has stable electrical characteristics and high reliability.

In addition, according to an embodiment of the present invention, it is possible to provide a semiconductor device in which a reduction in yield due to electrostatic discharge damage is prevented.

1 is a plan view and cross-sectional views illustrating an embodiment of a semiconductor device.
2 is a plan view and cross-sectional views illustrating an embodiment of a semiconductor device.
3 are diagrams showing examples of manufacturing steps of a semiconductor device.
4 are diagrams each showing an embodiment of a semiconductor device.
5 is a diagram illustrating an embodiment of a semiconductor device.
6 are views each showing an embodiment of a semiconductor device.
7 is a diagram illustrating an embodiment of a semiconductor device.
8 is diagrams illustrating electronic devices.
9 is diagrams illustrating electronic devices.
10 is a plan view and cross-sectional views illustrating an embodiment of a semiconductor device.
11 is a plan view and cross-sectional views illustrating an embodiment of a semiconductor device.
Fig. 12 is a diagram showing the result of ESR measurement.
13 are diagrams showing results of TDS measurement.
14 is an energy band diagram of a stacked structure included in a transistor according to an embodiment of the present invention.

Embodiments of the present invention will be described in detail below with reference to the drawings. It should be noted that those skilled in the art will readily understand that the present invention is not limited to the description below, and that the modes and details of the present invention can be modified in various ways. Therefore, the present invention should not be construed as being limited to the description of the embodiments given below.

It should be noted that in the structures of the present invention described below, the same parts or parts having a similar function are indicated by the same reference numerals in different drawings, and the description of these parts is not repeated. The same shading pattern is applied to parts having a similar function, and these parts are not specifically designated through reference numbers in some cases.

It should be noted that in each drawing described herein, the size, film thickness, or area of each component may be exaggerated for clarity. Therefore, embodiments of the present invention are not limited to these accumulations.

It should be noted that ordinal numbers such as “first” and “second” in this specification are used for convenience and do not refer to the order of steps or the order of stacking of layers. In addition, ordinal numbers, etc. in this specification do not designate any special names for limiting the present invention.

(Example 1)

In this embodiment, embodiments of a semiconductor device and a method for manufacturing a semiconductor device will be described with reference to FIGS. 1, 2, 3, 10, and 11. In this embodiment, lower-gate transistors including oxide semiconductor layers are described as an example of a semiconductor device.

<Structure Example 1 of a semiconductor device>

1 shows an example of a structure of a transistor 300. 1A is a plan view of the transistor 300, FIG. 1B is a cross-sectional view taken along a dashed-dotted line X1-Y1 in FIG. 1A, and FIG. 1C is a dashed-dotted line in FIG. 1A. It is a cross-sectional view taken along (V1-W1).

The transistor 300 includes a gate electrode layer 402 on a substrate 400 having an insulating surface, a gate insulating layer 404 on the gate electrode layer 402, and an oxide insulating layer on the gate insulating layer 404 ( 406), an oxide semiconductor layer 408 in contact with the oxide insulating layer 406 over the oxide insulating layer 406 and overlapping the gate electrode layer 402, and a source electrode layer electrically connected to the oxide semiconductor layer 408 ( 410a) and a drain electrode layer 410b.

In the transistor 300, the gate insulating layer 404 includes a silicon film containing nitrogen. A silicon film containing nitrogen has a higher relative dielectric constant than a silicon oxide film, and requires a thicker thickness for equivalent capacitance. Therefore, the physical thickness of the gate insulating layer can be increased. This can reduce a decrease in the withstand voltage of the transistor 300 and further increase the withstand voltage, thereby reducing electrostatic discharge damage to the semiconductor device.

The thickness of the gate insulating layer 404 is at least thicker than the thickness of the oxide insulating layer 406, preferably 325 nm or more and 550 nm or less, and more preferably 355 nm or more and 550 nm or less.

Examples of the silicon film containing nitrogen include a silicon nitride film, a silicon nitride oxide film, a silicon oxynitride film, and the like. Since a material with a high nitrogen content has a higher relative dielectric constant, it is preferable to use a silicon nitride film. Silicon oxide has an energy gap of 8 eV, whereas silicon nitride has a small energy gap of 5.5 eV, and thus has a low resistivity. Therefore, the use of a silicon nitride film can increase the resistance to ESD. In addition, when the silicon nitride film is formed by the CVD method, it is used when a silicon film containing oxygen and nitrogen, such as a silicon nitride oxide film, is formed by the CVD method, and there is no need to use _{N 2 O gas, which is a greenhouse gas.} It should be noted that in this specification, "silicon oxynitride film" refers to a film containing more oxygen than nitrogen, and "silicon nitride oxide film" refers to a film containing more nitrogen than oxygen.

In transistor 300, oxide insulating layer 406 contains one or more metal elements selected from the constituent elements of oxide semiconductor layer 408. Since the oxide insulating layer 406 is formed using such a material, the interface between the oxide insulating layer 406 and the oxide semiconductor layer 408 can be stabilized, and charge trapping at the interface can be reduced. Accordingly, deterioration of the transistor, especially photodeterioration, can be prevented, and thus a transistor of high reliability can be obtained.

In particular, as the oxide insulating layer 406, for example, a gallium oxide film ( _{also referred to as GaO x} (it should be noted that x is not necessarily a natural number, and may be a non-natural number)), a gallium zinc oxide film (Ga ₂ Zn _{Also referred to as x} O _y (x=1 to 5), a Ga ₂ O ₃ (Gd ₂ O ₃ ) film), an In-Ga-Zn-based oxide insulating film having a high gallium content and a low indium content, etc. It is desirable.

The oxide insulating layer 406 and the oxide semiconductor layer 408 may have different compositions of the same constituent elements. For example, when the In-Ga-Zn-based oxide semiconductor layer is used as the oxide semiconductor layer 408, since the energy gap can be controlled by the ratio between indium (In) and gallium (Ga), the oxide semiconductor layer 408 ) May have an atomic ratio of In:Ga:Zn=1:1:1 or In:Ga:Zn=3:1:2, and the oxide insulating layer 406 is In:Ga:Zn=1:3: It can have an atomic ratio of 2. It should be noted that the oxide insulating layer 406 and the oxide semiconductor layer 408 can be formed by a sputtering method, and through a sputtering target containing indium, the generation of particles during film formation can be reduced. Accordingly, an oxide insulating layer 406 containing indium and an oxide semiconductor layer 408 containing indium are preferred.

It should be noted that in the example of the transistor 300 shown in FIG. 1, through an etching treatment to treat the oxide semiconductor layer 408 into an island form, the oxide insulating layer 406 is also treated into an island form. Thus, the ends of the oxide insulating layer 406 and the oxide semiconductor layer 408 are oriented with each other.

The structure of the oxide semiconductor layer is described below.

The oxide semiconductor layer is roughly classified into a single crystal oxide semiconductor layer and a non-single crystal oxide semiconductor layer. The non-single crystal oxide semiconductor layer includes any one of an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, a polycrystalline oxide semiconductor layer, a c-axis oriented crystal oxide semiconductor (CAAC-OS) film, and the like.

The amorphous oxide semiconductor layer has an irregular atomic orientation and has no crystal components at all. A typical example of this is an oxide semiconductor layer, which has no crystal parts even in a small region, and the entire layer is amorphous.

The microcrystalline oxide semiconductor layer includes microcrystals (also referred to as nanocrystals) having a size of 1 nm or more and less than 10 nm, for example. Thus, the microcrystalline oxide semiconductor layer has a higher degree of atomic regularity than the amorphous oxide semiconductor layer. Accordingly, the density of the defect states of the microcrystalline oxide semiconductor layer is lower than that of the amorphous oxide semiconductor layer.

The CAAC-OS film includes a plurality of crystal portions, and most of each crystal portion is one of oxide semiconductor layers that fit into a cube whose one side is less than 100 nm. Accordingly, there is a case where the crystal part contained in the CAAC-OS film enters a cube having one side of less than 10 nm, less than 5 nm, or less than 3 nm. The density of the defect states of the CAAC-OS film is lower than that of the microcrystalline oxide semiconductor layer. The CAAC-OS membrane is described in detail below.

In the transmission electron microscopy (TEM) image of the CAAC-OS film, the boundary between the crystal parts, that is, the grain boundary is not clearly observed. Therefore, in the CAAC-OS film, a decrease in electron mobility due to grain boundaries is unlikely to occur.

According to the TEM image (cross-sectional TEM image) of the CAAC-OS film observed in a direction substantially parallel to the sample surface, the metal atoms are arranged in layers in the crystal parts. Each metal atomic layer has a topography reflecting the surface on which the CAAC-OS film is formed (hereinafter, the surface on which the CAAC-OS film is formed is referred to as the surface to be formed) or the top surface of the CAAC-OS film, and the surface on which the CAAC-OS film is formed or It is arranged parallel to the top surface.

In the present specification, the term "parallel" means that an angle formed between two straight lines is -10° or more and 10° or less, and therefore, also includes a case where the angle is -5° or more and 5° or less. In addition, the term "vertical" means that the angle formed between two straight lines is 80° or more and 100° or less, and thus includes the case where the angle is 85° or more and 95° or less.

On the other hand, according to the TEM image (planar TEM image) of the CAAC-OS film observed in a direction substantially perpendicular to the sample surface, the metal atoms are arranged in a triangular or hexagonal configuration within the crystal parts. However, there is no regularity of the arrangement of metal atoms between different crystal parts.

From the results of the cross-sectional TEM image and the planar TEM image, the orientation is found in the crystal parts in the CAAC-OS film.

The CAAC-OS film is subjected to structural analysis through an X-ray diffraction (XRD) device. For example, when _{a CAAC-OS film including an InGaZnO 4} crystal is analyzed by an out-of-plane method, a peak frequently appears when the diffraction angle 2θ is approximately 31°. This peak is _{derived from the (009) plane of the crystal of InGaZnO 4} , which means that the crystals in the CAAC-OS film have a c-axis orientation, and the c-axis are substantially perpendicular to the formation surface or top surface of the CAAC-OS film. Indicates oriented in a direction.

On the other hand, when the CAAC-OS film is analyzed by an in-plane method in which X-rays are incident on the sample in a direction perpendicular to the c-axis, the peak frequently occurs when 2θ is approximately 56°. appear. This peak is derived from the (110) plane _{of the InGaZnO 4 crystal.} Here, analysis (φ scan) is performed under conditions in which 2θ is fixed at approximately 56°, and the sample rotates with the normal vector of the sample surface as an axis (φ axis). When the sample is a single crystal oxide semiconductor layer of _{InGaZnO 4, six peaks appear.} The six peaks are derived from crystal planes equivalent to the (110) plane. On the other hand, in the case of the CAAC-OS film, even when a φ scan is performed with 2θ fixed at approximately 56°, the peak is not clearly observed.

According to the above results, in a CAAC-OS film having a c-axis orientation, the directions of the a-axis and the b-axis are different between the crystal parts, but the c-axis is the normal vector of the surface to be formed or the normal of the top surface. Oriented in a direction parallel to the vector. Thus, each layer of metal atoms arranged in layers observed in the cross-sectional TEM image corresponds to a plane parallel to the a-b plane of the crystal.

It should be noted that the crystal portion is formed simultaneously with the deposition of the CAAC-OS film, or is formed through a crystallization treatment such as heat treatment. As described above, the c-axis of the crystal is oriented in a direction parallel to the normal vector of the surface to be formed or the normal vector of the upper surface. Therefore, for example, when the shape of the CAAC-OS film is changed by etching or the like, the c-axis may not necessarily be parallel to the normal vector of the surface to be formed or the normal vector of the upper surface of the CAAC-OS film.

Moreover, the degree of crystallization in the CAAC-OS film is not necessarily uniform. For example, when crystal growth resulting in the CAAC-OS film occurs near the upper surface of the film, the degree of crystallization near the upper surface is higher than the degree of crystallization near the surface to be formed in some cases. Moreover, when an impurity is added to the CAAC-OS film, the crystallization in the region to which the impurity is added changes, and the degree of crystallization in the CAAC-OS film varies depending on the regions.

It _{should be noted that when the CAAC-OS film with InGaZnO 4} crystals is analyzed by the out-of-plane method, a peak of 2θ can also be observed at about 36°, in addition to the peak of 2θ at about 31°. A peak of 2θ at approximately 36° indicates that a crystal having no c-axis orientation is included in a portion of the CAAC-OS film. In the CAAC-OS film, it is preferable that the peak of 2θ appears at approximately 31° and the peak of 2θ does not appear at approximately 36°.

In the present specification, the trigonal system or rhombohedral system is included in the hexagonal system.

In a transistor using a CAAC-OS film, the change in electrical properties due to irradiation of visible light or ultraviolet light is small. Therefore, the transistor has high reliability.

The oxide semiconductor layer 408 may be, for example, any structure of an amorphous oxide semiconductor layer, a microcrystalline oxide semiconductor layer, or a CAAC-OS film, or a mixed film thereof, or comprising two or more films of these structures. It should be noted that it can be a laminated film.

It should be noted that in some cases, oxide insulating layer 406 has a lower degree of crystallinity than oxide semiconductor layer 408. The oxide insulating layer 406 may include an amorphous portion or a nanocrystal.

As other components, the transistor 300 covers the source electrode layer 410a and the drain electrode layer 410b, and an oxide insulating layer 412 and/or an oxide insulating layer 412 in contact with the oxide semiconductor layer 408 It may include a protective insulating layer 414 above.

As the oxide insulating layer 412, it is preferable to use a layer containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer 408, such as the oxide insulating layer 406. When such a material is used, it is possible to stabilize the interface between the oxide insulating layer 412 and the oxide semiconductor layer 408. Since the oxide insulating layer 412 is an insulating layer in contact with the back channel side of the oxide semiconductor layer 408, charge trapping at the interface between the two layers is reduced, thereby reducing the generation of parasitic channels.

In addition, oxide insulating layers containing one or more metal elements selected from the constituent elements of the oxide semiconductor layer 408 are brought into contact with the oxide semiconductor layer 408 so that the oxide semiconductor layer 408 is interposed therebetween, thereby forming the oxide semiconductor layer 408. ), when provided above and below the oxide insulating layers, may act to block entry from the outside by diffusion of impurities (such as nitrogen and metal elements) that may adversely affect the oxide semiconductor layer. Accordingly, when oxide insulating layers are provided so that the oxide semiconductor layer is interposed or surrounded, the composition and purity of the surrounded oxide semiconductor layer can be kept constant, and a semiconductor device having stable electrical properties can be obtained.

As the protective insulating layer 414, a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, a silicon nitride oxide film, or the like can be used.

<Structure Example 2 of a semiconductor device>

2 shows an example of the structure of the transistor 310. FIG. 2A is a plan view of the transistor 310, FIG. 2B is a cross-sectional view taken along a dashed-dotted line X2-Y2 in FIG. 2A, and FIG. 2C is a dashed-dotted line in FIG. 2A. It is a cross-sectional view taken along (V2-W2).

Like the transistor 300 of FIG. 1, the transistor 310 of FIG. 2 includes a gate electrode layer 402 on a substrate 400 having an insulating surface, and a gate insulating layer 404 on the gate electrode layer 402. , An oxide insulating layer 406 over the gate insulating layer 404, an oxide semiconductor layer 408 in contact with the oxide insulating layer 406 over the oxide insulating layer 406 and overlapping the gate electrode layer 402, and And a source electrode layer 410a and a drain electrode layer 410b electrically connected to the oxide semiconductor layer 408. As other components, the transistor 310 covers the source electrode layer 410a and the drain electrode layer 410b, and over the oxide insulating layer 412 and oxide insulating layer 412 in contact with the oxide semiconductor layer 408. A protective insulating layer 414 may be included.

Transistor 310 differs from transistor 300 in the structures of gate insulating layer 404 and oxide semiconductor layer 408. That is, the gate insulating layer 404 in the transistor 310 is a gate insulating layer 404a in contact with the gate electrode layer 402 and a gate insulating layer 404b between the gate insulating layer 404a and the oxide insulating layer 406. ). The oxide semiconductor layer 408 in the transistor 310 includes an oxide semiconductor layer 408a in contact with the oxide insulating layer 406 and an oxide semiconductor layer 408b in contact with the oxide insulating layer 412. Components other than the gate insulating layer 404 and the oxide semiconductor layer 408 in the transistor 310 are similar to other components of the transistor 300, and a description of the transistor 300 may be cited for this purpose. It should be noted.

In the transistor 310, the gate insulating layer 404a and the gate insulating layer 404b each include a silicon nitride film.

The gate insulating layer 404a has a thicker thickness than the gate insulating layer 404b and includes a silicon nitride film containing fewer defects. For example, the thickness of the gate insulating layer 404a is 300 nm or more and 400 nm or less. ^{In addition, in electron spin resonance (ESR) spectroscopy, a spin density of 1×10 17} spins//cm 3 or less, preferably 5×10 ¹⁶ spins/cm 3 or less, corresponding to the signal appearing at the center of Nc (at a g coefficient of 2.03) Having a silicon nitride film is used. When such a silicon nitride film having a thick thickness (eg, 300 nm or more) and including a small number of defects is provided, the withstand voltage of the gate insulating layer 404a may be, for example, 300V or more.

Since the gate insulating layer 404b is in contact with the oxide semiconductor layer 408, the gate insulating layer 404b must contain a silicon nitride film containing a low concentration of hydrogen, and the hydrogen concentration is at least that of the gate insulating layer 404a. It should be lower than the hydrogen concentration. For example, when the gate insulating layer 404a and the gate insulating layer 404b are formed by the plasma CVD method, the hydrogen concentration of the gate insulating layer 404b decreases the concentration of hydrogen contained in the supply gas, thereby reducing the gate insulating layer ( It may be made lower than the hydrogen concentration of 404a). In particular, when silicon nitride films are formed as the gate insulating layer 404a and the gate insulating layer 404b, the gate insulating layer 404b has a lower ammonia flow rate than in the supply gas for forming the gate insulating layer 404a. Or may be formed without using ammonia.

The thickness of the gate insulating layer 404b is 25 nm or more and 150 nm or less. Since a silicon nitride film containing a low concentration of hydrogen is provided as the gate insulating layer 404b, it is possible to reduce the ingress of hydrogen or hydrogen compounds (e.g., water) into the oxide insulating layer 406 and the oxide semiconductor layer 408 Do. Hydrogen in the oxide semiconductor causes carriers to be generated and the threshold voltage of the transistor to move in a negative direction. Therefore, when a silicon nitride film having a low hydrogen concentration is provided as the gate insulating layer 404b, the electrical properties of the transistor can be stabilized. In addition, when a silicon nitride film having a low hydrogen concentration is provided as the gate insulating layer 404b, the gate insulating layer 404b may also contain impurities such as hydrogen or a hydrogen compound contained in the gate insulating layer 404a as an oxide insulating layer. 406 and acts as a barrier film to prevent diffusion into the oxide semiconductor layer 408.

It should be noted that in this embodiment, both the gate insulating layer 404a and the gate insulating layer 404b are silicon nitride films, and the interface between these gate insulating layers may become unclear depending on materials or film formation conditions. Accordingly, in Figs. 2B and 2C, the interface between the gate insulating layer 404a and the gate insulating layer 404b is schematically shown by dotted lines. The same is true for the other drawings described below.

It is preferable that the oxide semiconductor layer 408a and the oxide semiconductor layer 408b included in the oxide semiconductor layer 408 have different compositions of the same constituent elements. When the oxide semiconductor layers containing indium and gallium are formed of the oxide semiconductor layer 408a and the oxide semiconductor layer 408b, in the oxide semiconductor layer 408a on the side (channel side) close to the gate electrode layer 402 It is preferable that the content of indium is higher than that of gallium (In> Ga). Further, it is preferable that the content of indium in the oxide semiconductor layer 408b on the side far from the gate electrode layer 402 (the back channel side) is equal to or less than the content of gallium (In≦Ga).

In an oxide semiconductor, the s orbitals of the heavy metal mainly contribute to carrier conduction, and the overlaps of the s orbitals tend to increase when the indium content in the oxide semiconductor increases. Therefore, an oxide having a composition of In> Ga has a higher mobility than an oxide having a composition of In? Ga. Moreover, in Ga, the formation energy of oxygen vacancies is larger, and thus oxygen vacancies are more difficult to generate than in In; Therefore, an oxide having a composition of In ≤ Ga has more stable properties than an oxide having a composition of In> Ga.

An oxide semiconductor having a composition of In>Ga is used on the channel side, and an oxide semiconductor having a composition of In≦Ga is used on the back channel side, so that the mobility and reliability of the transistor can be further improved. For example, the oxide semiconductor layer 408a may have an atomic ratio of In:Ga:Zn = 3:1:2, and the oxide semiconductor layer 408b may have an atomic ratio of In:Ga:Zn = 1:1:1 I can have it.

The oxide insulating layer 406 because the oxide semiconductor layer 408a and the oxide insulating layer 406 in contact with the oxide semiconductor layer 408b have different compositions of the same constituent elements, so that the interface of the two layers can be further stabilized. It should be noted that it is desirable to have this insulating property. The same applies to the oxide insulating layer 412 in contact with the oxide semiconductor layer 408b.

Also, oxide semiconductors having different crystallinities may be used for the oxide semiconductor layer 408a and the oxide semiconductor layer 408b. That is, the oxide semiconductor layers 408a and 408b may be formed using a combination of any of a single crystal oxide semiconductor, a polycrystalline oxide semiconductor, a nanocrystalline oxide semiconductor, an amorphous oxide semiconductor, and CAAC-OS as appropriate. It should be noted that the amorphous oxide semiconductor is easy to adsorb impurities such as hydrogen, it is easy to have oxygen vacancies, and thus can be easily n-type. Therefore, the oxide semiconductor layer 408a on the channel side is preferably formed using a crystal oxide semiconductor such as CAAC-OS.

When the oxide semiconductor layer 408b on the back channel side is formed using an amorphous oxide semiconductor, the oxide semiconductor layer 408b is oxygenated through an etching treatment to form the source electrode layer 410a and the drain electrode layer 410b. It is easy to have vacancy in and becomes n-type easily. Therefore, it is preferable that the oxide semiconductor layer 408b is formed using a crystalline oxide semiconductor.

14 is a diagram in the present embodiment having a stacked structure of a gate insulating layer GI, an oxide insulating layer OI1, oxide semiconductor layers OS1 and OS2, an oxide insulating layer OI2, and a protective insulating layer Passi. It is a diagram (schematic diagram) of the energy band of the transistor. Considering an ideal situation in which the gate insulating layer, the oxide insulating layers, the oxide semiconductor layers, and the protective insulating layer are all intrinsic, FIG. 14 shows that the gate insulating layer GI and the protective insulating layer Passi are silicon nitride films (band gaps). Eg): 5eV), and the oxide insulating layer (OI1) and the oxide insulating layer (OI2) are In:Ga:Zn = 1:3:2 (band gap (Eg): 3.6 eV) In-Ga-Zn oxide Insulation layers, the oxide semiconductor layer (OS1) is an In-Ga-Zn-based oxide semiconductor layer with In:Ga:Zn=3:1:2 (band gap (Eg): 2.8 eV), and an oxide semiconductor layer (OS2) A case of an In-Ga-Zn-based oxide semiconductor layer having an In:Ga:Zn=1:1:1 (band gap (Eg): 3.2 eV) is shown.

In FIG. 14, it should be noted that the oxide insulating layer OI1, the oxide insulating layer OI2, the oxide semiconductor layer OS1, and the oxide semiconductor layer OS2 are all assumed to have a relative dielectric constant of 15. In addition, the oxide insulating layer OI1 and the oxide insulating layer OI2 have a mobility of 4 cm 2 /Vs, the oxide semiconductor layer OS1 has a mobility of 25 cm 2 /Vs, and the oxide semiconductor layer OS2 It is considered to have a mobility of 10 cm 2 /Vs. Moreover, the gate insulating layer GI has a thickness of 325 nm, the oxide insulating layer OI1 has a thickness of 30 nm, the oxide semiconductor layer OS1 has a thickness of 10 nm, and the oxide semiconductor layer OS2 has a thickness of 10 nm. It is considered that it has a thickness, the oxide insulating layer OI2 has a thickness of 30 nm, and the protective insulating layer Passi has a thickness of 300 nm. Calculations are performed based on these assumptions.

14, on the gate electrode side (channel side) of the oxide semiconductor layer OS1, an energy barrier exists at the interface between the oxide semiconductor layer OS1 and the oxide insulating layer OI1. Similarly, on the back channel side (opposite of the gate electrode side) of the oxide semiconductor layer OS2, an energy barrier exists at the interface between the oxide semiconductor layer OS2 and the oxide insulating layer OI2. Since these energy barriers exist at the interfaces between the oxide semiconductor layers and the oxide insulating layers, the movement of carriers at the interfaces can be prevented; Thus, carriers move inside the oxide semiconductor layers and do not migrate from the oxide semiconductor layers to the oxide insulating layers. That is, when a stacked structure is formed such that oxide semiconductor layers are interposed between materials having band gaps stepwise larger than the band gap of the oxide semiconductor, carriers move inside the oxide semiconductor layer OS1 and the oxide semiconductor layer OS2. do.

<Method of manufacturing semiconductor device>

An example of a method of manufacturing the transistor 310 will be described below with reference to FIG. 3.

First, a gate electrode layer 402 is formed on a substrate 400 having an insulating surface.

There is no particular limitation on the substrate that can be used as the substrate 400 having an insulating surface, but it is at least necessary that the substrate has sufficient thermal resistance to withstand the heat treatment performed later. For example, glass substrates such as barium borosilicate glass, alumino borosilicate glass, and the like, ceramic substrates, crystal substrates, sapphire substrates, and the like can be used. Alternatively, a single crystal semiconductor substrate or polycrystalline semiconductor substrate made of silicon, silicon carbide, or the like, a composite semiconductor substrate made of silicon germanium, or the like, an SOI substrate, or the like may be used as the substrate 400. As yet another alternative, any of these substrates additionally equipped with a semiconductor device may be used as the substrate 400.

The gate electrode layer 402 may be formed using a metal material such as molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, neodymium, or scandium, or an alloying material containing any of these materials as a main component. I can. Alternatively, a semiconductor film typical of a polycrystalline silicon film doped with an impurity element such as phosphorus, or a silicide film such as a nickel silicide film may be used as the gate electrode layer 402. The gate electrode layer 402 may have a single layer structure or a stacked structure. The gate electrode layer 402 may have an inclined shape having an inclination angle of 30° or more and 70° or less, for example. Here, the inclination angle refers to the angle formed between the side surface of the layer and the bottom surface of the layer having an inclined shape.

The material of the gate electrode layer 402 is indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium oxide It may be a conductive material such as zinc oxide, or indium tin oxide to which silicon oxide is added.

Alternatively, the material of the gate electrode layer 402 is an In-Ga-Zn-based oxide containing nitrogen, an In-Sn-based oxide containing nitrogen, an In-Ga-based oxide containing nitrogen, and In-containing nitrogen. -Zn-based oxide, Sn-based oxide containing nitrogen, In-based oxide containing nitrogen, or a metal nitride (such as indium nitride, zinc nitride, tantalum nitride, or tungsten nitride). Each of these materials has a work function of 5 eV or more, which allows the threshold voltage of the transistor to be positive when used for the gate electrode layer 402. Thus, a normally off switching transistor can be provided.

Next, a gate insulating layer 404 including the gate insulating layer 404a and the gate insulating layer 404b is formed to cover the gate electrode layer 402 (see FIG. 3A). A silicon film containing nitrogen may be used for the gate insulating layer 404. In this embodiment, the gate insulating layer 404 is formed by laminating a gate insulating layer 404a including a silicon nitride film and a gate insulating layer 404b including a silicon nitride film. For in-plane fluctuations, mixing of particles, and reduction of the film formation cycle time, it is effective to use the CVD method to form the gate insulating layer 404. The CVD method is also effective in forming a film on a large substrate.

In this embodiment, the gate insulating layer 404a and the gate insulating layer 404b are successively formed by the plasma CVD method. First, using a mixed gas of silane (SiH ₄ ), nitrogen (N ₂ ) and ammonia (NH ₃ ) as a supply gas, a silicon nitride film is formed as the gate insulating layer 404a, and then the supply gas is silane (SiH _{4 ).} ) And nitrogen (N ₂ ), and a silicon nitride film is formed as the gate insulating layer 404b.

The silicon nitride film formed by the plasma CVD method using a mixed gas of silane (SiH ₄ ), nitrogen (N ₂ ) and ammonia (NH _{3 ) as a supply gas is a combination of silane (SiH 4} ) and nitrogen (N ₂ ) as a supply gas. It contains fewer defects than a silicon nitride film formed using a mixed gas. Thus, the gate insulating layer 404a contains at least fewer defects than the gate insulating layer 404b, and corresponds to a signal appearing at the center of Nc (at a g-factor of 2.003) in electron spin resonance (ESR) spectroscopy. ^It may have a spin density of 17 spins/cm3 or less, preferably 5×10 ^{16 spins/cm3 or less.} A silicon nitride film formed using a mixed gas containing ammonia provides better coverage than that formed using a mixed gas of silane and nitrogen as a feed gas. Therefore, it is effective to provide a silicon nitride film formed using the above-described mixed gas as the gate insulating layer in contact with the gate electrode layer 402. When the gate insulating layer 404a including a small number of defects is formed to have a thickness of 300 nm or more and 400 nm or less, the withstand voltage of the gate insulating layer 404 may be 300V or more.

On the other hand, the gate insulating layer 404b formed through the source gas not containing ammonia contains a lower hydrogen concentration than the gate insulating layer 404a. When such a film having a thickness of 25 nm or more and 150 nm or less is provided between the oxide insulating layer 406 and the gate electrode layer 402, from the gate insulating layer 404b to the oxide insulating layer 406 and the oxide semiconductor layer 408 It can reduce the ingress of hydrogen. The gate insulating layer 404b also functions as a barrier film to reduce the entry of hydrogen or a hydrogen compound contained in the gate insulating layer 404a into the oxide insulating layer 406 and the oxide semiconductor layer 408.

When the gate insulating layer 404a having a large thickness and containing a small number of defects and the gate insulating layer 404b having a low hydrogen concentration are stacked as the gate insulating layer 404, good withstand voltage is obtained, and at the same time, hydrogen and It is possible to reduce the diffusion of the same impurities into the oxide insulating layer 406 and the oxide semiconductor layer 408. Thus, it is possible to reduce electrostatic discharge damage to the transistor including the gate insulating layer 404 and stabilize its electrical properties.

Next, an oxide insulating layer and an oxide semiconductor layer are formed over the gate insulating layer 404b, and treated in an island form by an etching treatment, whereby the oxide insulating layer 406, and the oxide semiconductor layer 408a and the oxide semiconductor An oxide semiconductor layer 408 including layer 408b is formed (see Fig. 3B). Since the etching treatment is performed using one photomask, the oxide insulating layer 406 and the oxide semiconductor layer 408 have the same pattern shape in a plan view, and their ends are oriented to each other.

As the oxide insulating layer 406, an oxide insulating layer containing one or more metal elements selected from constituent elements of the oxide semiconductor layer 408 is provided. For example, it is preferable to use an insulating film such as a gallium oxide film, a gallium zinc oxide film, a gallium oxide gadolinium film, or an In-Ga-Zn-based oxide insulating film having a high gallium content and a low indium content.

The oxide semiconductor layer 408 may have an amorphous structure or a crystalline structure. When the formed oxide semiconductor layer has an amorphous structure, the oxide semiconductor layer may be subjected to heat treatment in a subsequent manufacturing process so that the oxide semiconductor layer 408 has a crystalline structure. The heat treatment for crystallizing the amorphous oxide semiconductor layer is performed at a temperature of 250° C. or more and 700° C. or less, preferably 400° C. or more, more preferably 500° C. or more, and further more preferably 550° C. or more. It should be noted that heat treatment can also act as another heat treatment in the manufacturing process.

The oxide insulating layer 406 and the oxide semiconductor layer 408 may be appropriately formed by a sputtering method, a molecular beam epitaxy (MBE) method, a CVD method, a pulsed laser deposition method, an atomic layer deposition (ALD) method, and the like. have.

When forming the oxide insulating layer 406 and the oxide semiconductor layer 408, the concentration of hydrogen to be contained is preferably reduced as much as possible. In order to reduce the concentration of hydrogen, for example, when the oxide insulating layer and oxide semiconductor layer are formed by sputtering, a high purity rare gas (typically argon) from which impurities such as hydrogen, water, hydroxyl groups and hydroxides are removed, high Pure oxygen or a high-purity mixed gas of rare gas and oxygen is suitably used as the atmospheric gas supplied to the film forming chamber of the sputtering apparatus.

The oxide insulating layer and the oxide semiconductor layer are formed in such a way that hydrogen and a sputtering gas from which moisture has been removed are introduced into the film forming chamber while the moisture remaining in the film forming chamber is removed, whereby the oxide insulating layer and the oxide semiconductor layer The concentration of hydrogen in the can be reduced. In order to remove moisture remaining in the film forming chamber, it is preferable to use an adsorption vacuum pump such as a cryo pump, an ion pump, or a titanium sublimation pump. Turbomolecular pumps with cold traps can alternatively be used. When the film forming chamber is _{evacuated to a cryopump with high performance to remove hydrogen molecules, compounds containing hydrogen atoms such as water (H 2} O) (preferably also compounds containing carbon atoms), etc., The concentration of impurities to be contained in the film formed in the film formation chamber can be reduced.

It should be noted that it is preferable that the oxide insulating layer and the oxide semiconductor layer are formed continuously without being exposed to air. By the continuous formation of the oxide insulating layer and the oxide semiconductor layer without exposure to air, hydrogen or a hydrogen compound (e.g., water) can be prevented from adhering to the surface of the oxide insulating layer or the surface of the oxide semiconductor layer stacked thereon. I can. Thus, the ingress of impurities can be reduced.

When the oxide insulating layer or oxide semiconductor layer is formed by the sputtering method, the relative density (filling factor) of the metal oxide target used for film formation is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. . By using a metal oxide target having a high relative density, a dense oxide film can be formed.

It should be noted that in order to reduce the impurity concentration of the oxide semiconductor layer, it is also effective to form the oxide semiconductor layer while the substrate 400 is maintained at a high temperature. The temperature at which the substrate 400 is heated may be 150° C. or more and 450° C. or less; The substrate temperature is preferably 200°C or more and 350°C or less. The crystalline oxide semiconductor layer can be formed by heating the substrate to a high temperature during formation.

When the CAAC-OS film is used as the oxide semiconductor layer 408, the CAAC-OS film can be obtained by the following methods. One method is to form an oxide semiconductor layer at a film forming temperature of 200° C. or higher and 450° C. or lower, thereby obtaining a c-axis orientation substantially perpendicular to the surface. Another method is to form a thin oxide semiconductor layer, which is then subjected to a heat treatment carried out at a temperature of 200° C. to 700° C., thereby obtaining a c-axis orientation substantially perpendicular to the surface. Another method is to form a first thin oxide semiconductor film, subject the film to a heat treatment performed at a temperature of 200°C or more and 700°C or less, and then form a second oxide semiconductor film, thereby forming a c -Get the axial orientation.

The oxide semiconductor used for the oxide semiconductor layer 408 contains at least indium (In). In particular, indium and zinc (Zn) are preferably contained. In addition, as a stabilizer for reducing fluctuations in electrical properties of a transistor using an oxide semiconductor, it is preferable that gallium (Ga) is additionally contained. It is preferable that at least one element selected from tin (Sn), hafnium (Hf), aluminum (Al) and zirconium (Zr) is contained as a stabilizer.

As other stabilizers, lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), One or more lanthanide elements selected from holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu) may be contained.

As an oxide semiconductor, for example, indium oxide, tin oxide, zinc oxide, an In-Zn-based oxide that is an oxide of a two-element metal, an In-Mg-based oxide or an In-Ga-based oxide, and an In-Ga that is an oxide of a three-element metal. -Zn-based oxide, In-Al-Zn-based oxide, In-Sn-Zn-based oxide, In-Hf-Zn-based oxide, In-La-Zn-based oxide, In-Ce-Zn-based oxide, In-Pr-Zn Oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-Dy-Zn oxide , In-Ho-Zn-based oxide, In-Er-Zn-based oxide, In-Tm-Zn-based oxide, In-Yb-Zn-based oxide or In-Lu-Zn-based oxide, or 4-element metal oxide In- Sn-Ga-Zn-based oxide, In-Hf-Ga-Zn-based oxide, In-Al-Ga-Zn-based oxide, In-Sn-Al-Zn-based oxide, In-Sn-Hf-Zn-based oxide or In- Hf-Al-Zn-based oxide may be used.

For example, "In-Ga-Zn-based oxide" means an oxide containing In, Ga, and Zn as major constituent elements, and there is no restriction on the ratio of In:Ga:Zn. Moreover, metal elements may be contained in addition to In, Ga and Zn.

Alternatively, _{a material expressed as InMO 3} (ZnO) _m (m>0, where m is not an integer) can be used as the oxide semiconductor. It should be noted that M represents one or more metal elements selected from Ga, Fe, Mn and Co. Alternatively, _{a material represented by In 2} SnO ₅ (ZnO) _n (n>0, where n is an integer) can be used as the oxide semiconductor.

For example, In:Ga:Zn = 1:1:1(=1/3:1/3:1/3), In:Ga:Zn = 2:2:1(=2/5:2/5:1 /5), or an In-Ga-Zn-based oxide with an atomic ratio of In:Ga:Zn = 3:1:2 (=1/2:1/6:1/3) or close to the above atomic ratios An oxide having an atomic ratio can be used. Alternatively, In:Sn:Zn = 1:1:1(=1/3:1/3:1/3), In:Sn:Zn = 2:1:3(=1/3:1/6 :1/2), or In:Sn:Zn = 2:1:5 (=1/4:1/8:5/8) In-Sn-Zn oxide having an atomic ratio of or above atomic ratios An oxide having an atomic ratio close to can be used.

However, the oxide semiconductor containing indium contained in the transistor is not limited to the materials given above; A material of an appropriate composition can be used for a transistor comprising an oxide semiconductor containing indium depending on the required electrical properties (eg, field-effect mobility, threshold voltage, and fluctuation). In order to obtain necessary electrical properties, it is preferable that the carrier concentration, impurity concentration, defect density, atomic ratio of metal elements to oxygen, interatomic distance, density, etc. are set appropriately.

For example, high field-effect mobility can be obtained relatively easily in a transistor containing an In-Sn-Zn-based oxide. In addition, in the case of a transistor including an In-Ga-Zn-based oxide, the field-effect mobility can be increased by reducing the defect density in the volume.

For example, "atomic ratio, In:Ga:Zn = a:b:c (a + b + c = 1), the composition of the oxide containing In, Ga, and Zn, the atomic ratio, In:Ga:Zn = A :B:C(A+B+C=1) is adjacent to the composition of the oxide containing In, Ga and Zn", for example a, b and c have the following relationship: (aA) ² + ( It should be noted that bB) ² + (cC) ² ≤ r ² , meaning that r meets a relationship that could be 0.05. This relationship applies equally to other oxides.

Moreover, it is preferable that a heat treatment is performed on the oxide insulating layer 406 and/or the oxide semiconductor layer 408 in order to remove excess hydrogen (including water and hydroxyl groups) (to perform dehydration or dehydrogenation). The heat treatment temperature is 300°C or more and 700°C or less, or less than the strain point of the substrate. The heat treatment may be performed under reduced pressure, nitrogen atmosphere, or the like. Hydrogen, an impurity that adds n-type conductivity, can be removed by heat treatment.

It should be noted that as long as this heat treatment for dehydration or dehydrogenation is performed after formation of the oxide insulating layer and/or oxide semiconductor layer, this heat treatment can be performed at any timing in the process of fabricating the transistor. This heat treatment for dehydration or dehydrogenation may be performed a plurality of times, and may also serve as another heat treatment.

When the oxide insulating layer contains an oxygen-excessive region, this heat treatment for dehydration or dehydrogenation can prevent the oxygen contained in the oxide insulating layer from being released through heat treatment, so that the oxide insulating layer and the oxide semiconductor It should be noted that it is preferred that the layer is carried out before it is treated in the form of an island.

During the heat treatment, it is preferable that water, hydrogen, and the like are not contained in nitrogen or a noble gas such as helium, neon or argon. Alternatively, the purity of nitrogen or rare gases such as helium, neon or argon introduced into the heat treatment apparatus is preferably 6N (99.9999%) or more, more preferably 7N (99.99999%) or more (i.e., the impurity concentration is 1 ppm. Or less, preferably 0.1 ppm or less).

In addition, after the oxide semiconductor layer 408 is heated by heat treatment, high-purity oxygen gas, high-purity dinitrogen monoxide gas, or ultra-dry air (using a cavity ring down laser spectrometer (CRDS) When measured with a dew point meter, 20 ppm (with a moisture content of -55° C. in terms of dew point) or less, preferably 1 ppm or less, more preferably 10 ppb or less), the heating temperature is maintained or gradually It can be introduced into the same furnace while it is decreasing. It is preferable that water, hydrogen, and the like are not contained in the oxygen gas or dinitrogen monoxide gas. The purity of the oxygen gas or dinitrogen monoxide gas introduced into the heat treatment apparatus is preferably 6N or more, more preferably 7N or more (i.e., the concentration of impurities in the oxygen gas or dinitrogen monoxide gas is preferably 1 ppm or less, more preferably Is 0.1 ppm or less). Oxygen gas or dinitrogen monoxide gas is the main constituent material of the oxide semiconductor and acts to supply oxygen which is reduced by the impurity removal step for dehydration or dehydrogenation, so that the oxide semiconductor layer is highly purified i-type (intrinsic ) It becomes possible to become an oxide semiconductor layer.

Oxygen (which contains at least one of an oxygen radical, an oxygen atom and an oxygen ion) is dehydrated or dehydrogenated, since oxygen, a major element of the oxide semiconductor, is also released and has the potential to be reduced by dehydration or dehydrogenation treatment. It is introduced into the oxide semiconductor layer that has undergone treatment, so that oxygen can be supplied to the layer.

By introducing and supplying oxygen to the dehydrated or dehydrogenated oxide semiconductor layer, the oxide semiconductor layer can be highly purified and become i-type (intrinsic). Changes in the electrical properties of a transistor having a highly purified i-type (intrinsic) oxide semiconductor are suppressed, and the transistor is electrically stable.

In the step of introducing oxygen into the oxide semiconductor layer 408, oxygen may be introduced directly into the oxide semiconductor layer 408, or may be introduced into the oxide semiconductor layer 408 through another insulating layer to be formed later. As a method of introducing oxygen (including at least one of oxygen radicals, oxygen atoms, and oxygen ions), an ion implantation method, an ion doping method, a plasma immersion ion implantation method, a plasma treatment, and the like can be used. A gas containing oxygen can be used for the oxygen introduction treatment. As the gas containing oxygen, oxygen, dinitrogen monoxide, nitrogen dioxide, carbon dioxide, carbon monoxide, and the like can be used. Further, a noble gas may be included in the gas containing oxygen for the oxygen introduction treatment.

For example, when oxygen ions are implanted into the oxide semiconductor layer 408 by the ion implantation method, the implantation amount may be 1×10 ¹³ ions/cm 2 or more and 5×10 ¹⁶ ions/cm 2 or less.

Alternatively, oxygen may be supplied to the oxide semiconductor layer 408 in the following manner: the oxide insulating layer 406 in contact with the oxide semiconductor layer is formed to include an oxygen-excess region; Heat treatment is performed in a state in which the oxide insulating layer 406 and the oxide semiconductor layer 408 are in contact with each other, so that excess oxygen contained in the oxide insulating layer 406 is diffused into the oxide semiconductor layer 408. This heat treatment can act as another heat treatment in the process of fabricating the transistor.

In order to provide an oxygen-rich region in the oxide insulating layer 406, for example, an oxide insulating layer may be formed in an oxygen atmosphere. Alternatively, oxygen may be introduced into the oxide insulating layer after it has been formed to provide an oxygen excess region within the oxide insulating layer 406.

As long as the timing of supplying oxygen to the oxide insulating layer 406 or the oxide semiconductor layer 408 is after the formation of the oxide insulating layer or the oxide semiconductor layer, the above is not particularly limited. The step of introducing oxygen may be performed a plurality of times.

Next, a conductive film is formed over the oxide semiconductor layer 408, which is then processed, whereby the source electrode layer 410a and the drain electrode layer 410b are formed (see C in Fig. 3).

The source electrode layer 410a and the drain electrode layer 410b are, for example, a metal film containing an element selected from Al, Cr, Cu, Ta, Ti, Mo and W, containing any of these elements as constituent elements. It may be formed using a metal nitride film (a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film), or the like. Alternatively, a film of a high melting point metal such as Ti, Mo, or W, or a metal nitride film thereof (e.g., a titanium nitride film, a molybdenum nitride film, or a tungsten nitride film) is placed on a metal film such as an Al film or a Cu film. And/or may be formed below. Also alternatively, the source electrode layer 410a and the drain electrode layer 410b may be formed using a conductive metal oxide. As a conductive metal oxide, indium oxide (In ₂ O ₃ ), tin oxide (SnO ₂ ), zinc oxide (ZnO), indium tin oxide (In ₂ O ₃ -SnO ₂ ), indium oxide zinc oxide (In ₂ O ₃₎ -ZnO), or any of these metal oxide materials containing silicon oxide may be used.

For the source electrode layer 410a and the drain electrode layer 410b, an In-Ga-Zn-O film containing nitrogen, an In-Sn-O film containing nitrogen, an In-Ga-O film containing nitrogen , A metal nitride film such as an In-Zn-O film containing nitrogen, a Sn-O film containing nitrogen, or an In-O film containing nitrogen may be used. These films contain the same constituent elements as the oxide semiconductor layer 408 and thus can form a stable interface with the oxide semiconductor layer 408. For example, the source electrode layer 410a and the drain electrode layer 410b have a stacked structure in which an In-Ga-Zn-O film containing nitrogen and a tungsten film are sequentially stacked from the side in contact with the oxide semiconductor layer 408. I can.

Thereafter, the oxide insulating layer 412 is formed to cover the source electrode layer 410a, the drain electrode layer 410b, and the exposed oxide semiconductor layer 408. Oxide insulating layer 412 may be formed using materials and fabrication methods similar to those for oxide insulating layer 406.

A protective insulating layer 414 is then formed over the oxide insulating layer 412 (see FIG. 3D).

The protective insulating layer 414 is formed by using a silicon oxide film, a gallium oxide film, an aluminum oxide film, a silicon nitride film, a silicon oxynitride film, an aluminum oxynitride film, a silicon nitride oxide film, or the like, in a plasma CVD method or a sputtering method. Can be formed by Since it is possible to further reduce electrostatic discharge damage to the semiconductor device during or after the manufacturing process, the protective insulating layer 414 is preferably a silicon film containing nitrogen, even more preferably a layer comprising a silicon nitride film. It should be noted that

In this way, the transistor 310 of this embodiment can be formed.

<Structure Example 3 of a semiconductor device>

10 shows an example of the structure of the transistor 320. 10A is a plan view of the transistor 320, FIG. 10B is a cross-sectional view taken along the dashed-dotted line X3-Y3 in FIG. 10A, and FIG. 10C is a dashed-dotted line V3 in FIG. 10A. It is a cross-sectional view taken along -W3).

Like the transistor 300 of FIG. 1, the transistor 320 of FIG. 10 includes a gate electrode layer 402 on a substrate 400 having an insulating surface, and a gate insulating layer 404 on the gate electrode layer 402. , An oxide insulating layer 406 over the gate insulating layer 404, an oxide semiconductor layer 408 in contact with the oxide insulating layer 406 over the oxide insulating layer 406 and overlapping the gate electrode layer 402, and And a source electrode layer 410a and a drain electrode layer 410b electrically connected to the oxide semiconductor layer 408. As other components, the transistor 320 covers the source electrode layer 410a and the drain electrode layer 410b, and over the oxide insulating layer 412 and oxide insulating layer 412 in contact with the oxide semiconductor layer 408. A protective insulating layer 414 may be included.

Transistor 320 differs from transistor 300 in the structures of gate insulating layer 404 and oxide semiconductor layer 408. That is, the gate insulating layer 404 in the transistor 320 is a gate insulating layer 404c in contact with the gate electrode layer 402, a gate insulating layer 404a over the gate insulating layer 404c, and a gate insulating layer ( A gate insulating layer 404b between 404a) and an oxide insulating layer 406. As in the transistor 310, the oxide semiconductor layer 408 in the transistor 320 has an oxide semiconductor layer 408a in contact with the oxide insulating layer 406 and an oxide semiconductor layer 412 in contact with the oxide insulating layer 412 ( 408b).

In the transistor 320, components other than the gate insulating layer 404 and the oxide semiconductor layer 408 are similar to other components of the transistor 300, and the description of the transistor 300 may be cited for this purpose. It should be noted that there is.

The structure of the oxide semiconductor layer 408 in the transistor 320 is similar to that in the transistor 310, for which a description of the transistor 310 may be cited. Note that in the transistor 320, the thickness of the region of the oxide insulating layer 408b in contact with the oxide insulating layer 412 is thinner than the thickness of the regions in contact with the source electrode layer 410a and the drain electrode layer 410b. Should be. The region having a thin thickness is partially etched at the time of processing the conductive film to form the source electrode layer 410a and the drain electrode layer 410b, or the source electrode layer 410a and the drain electrode layer 410b are formed. Then, it is formed by performing an etching treatment on the exposed area of the oxide semiconductor layer 408b. The region having a thin thickness serves as a channel formation region of the transistor 320. By reducing the thickness of the channel formation region, the resistance of regions in contact with the source electrode layer 410a and the drain electrode layer 410b may be made lower than the resistance of the channel formation region. Accordingly, the contact resistance between the source electrode layer 410a and the drain electrode layer 410b may be reduced.

The gate insulating layer 404 included in the transistor 320 includes a gate insulating layer 404c in contact with the gate electrode layer 402, and a gate insulating layer 404c in contact with the gate insulating layer 404c on the gate insulating layer 404c. 404a and a gate insulating layer 404b in contact with the oxide insulating layer 406.

In this embodiment, silicon nitride films are used as the gate insulating layer 404c, the gate insulating layer 404a, and the gate insulating layer 404b, and the gate insulating layers are continuously formed by the plasma CVD method. First, through the supply of a mixed gas of silane (SiH ₄ ) and nitrogen (N ₂ ) as a supply gas, a silicon nitride film is formed as the gate insulating layer 404c. Thereafter, the supply gas is _{changed to a mixed gas of silane (SiH 4} ), nitrogen (N ₂ ) and ammonia (NH ₃ ), and a silicon nitride film is formed as the gate insulating layer 404a. Thereafter, the supply gas is _{changed to a mixed gas of silane (SiH 4} ) and nitrogen (N ₂ ), and a silicon nitride film is formed as the gate insulating layer 404b.

The gate insulating layer 404c formed through the supply of a mixed gas of silane (SiH ₄ ) and nitrogen (N ₂ ) is formed in a film forming atmosphere containing less ammonia, and at least silane (SiH ₄ ) and nitrogen (N ₂ ) and ammonia (NH ₃ ) have a lower ammonia content than the gate insulating layer 404a formed through the supply of a gas mixture. Ammonia becomes a ligand for a metal complex by the action of a pair of electrons on a nitrogen atom. Thus, for example, when copper is used for the gate electrode layer 402, a gate insulating layer having a high ammonia content is provided in contact with the gate electrode layer, and copper is gated by a reaction represented by the following equation (1). It can diffuse into the insulating layer.

In the transistor 320 shown in FIG. 10, since a gate insulating layer 404c having an ammonia content lower than at least the gate insulating layer 404a is provided in contact with the gate electrode layer 402, the gate electrode layer 402 The diffusion of material (eg, copper) into the gate insulating layer 404 can be reduced. That is, the gate insulating layer 404c may act as a barrier film for a metal material included in the gate electrode layer 402. The gate insulating layer 404c may further improve the reliability of the transistor.

It should be noted that the gate insulating layer 404a and the gate insulating layer 404b in the gate insulating layer 404 included in the transistor 320 may be similar to those in the transistor 310. Including the gate insulating layer having the above structure, the transistor can be prevented from damage due to electrostatic discharge, and can have stable electrical characteristics. Thus, a highly reliable semiconductor device can be obtained.

The thickness of the gate insulating layer 404c is 30 nm or more and 100 nm or less, and preferably 30 nm or more and 50 nm or less. As described above, the thickness of the gate insulating layer 404a provided as a countermeasure against electrostatic discharge damage to the transistor is preferably 300 nm or more and 400 nm or less. The thickness of the gate insulating layer 404b, which functions as a barrier film for preventing diffusion of hydrogen into the oxide semiconductor layer 408, is preferably 25 nm or more and 150 nm or less. Preferably, the thickness of each gate insulating layer is appropriately adjusted so that the thickness of the gate insulating layer 404 (the total thickness of the gate insulating layer 404c, the gate insulating layer 404a, and the gate insulating layer 404b) is 355 nm to 550 nm. It should be noted that it falls within the scope of

<Structure Example 4 of a semiconductor device>

11 shows an example of the structure of the transistor 330. FIG. 11A is a plan view of the transistor 330, FIG. 11B is a cross-sectional view taken along the dashed-dotted line X4-Y4 of FIG. 11A, and FIG. 11C is a dashed-dotted line V4 of FIG. 11A. It is a cross-sectional view taken along -W4).

The transistor 330 shown in FIG. 11 includes a gate electrode layer 402 on a substrate 400 having an insulating surface, a gate insulating layer 404 on the gate electrode layer 402, and a gate insulating layer 404 on the gate electrode layer 402. Of the oxide insulating layer 406, the oxide semiconductor layer 408 in contact with the oxide insulating layer 406 over the oxide insulating layer 406 and overlapping the gate electrode layer 402, the oxide semiconductor layer 408 electrically An oxide insulating layer 412 and an oxide insulating layer covering the connected source electrode layer 410a and drain electrode layer 410b, the source electrode layer 410a and the drain electrode layer 410b, and in contact with the oxide semiconductor layer 408 412 and a protective insulating layer 414 over it.

Within the transistor 330, the protective insulating layer 414 comprises a layered structure comprising a protective insulating layer 414a in contact with the oxide insulating layer 412 and a protective insulating layer 414b over the protective insulating layer 414a. And for each of these, a silicon nitride film can be used.

The protective insulating layer 414a may be similar to the gate insulating layer 404b of the transistor 310. The protective insulating layer 414a can reduce the ingress of hydrogen or a hydrogen compound into the oxide insulating layer 412 and the oxide semiconductor layer 408; Thus, the electrical properties of the transistor can be further stabilized.

The protective insulating layer 414b may be similar to the gate insulating layer 404a of the transistor 310. The protective insulating layer 414b may reduce electrostatic discharge damage to the semiconductor device during or after the manufacturing process.

It should be noted that the other components of the transistor 330 are similar to the other components of the transistor 310, and a description of the transistor 310 may be cited for this purpose.

The structures of the transistors shown in Figs. 1, 2, 10 and 11 are partially different from each other; However, it should be noted that embodiments of the present invention are not limited to these structures, and various combinations are possible.

Each of the transistors described in this embodiment contains nitrogen as a gate insulating layer and has a large thickness (e.g., 325 nm or more and 550 nm or less), and a constituent element of an oxide semiconductor layer between the gate insulating layer and the oxide semiconductor layer. And an oxide insulating layer containing one or more metal elements selected from among them. Silicon films containing nitrogen can be formed using mass production techniques that have been applied in practical use. In addition, since a silicon film containing nitrogen and having a thick thickness is provided, the physical thickness of the gate insulating layer can be increased, which makes it possible to reduce the decrease in the withstand voltage of the transistor and further increase the withstand voltage, thereby Reduces electrostatic discharge damage to semiconductor devices. The oxide insulating layer can form a stable interface with the oxide semiconductor layer, and charge trapping at this interface can be reduced. Accordingly, deterioration of the transistor can be prevented, and a highly reliable transistor can be obtained.

The configurations, methods, and the like described in this embodiment may be appropriately combined with any of the configurations, methods, and the like described in other embodiments.

(Example 2)

A semiconductor device having a display function (also referred to as a display device) can be fabricated using any of the transistors described in the first embodiment. Moreover, some or all of the driving circuits including such transistors may be formed on the substrate on which the pixel portion is formed, thereby obtaining a system-on-panel.

In FIG. 4A, a sealant 4005 is provided to surround the pixel portion 4002 provided on the substrate 4001, and the pixel portion 4002 is sealed using the substrate 4006. In FIG. 4A, the signal line driving circuit 4003 and the scan line driving circuit 4004, each formed using a single crystal semiconductor film or a polycrystalline semiconductor film on an IC or on a separately prepared substrate, are sealed on the substrate 4001. It is mounted in an area different from the area enclosed by the element 4005. Various signals and potentials are supplied from flexible printed circuits (FPCs) 4018a and 4018b to the pixel portion 4002 through a signal line driving circuit 4003 and a scan line driving circuit 4004.

In FIGS. 4B and 4C, a sealant 4005 is provided to surround the pixel portion 4002 and the scan line driving circuit 4004 provided on the substrate 4001. The substrate 4006 is provided on the pixel portion 4002 and the scan line driving circuit 4004. As a result, the pixel portion 4002 and the scan line driving circuit 4004 are sealed together with the display element by the substrate 4001, the sealant 4005, and the substrate 4006. 4B and C, a signal line driving circuit 4003 formed using a single crystal semiconductor film or a polycrystalline semiconductor film on an IC chip or on a separately prepared substrate is surrounded by a sealant 4005 on the substrate 4001. It is mounted in an area different from that of the area. 4B and 4C, various signals and potentials are supplied from the FPC 4018 to the pixel portion 4002 through the signal line driving circuit 4003 and the scan line driving circuit 4004.

Each of B and C of FIG. 4 shows an example in which the signal line driving circuit 4003 is separately formed and mounted on the substrate 4001, but an embodiment of the present invention is not limited to this structure. The scan line driving circuit may be formed separately and then mounted, or only a portion of the signal line driving circuit or a portion of the scan line driving circuit may be formed separately and then mounted.

There is no particular limitation on the method of connecting the separately formed driving circuit, and the chip-on-glass (COG) method, wire bonding method, tape automated bonding method, etc. can be used. It should be noted. 4A shows an example in which the signal line driving circuit 4003 and the scan line driving circuit 4004 are mounted by the COG method. 4B shows an example in which the signal line driving circuit 4003 is mounted by the COG method. 4C shows an example in which the signal line driving circuit 4003 is mounted by the TAB method.

It is well known that display devices include a panel in which display elements are sealed, and a module in which an IC including a controller or the like is mounted on the panel. In particular, in the present specification, a display device means an image display device, a display device, or a light source (including a lighting device). Moreover, the display device also includes the following modules within its category: a module to which a connector such as FPC or TCP is attached; A module having a TCP in which a printed wiring board is provided at the end; And a module in which an integrated circuit (IC) is mounted directly on the display element by the COG method.

The pixel portion and the scan line driving circuit provided on the substrate include a plurality of transistors, and any of the transistors described in the first embodiment may be applied to such a transistor.

As the display element provided in the display device, a liquid crystal element (also referred to as a liquid crystal display element) or a light emitting element (also referred to as a light-emitting display element) can be used. Light-emitting elements include elements whose luminance is controlled by current or voltage within their category, and in particular include inorganic electroluminescent (EL) elements, organic EL elements, and the like. Moreover, a display medium in which the contrast is changed by an electric effect, such as an electronic ink display device (electronic paper), can be used.

Embodiments of the semiconductor device will be described with reference to FIGS. 4, 5 and 6. 6 corresponds to cross-sectional views along the line M-N in FIG. 4B.

4 and 6, the semiconductor device includes a connection terminal electrode 4015 and a terminal electrode 4016. The connection terminal electrode 4015 and the terminal electrode 4016 are electrically connected to terminals included in the FPC 4018 or 4018b through an anisotropic conductive layer 4019.

The connection terminal electrode 4015 is formed using the same conductive layer as the first electrode layer 4034, and the terminal electrode 4016 has the same conductive layer as the source electrode layers and the drain electrode layers of the transistors 4010 and 4011. Is formed using

The pixel portion 4002 and the scan line driving circuit 4004 provided on the substrate 4001 include a plurality of transistors. 6 illustrates a transistor 4010 included in the pixel unit 4002 and a transistor 4011 included in the scan line driving circuit 4004. In Fig. 6A, an oxide insulating layer 4030 and a protective insulating layer 4032 are provided over the transistors 4010 and 4011. In Fig. 6B, an insulating layer 4021 serving as a planarizing insulating layer is additionally provided.

Any of the transistors described in Embodiment 1 may be applied to the transistor 4010 and the transistor 4011. Described in this embodiment is an example in which a transistor having a structure similar to that of the transistor 300 described in Embodiment 1 is used. Transistors 4010 and 4011 are lower-gate transistors.

Each of the transistors 4010 and 4011 is an oxide insulating layer 4020b and an oxide insulating layer 4030, which are insulating layers in contact with the oxide semiconductor layer, and contain one or more metal elements selected from constituent elements of the oxide semiconductor layer. It includes oxide insulating layers, and also includes, as the gate insulating layer 4020a, a silicon film containing nitrogen and having a thick thickness (eg, 325 nm or more and 550 nm or less). Thus, within the transistors 4010 and 4011, the change in electrical characteristics is reduced, and electrostatic discharge damage is reduced.

In addition, the conductive layer may be provided to overlap the channel formation region in the oxide semiconductor layer of the transistor 4011 for the driving circuit. By providing the conductive layer so as to overlap the channel formation region in the oxide semiconductor layer, the amount of change in the threshold voltage of the transistor 4011 can be further reduced. The conductive layer may have a potential equal to or different from the potential of the gate electrode layer of the transistor 4011 and may function as a second gate electrode layer. The potential of the conductive layer may be in a floating state.

In addition, the conductive layer has a function of blocking an external electric field, that is, a function of preventing an external electric field from affecting the inside (a circuit portion including a transistor) (in particular, a function of preventing static electricity). The blocking function of the conductive layer can prevent variations in electrical characteristics of the transistor due to the influence of an external electric field such as static electricity.

The transistor 4010 provided in the pixel portion 4002 is electrically connected to a display element for forming a display panel. Various display elements can be used as display elements as long as the display can be performed.

An example of a liquid crystal display device including a liquid crystal element as a display element is shown in Fig. 6A. In Fig. 6A, the liquid crystal element 4013 includes a first electrode layer 4034, a second electrode layer 4031, and a liquid crystal layer 4008. The insulating layers 4038 and 4033 serving as alignment layers are provided so that the liquid crystal layer 4008 is interposed therebetween. The second electrode layer 4031 is provided on the substrate 4006 side, and the first electrode layer 4034 and the second electrode layer 4031 are stacked with the liquid crystal layer 4008 interposed therebetween.

The thermal spacers 4035 are obtained through selective etching of the insulating layer, and are provided to control the thickness (cell gap) of the liquid crystal layer 4008. Alternatively, spherical spacers can be used.

When a liquid crystal element is used as a display element, a thermotropic liquid crystal, a ferroelectric liquid crystal, an antiferroelectric liquid crystal, and the like can be used. These liquid crystal materials may be a low-molecular compound or a high-molecular compound. The liquid crystal materials (liquid crystal compositions) represent a cholesteric phase, a smectic phase, a cubic phase, a chiral nematic phase, an isotropic phase, and the like according to conditions.

Alternatively, a liquid crystal composition exhibiting a blue phase in which an alignment layer is unnecessary may be used for the liquid crystal layer 4008. In this case, the liquid crystal layer 4008 contacts the first electrode layer 4034 and the second electrode layer 4031. The blue phase is one of the liquid crystal states generated just before the cholesteric phase changes to an isotropic phase while the temperature of the cholesteric liquid crystal rises. The blue phase can be expressed using a liquid crystal composition that is a mixture of liquid crystal and chiral material. In order to increase the temperature range in which the blue phase is expressed, the liquid crystal layer can be formed by adding a polymerizable monomer, a polymerization initiator, or the like to the liquid crystal composition expressing the blue phase, and performing a polymer stabilization treatment. The liquid crystal composition expressing a blue phase has a short response time and has light isotropy, which contributes to the elimination of the alignment treatment and reduction of the viewing angle dependence. In addition, since the alignment film does not need to be provided and the polishing treatment is not required, electrostatic discharge damage caused by the polishing treatment can be prevented, and defects and damages of the liquid crystal display device during the manufacturing process can be reduced. Accordingly, the productivity of the liquid crystal display device can be improved.

The resistivity of the liquid crystal material is 1×10 ⁹ Ω·cm or more, preferably 1×10 ¹¹ Ω·cm or more, and more preferably 1×10 ¹² Ω·cm or more. It should be noted that in this specification, the resistivity was measured at 20°C.

The size of the memory capacitor formed in the liquid crystal display device is set in consideration of a leakage current of a transistor provided in the pixel portion or the like so that electric charges can be maintained for a predetermined period. The size of the memory capacitor may be set in consideration of the off-state current of the transistor. By using a transistor comprising an oxide semiconductor layer disclosed herein, it is sufficient to provide a memory capacitor having a capacitance of less than 1/3, preferably less than 1/5 of the liquid crystal capacitance of each pixel.

In the transistor including the oxide semiconductor layer disclosed herein, the off-state current (off-state current) may be controlled to be small. Thus, an electrical signal such as an image signal can be maintained for a long period of time, and the recording interval can be set longer. Therefore, the frequency of the refresh operation can be reduced, which results in an effect of suppressing power consumption.

The transistor including the oxide semiconductor layer disclosed herein may have a relatively high field effect mobility, and thus may operate at a high speed. For example, when such a transistor is used for a liquid crystal display, the switching transistor in the pixel portion and the driver transistor in the driving circuit portion may be formed on one substrate. In addition, by using such a transistor in the pixel portion, a high-quality image can be provided.

For liquid crystal displays, twist nematic (TN) mode, in-plane-switching (IPS) mode, flinge field switching (FFS) mode, axially symmetrically aligned micro-cell (ASM) mode, optical compensation birefringence (OCB) A mode, a ferroelectric liquid crystal (FLC) mode, an antiferroelectric liquid crystal (AFLC) mode, and the like may be used.

A normal black liquid crystal display device such as a transmissive liquid crystal display device using a vertical alignment (VA) mode may be used. Some examples are given as vertical orientation mode. For example, a multi-domain vertical orientation (MVA) mode, a patterned vertical orientation (PVA) mode, or an advanced super view (ASV) mode can be used. Moreover, this embodiment can be applied to a VA liquid crystal display. VA liquid crystal display devices have a type in which the alignment of liquid crystal molecules of a liquid crystal display panel is controlled. In a VA liquid crystal display, liquid crystal molecules are aligned in a direction perpendicular to the panel surface when no voltage is applied. Moreover, a method called multi-domainization or multi-domain design can be used, in which one pixel is divided into some regions (subpixels) and molecules are oriented in different directions in each region.

In the display device, a light member (optical substrate) such as a black matrix (light blocking layer), a polarizing member, a retarding member, or an antireflection member, or the like is provided as appropriate. For example, circularly polarized light can be obtained using a polarizing substrate and a retarding substrate. In addition, a backlight, a side light, or the like can be used as a light source.

As a display method in the pixel unit, a sequential method, an interlaced method, or the like may be employed. Moreover, the color elements controlled within a pixel in color display are not limited to three colors: R, G and B (corresponding to red, green and blue respectively). For example, R, G, B, and W (W corresponds to white); R, G, B, and at least one of yellow, cyan, magenta, and the like; Etc. can be used. Moreover, the sizes of the display areas are different between each point of the color elements. One embodiment of the present invention disclosed herein is not limited to an application for a display device for a color display; It should be noted that an embodiment of the present invention disclosed in this specification can also be applied to a display device for a single color display.

Alternatively, as a display element included in the display device, a light-emitting element using electroluminescence may be used. Light-emitting elements using electroluminescence are classified according to whether the light-emitting material is an organic compound or an inorganic compound. In general, the former is referred to as an organic EL element, and the latter is referred to as an inorganic EL element.

In the organic EL element, through the application of a voltage to the light-emitting element, electrons and holes are separately injected from a pair of electrodes into the layer containing the light-emitting organic compound, so that a current flows. The carriers (electrons and holes) are recombined, and thus the light-emitting organic compound is excited. The light-emitting organic compound returns from the excited state to the ground state, thereby emitting light. Due to this mechanism, this light-emitting element is referred to as a current-excited light-emitting element. In this embodiment, an example in which an organic EL element is used as a light emitting element is described.

Inorganic EL elements are classified into distributed inorganic EL elements and thin-film inorganic EL elements according to the structures of those elements. The dispersed inorganic EL element has a light emitting layer in which particles of a light emitting material are dispersed in a binder, and the light emitting mechanism is light emission of a donor-acceptor recombination type using a donor level and an acceptor level. The thin film inorganic EL element has a structure in which a light emitting layer is interposed between dielectric layers, these are further interposed between electrodes, and the light emitting mechanism is a limited type of light emission using inner shell electron transition of metal ions. It should be noted that an example of an organic EL element as a light emitting element has been described herein.

In order to extract the light emitted from the light emitting element, at least one of the pairs of electrodes has a light transmitting property. The transistor and the light emitting element are formed on one substrate. The light emitting element comprises: a top emission structure in which light emission is extracted through an opposite surface of the substrate; A lower emission structure in which light emission is extracted through the surface of the substrate side; Or a double emission structure in which light emission is extracted through the opposite surface and the substrate-side surface of the substrate, and a light-emitting element having any of these emission structures may be used.

An example of a light emitting device including a light emitting element as a display element is shown in Figs. 5 and 6B.

FIG. 5A is a plan view of the light emitting device, and FIG. 5B is a cross-sectional view taken along dashed-dotted lines S1-T1, S2-T2, and S3-T3 in FIG. 5A. It should be noted that the electroluminescent layer 542 and the second electrode layer 543 are not shown in the plan view of FIG. 5A.

The light emitting device shown in FIG. 5 includes, over a substrate 500, a transistor 510, a capacitor 520, and an intersection 530 of wiring layers. Transistor 510 is electrically connected to light emitting element 540. It should be noted that FIG. 5 shows a bottom emitting light emitting device in which light from a light emitting element 540 is extracted through a substrate 500.

Any of the transistors described in Embodiment 1 may be applied to transistor 510. What is described in this embodiment is an example in which a transistor having a structure similar to that of the transistor 300 described in the first embodiment is used. Transistor 510 is a lower-gate transistor.

The transistor 510 includes gate electrode layers 511a and 511b, a gate insulating layer 502, an oxide insulating layer 512, an oxide semiconductor layer 514, and conductive layers serving as a source electrode layer and a drain electrode layer ( 513a and 513b).

The transistor 510 is an oxide insulating layer 512 that is an insulating layer that is in contact with the oxide semiconductor layer 514, and includes an oxide insulating layer containing one or more metal elements selected from constituent elements of the oxide semiconductor layer 514, and a gate. As the insulating layer 502, a silicon film containing nitrogen and having a thick thickness (eg, 325 nm or more and 550 nm or less) is included. Through this configuration, charge trapping at the interface between the oxide semiconductor layer 514 and the oxide insulating layer 512 can be reduced, and the transistor 510 can have good electrical properties. In addition, electrostatic discharge damage to the transistor 510 can be prevented. Thus, a highly reliable semiconductor device can be provided with a high yield. It is noted that as the insulating layer 524 over the oxide semiconductor layer 514 and in contact with the oxide semiconductor layer 514, it is preferable to use an oxide insulating layer similar to the oxide insulating layer 512. As the insulating layer 525 over the insulating layer 524 and in contact with the insulating layer 524, it is preferable to use an insulating layer similar to the gate insulating layer 502.

The capacitor 520 includes conductive layers 521a and 521b, a gate insulating layer 502, an oxide insulating layer 522, an oxide semiconductor layer 526, and a conductive layer 523. The gate insulating layer 502, the oxide insulating layer 522 and the oxide semiconductor layer 526 are interposed between the conductive layers 521a and 521b and the conductive layer 523, thereby forming a capacitor.

The intersection 530 of the wiring layers is an intersection of the gate electrode layers 511a and 511b and the conductive layer 533. The gate electrode layers 511a and 511b and the conductive layer 533 cross each other through a gate insulating layer 502 therebetween.

In this embodiment, a titanium film having a thickness of 30 nm is used for the gate electrode layer 511a and the conductive layer 521a, and a copper thin film having a thickness of 200 nm is used for the gate electrode layer 511b and the conductive layer 521b. Is used for Therefore, the gate electrode layer has a laminated structure of a titanium film and a copper thin film.

An In-Ga-Zn-O film with a thickness of 25 nm is used for the oxide semiconductor layers 514 and 526.

An interlayer insulating layer 504 is formed over the transistor 510, the capacitor 520, and the intersection 530 of the wiring layers. Over the interlayer insulating layer 504, a color filter layer 505 is provided in an area overlapping the light emitting element 540. An insulating layer 506 serving as a planarizing insulating layer is provided over the interlayer insulating layer 504 and the color filter layer 505.

A light emitting element 540 having a stacked structure in which the first electrode layer 541, the electroluminescent layer 542 and the second electrode layer 543 are sequentially stacked is provided on the insulating layer 506. The first electrode layer 541 and the conductive layer 513a are in contact with each other within the opening, formed within the insulating layer 506 and the interlayer insulating layer 504 to reach the conductive layer 513a; Accordingly, the light emitting element 540 and the transistor 510 are electrically connected to each other. It should be noted that one partition 507 is provided to cover a portion of the first electrode layer 541 and the opening.

Further, a photosensitive acrylic film having a thickness of 1500 nm and a photosensitive polyimide film having a thickness of 1500 nm may be used for the insulating layer 506 and the partition 507, respectively.

For the color filter layer 505, for example, a chromatic light transmitting resin may be used. As such a chromatic light transmitting resin, a photosensitive organic resin or a non-photosensitive organic resin may be used. It is preferred that a photosensitive organic resin layer be used, because the number of resist masks can be reduced, resulting in simplification of the process.

The chromatic colors are colors excluding colorless colors such as black, gray and white. The color filter layer is formed using a material that transmits only chromatic color light. As the chromatic color, red, green, blue, and the like may be used. Cyan, magenta, yellow, etc. may also be used. “To transmit only chromatic color light” means that the light transmitted through the color filter layer has a peak at the wavelength of chromatic color light. The thickness of the color filter layer can be controlled to be appropriately optimized in consideration of the relationship between the concentration of the colored material to be included and the transmittance of light. For example, the thickness of the color filter layer 505 may be 1500 nm or more and 2000 nm or less.

In the light emitting device shown in Fig. 6B, the light emitting element 4513 is electrically connected to a transistor 4010 provided in the pixel portion 4002. The structure of the light emitting element 4513 is not limited to the illustrated stacked structure including a first electrode layer 4034, an electroluminescent layer 4511, and a second electrode layer 4031. The structure of the light-emitting element 4513 may be appropriately changed according to the direction in which light is extracted from the light-emitting element 4513, or the like.

The partition 4510 and the partition 507 may be formed using an organic insulating material or an inorganic insulating material. It is particularly preferred that the partitions 4510 and 507 are formed with openings over the first electrode layers 4034 and 541 using a photosensitive resin material, and the sidewalls of each opening are formed as an inclined surface having a continuous curvature. .

Each of the electroluminescent layers 4511 and 542 may be formed using a single layer or a plurality of stacked layers.

A protective film may be formed on each of the second electrode layers 4031 and 543 and the compartments 4510 and 507 to prevent entry of the light emitting elements 4513 and 540 such as oxygen, hydrogen, moisture, carbon dioxide, etc. have. As the protective film, a silicon nitride film, a silicon nitride oxide film, a DLC film, or the like can be formed.

Moreover, the light-emitting elements 4513 and 540 may be covered with respective layers containing an organic compound formed by a vapor deposition method so that oxygen, hydrogen, moisture, carbon dioxide, etc. do not enter the light-emitting elements 4513 and 540. have.

In addition, in the space sealed by the substrate 4001, the substrate 4006 and the sealant 4005, a filler 4514 is provided for sealing. In this way, it is recommended that the light emitting element 4513 and the like be packaged (sealed) with a protective film (such as a laminate film or an ultraviolet curable resin film) or a cover material having high airtightness and low deaeration, so as not to be exposed to outside air desirable.

As the filler 4514, not only an inert gas such as nitrogen or argon, but also an ultraviolet curable resin or a thermosetting resin may be used. For example, polyvinyl chloride (PVC), acrylic resin, polyimide, epoxy resin, silicone resin, polyvinyl butyral (PVB), or ethylene vinyl acetate (EVA) copolymer may be used. For example, nitrogen is used as a filler.

In addition, when necessary, a light film such as a polarizing plate, a circular polarizing plate (including an elliptically polarizing plate), a retarding plate (a quarter-wave plate or a half-wave plate), or a color filter is appropriately provided on the light-emitting surface of the light-emitting element. Can be. Moreover, the polarizing plate or the circular polarizing plate may have an antireflection film. For example, in order to reduce diffuse reflection, a diffuse reflection prevention treatment in which reflected light can be diffused by irregularities on the surface may be performed.

Moreover, electronic paper on which electronic ink is driven can be provided as a display device. Electronic paper is also referred to as an electrophoretic display device (electrophoretic display), and is advantageous in that it has the same level of readability as flat paper, has lower power consumption than other display devices, and can be made thin and light.

Although the electrophoretic display device may have various modes, the electrophoretic display device contains a plurality of microcapsules dispersed in a solvent, and each microcapsule contains positively charged first particles and negatively charged second particles. Contains. By applying an electric field to the microcapsules, these particles in the microcapsules move in opposite directions, and only the colors of the particles gathered on one side are displayed. It should be noted that the first particles and the second particles each contain a pigment and do not move without an electric field. Moreover, the first particles and the second particles have different colors (which may be colorless).

The solution in which the above microcapsules are dispersed in a solvent is referred to as electronic ink. By using a color filter or particles with a pigment, a color display can also be achieved.

4, 5 and 6, it should be noted that glass substrates as well as flexible substrates can be used as the substrate 4001, the substrate 500, and the substrate 4006. For example, a plastic substrate having light transmission properties, etc. may be used. As the plastic, a glass fiber reinforced plastic (FRP) plate, a polyvinyl fluoride (PVF) film, a polyester film, or an acrylic resin film can be used. When the light transmission property is not required, a metal substrate (metal film) such as aluminum, stainless steel, or the like can be used. For example, a sheet having a structure in which an aluminum foil is interposed between PVF films or polyester films may be used.

In addition, the insulating layers 4021 and 506, each serving as a planarizing insulating layer, may be formed using an organic material having heat resistance such as acrylic resin, polyimide, benzocyclobutene-based resin, polyamide, or epoxy resin. have. In addition to these organic materials, it is also possible to use low dielectric constant materials (low k materials) such as siloxane-based resins, phosphate glass (PSG), or boron phosphate glass (BPSG). It should be noted that each of the insulating layers 4021 and 506 may be formed by stacking a plurality of insulating layers formed using any of these materials.

There is no particular limitation on the method of forming the insulating layers 4021 and 506, and sputtering method, spin coating, dipping, spray coating, droplet ejection method (such as inkjet method), screen printing, offset printing, etc. may be used depending on the material. I can.

The first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 are indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, and titanium oxide. It may be formed using a light-transmitting conductive material such as indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide, indium tin oxide to which silicon oxide is added, or graphene.

The first electrode layers 4034 and 541 and the second electrode layers 4031 and 543 are tungsten (W), molybdenum (Mo), zirconium (Zr), hafnium (Hf), vanadium (V), and niobium (Nb). , Metals such as tantalum (Ta), chromium (Cr), cobalt (Co), nickel (Ni), titanium (Ti), platinum (Pt), aluminum (Al), copper (Cu), or silver (Ag); Alloys thereof; And it may be formed using one or a plurality of types selected from these nitrides.

In this embodiment, since the light emitting device shown in Fig. 5 has a lower emission structure, the first electrode layer 541 has light-emitting characteristics, and the second electrode layer 543 has light reflection characteristics. Therefore, when using a metal film as the first electrode layer 541, it is preferable that the film is made sufficiently thin to ensure light transmission properties; When using a light-transmitting conductive layer as the second electrode layer 543, a light-reflecting conductive layer is preferably laminated.

A conductive composition containing a conductive polymer (also referred to as a conductive polymer) can be used for the first electrode layers 4034 and 541 and the second electrode layers 4031 and 543. As the conductive polymer, a so-called π-electron conjugated conductive polymer can be used. For example, polyaniline or a derivative thereof, polypyrrole or a derivative thereof, polythiophene or a derivative thereof, a copolymer of two or more of aniline, pyrrole, and thiophene or a derivative thereof may be mentioned.

A protection circuit for protecting the driving circuit may also be provided. The protection circuit is preferably formed using nonlinear elements.

By using any of the transistors described in Embodiment 1 described above, the semiconductor device can have various functions.

The configurations, methods, and the like described in this embodiment may be appropriately combined with any of the configurations, methods, and the like described in other embodiments.

(Example 3)

A semiconductor device having an image sensor function for reading information on an object can be fabricated using any of the transistors described in the first embodiment.

7A shows an example of a semiconductor device having an image sensor function. 7A is an equivalent circuit diagram of a photosensor, and FIG. 7B is a cross-sectional view showing a part of the photosensor.

One electrode of the photodiode 602 is electrically connected to the photodiode reset signal line 658 and the other electrode of the photodiode 602 is electrically connected to the gate of the transistor 640. One of the source and drain of the transistor 640 is electrically connected to the photosensor reference signal line 672, and the other of the source and drain of the transistor 640 is electrically connected to one of the source and drain of the transistor 656. Connected. The gate of the transistor 656 is electrically connected to the gate signal line 659 and the other of its source and drain is electrically connected to the photosensor output signal line 671.

It should be noted that in the circuit diagrams herein, a transistor comprising an oxide semiconductor layer is denoted by the symbol "OS" so that it can be identified as a transistor comprising an oxide semiconductor layer. In FIG. 7A, the transistor 640 and the transistor 656 are transistors each including an oxide semiconductor layer, and any of the transistors described in Example 1 may be applied thereto. What has been described in this embodiment is an example in which a transistor having a structure similar to that of the transistor 300 described in Embodiment 1 is used. Transistor 640 is a lower-gate transistor.

7B is a cross-sectional view of the photodiode 602 and the transistor 640 in the photosensor. A photodiode 602 and a transistor 640 serving as sensors are provided on a substrate 601 (element substrate) having an insulating surface. A substrate 613 is provided over the photodiode 602 and transistor 640 using an adhesive layer 608.

An insulating layer 631, an insulating layer 632, an interlayer insulating layer 633, and an interlayer insulating layer 634 are provided over the transistor 640. The photodiode 602 includes an electrode layer 641b formed on the interlayer insulating layer 633, a first semiconductor film 606a sequentially stacked on the electrode layer 641b, a second semiconductor film 606b, and a third Using the same layer as the electrode layer 642 and the electrode layer 641b formed on the semiconductor film 606c, the interlayer insulating layer 634 and electrically connected to the electrode layer 641b through the first to third semiconductor films. And an electrode layer 641a formed by the method and electrically connected to the electrode layer 642.

The electrode layer 641b is electrically connected to the conductive layer 643 formed over the interlayer insulating layer 634, and the electrode layer 642 is electrically connected to the conductive layer 645 through the electrode layer 641a. The conductive layer 645 is electrically connected to the gate electrode layer of the transistor 640 and the photodiode 602 is electrically connected to the transistor 640.

Here, a semiconductor film having p-type conductivity as the first semiconductor film 606a, a high-resistance semiconductor film (i-type semiconductor film) as the second semiconductor film 606b, and an n-type semiconductor film 606c as the third semiconductor film 606c A pin-type photodiode in which a conductive semiconductor film is stacked is shown as an example.

The first semiconductor film 606a is a p-type semiconductor film, and may be formed using an amorphous silicon film containing an impurity element that adds p-type conductivity. The first semiconductor film 606a is formed by a plasma CVD method using a semiconductor source gas containing an impurity element belonging to Group 13 (eg, boron (B)). As the semiconductor source gas, silane (SiH ₄ ) may be used. Alternatively, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF ₄ , etc. can be used. As a further alternative, an amorphous silicon film containing no impurity element may be formed, and then the impurity element may be implanted into the amorphous silicon film by a diffusion method or an ion implantation method. In order to diffuse the impurity element, heating or the like may be performed after the impurity element is implanted by an ion implantation method or the like. In this case, as a method of forming an amorphous silicon film, an LPCVD method, a vapor deposition method, a sputtering method, or the like can be used. It is preferable that the first semiconductor film 606a is formed to have a thickness of 10 nm or more and 50 nm or less.

The second semiconductor film 606b is an i-type semiconductor film (intrinsic semiconductor film), and is formed using an amorphous silicon film. For the formation of the second semiconductor film 606b, an amorphous silicon film is formed by the plasma CVD method through the use of a semiconductor source gas. As the semiconductor source gas, silane (SiH ₄ ) may be used. Alternatively, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF ₄ , etc. can be used. The second semiconductor film 606b may be formed by an LPCVD method, a vapor deposition method, a sputtering method, or the like. It is preferable that the second semiconductor film 606b is formed to have a thickness of 200 nm or more and 1000 nm or less.

The third semiconductor film 606c is an n-type semiconductor film, and is formed using an amorphous silicon film containing an impurity element that adds n-type conductivity. The third semiconductor film 606c is formed by a plasma CVD method using a semiconductor source gas containing an impurity element belonging to Group 15 (eg, phosphorus (P)). As the semiconductor source gas, silane (SiH ₄ ) may be used. Alternatively, Si ₂ H ₆ , SiH ₂ Cl ₂ , SiHCl ₃ , SiCl ₄ , SiF ₄ , etc. can be used. As a further alternative, an amorphous silicon film containing no impurity element may be formed, and then the impurity element may be implanted into the amorphous silicon film by a diffusion method or an ion implantation method. In order to diffuse the impurity element, heating may be performed after the impurity element is implanted by an ion implantation method or the like. In this case, as a method of forming an amorphous silicon film, an LPCVD method, a vapor deposition method, a sputtering method, or the like can be used. It is preferable that the third semiconductor film 606c is formed to have a thickness of 20 nm or more and 200 nm or less.

The first semiconductor film 606a, the second semiconductor film 606b, and the third semiconductor film 606c do not necessarily need to be formed using an amorphous semiconductor, and a polycrystalline semiconductor or a microcrystalline semiconductor (semi-amorphous semiconductor: SAS) It can be formed using

The mobility of holes created by the photoelectric effect is lower than that of electrons. Therefore, the pin-type photodiode has better properties when the surface on the p-type semiconductor film side is used as the light receiving plane. Here, an example in which light received by the photodiode 602 from the surface of the substrate 601 on which the pin-type photodiode is formed is converted into electrical signals will be described. Moreover, light from a semiconductor film having a conduction type opposite to that of the semiconductor film on the light receiving plane is disturbing light; Therefore, the electrode layer is preferably formed using a light blocking conductive layer. Alternatively, the surface on the side of the n-type semiconductor film can be used as the light receiving plane.

The transistor 640 is an oxide insulating layer 621, which is an insulating layer in contact with the oxide semiconductor layer 623, and includes an oxide insulating layer containing one or more metal elements selected from constituent elements of the oxide semiconductor layer 623. . Accordingly, charge trapping at the interface between the oxide semiconductor layer 623 and the oxide insulating layer 621 may be reduced, and electrical characteristics of the transistor 640 may be stabilized. In addition, the transistor 640, as the gate insulating layer 620, contains nitrogen and includes a silicon film having a thick thickness (eg, 325 nm or more and 550 nm or less). Accordingly, electrostatic discharge damage to the transistor 640 can be prevented. A semiconductor device having high reliability including the transistor 640 may be provided with a high yield.

Using an insulating material, the insulating layer 631, the insulating layer 632, the interlayer insulating layer 633 and the interlayer insulating layer 634, depending on the material, sputtering method, plasma CVD method, spin coating, dipping, spray coating , A droplet ejection method (such as an inkjet method), screen printing, offset printing, and the like.

It should be noted that, as the insulating layer 631 in contact with the oxide semiconductor layer 623, it is preferable to use an oxide insulating layer containing one or more metal elements selected from constituent elements of the oxide semiconductor layer 623. As the insulating layer 632 over the insulating layer 631 in contact with the insulating layer 631, it is preferable to provide a silicon film containing nitrogen.

In order to reduce the surface roughness, an insulating layer serving as a planarizing insulating layer is preferably used as each of the interlayer insulating layers 633 and 634. For the interlayer insulating layers 633 and 634, an organic insulating material having heat resistance such as polyimide, acrylic resin, benzocyclobutene-based resin, polyamide, or epoxy resin may be used. In addition to these organic insulating materials, a single layer or laminate of a low dielectric constant material (low k material), a siloxane-based resin, phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), or the like can be used.

By detection of the light 622 entering the photodiode 602, information on the object to be detected can be read. It should be noted that a light source such as a backlight can be used when reading information on an object to be detected.

The configurations, methods, and the like described in this embodiment may be appropriately combined with any of the configurations, methods, and the like described in other embodiments.

(Example 4)

The semiconductor device according to the present invention disclosed in the present specification can be applied to various electronic devices (including entertainment devices). Examples of electronic devices include television devices (also referred to as TV or television receivers), monitors for computers, etc., cameras such as digital cameras and digital video cameras, digital photo frames, cellular phones, portable Game consoles, portable information terminals, audio playback devices, entertainment devices (such as pinballs and slot machines), game consoles, and the like. Specific examples of these electronic devices are shown in FIG. 8.

8A shows a table 9000 having a display unit. In the table 9000, the display unit 9003 is integrated into the housing 9001, and an image may be displayed on the display unit 9003. It should be noted that the housing 9001 is supported on the four legs 9002. Additionally, the housing 9001 has a power cord 9005 for supplying power.

The semiconductor device described in any of the above embodiments may be used for the display unit 9003 so that the electronic device has high reliability.

The display unit 9003 has a touch input function. When a user touches the displayed buttons 9004 displayed on the display unit 9003 of the table 9000 using his or her finger, the user may perform an operation of the screen and input of information. Further, when the table can communicate with other household appliances or can control household appliances, the table 9000 can function as a control device for controlling the household appliances by operation on the screen. For example, through the use of the semiconductor device having the image sensor function described in the third embodiment, the display unit 9003 may have a touch input function.

Further, the screen of the display unit 9003 may be placed vertically on the floor through a hinge provided on the housing 9001; Thus, the table 9000 can also be used as a television device. When a television device with a large screen is installed in a small room, the open space is reduced; However, when the display unit is integrated into the table, the space in the room can be used efficiently.

8B shows a television device 9100. In the television device 9100, the display portion 9103 is integrated within the housing 9101, and an image can be displayed on the display portion 9103. It should be noted that the housing 9101 is supported here by a stand 9105.

The television device 9100 may be operated by an operation switch of the housing 9101 or a separate remote control 9110. Channels and volumes can be controlled through operation keys 9191 of the remote control 9110, and images displayed on the display 9103 can be controlled. In addition, the remote control 9110 may include a display unit 9307 for displaying data output from the remote control 9110.

The television device 9100 shown in Fig. 8B includes a receiver, a modem, and the like. Through the receiver, the television device 9100 may receive a general television broadcast. Moreover, when the television device 9100 is connected to the communication network with a wired or wireless connection via a modem, one-way (from the transmitter to the receiver) or two-way (between the transmitter and receiver, between receivers, etc.) data communication can be performed. .

The semiconductor device described in any of the above embodiments can be used for the display units 9103 and 9107, so that the television device and the remote control can have high reliability.

8C shows a computer including a main body 9201, a housing 9202, a display 9203, a keyboard 9204, an external connection port 9205, a pointing device 9306, and the like.

The semiconductor device described in any one of the above embodiments can be used for the display unit 9203, so that the computer can have high reliability.

9A and 9B illustrate a folder-type tablet terminal. The tablet terminal is opened in A of FIG. 9. The tablet terminal includes a housing 9630, a display unit 9631a, a display unit 9631b, a display mode switch 9034, a power switch 9035, a power saving switch 9036, a latch 9033, and an operation switch 9038. ).

The semiconductor device described in any one of the above embodiments can be used for the display unit 9631a and the display unit 9631b, so that the tablet terminal can have high reliability.

A portion of the display unit 9631a may be the touch panel area 9632a, and data may be input when the displayed operation key 9638 is touched. A structure in which a half area of the display unit 9631a only has a display function and the other half area also has a function of a touch panel is illustrated as an example, but the display unit 9631a is not limited to this structure. The entire area of the display unit 9631a may have a touch panel function. For example, the display unit 9631a may display keyboard buttons on the entire area to be a touch panel, and the display unit 9631b may be used as a display screen.

As in the display unit 9631a, a portion of the display unit 9631b may become the touch panel area 9632b. When the keyboard display switching button 9639 displayed on the touch panel is touched with a finger, a stylus, or the like, the keyboard may be displayed on the display unit 9631b.

The touch input may be performed simultaneously in the touch panel area 9632a and the touch panel area 9632b.

The display mode switch 9034 may, for example, switch the display between portrait mode, landscape mode, etc., and between a monochrome display and a color display. The power saving switch 9036 may control the display luminance according to the amount of external light when using the tablet terminal detected by the optical sensor integrated in the tablet terminal. In addition to the light sensor, other detection devices including sensors for detecting tilt, such as gyroscopes or acceleration sensors, may be incorporated into the tablet terminal.

9A shows an example in which the display unit 9631a and the display unit 9631b have the same display area; However, without limitation thereto, one of the display units may be different from the other display units in size and display quality. For example, one display panel may be a display having a higher resolution than another display panel.

The tablet terminal is closed in B of FIG. 9. The tablet terminal includes a housing 9630, a solar cell 9633, and a charge-discharge control circuit 9634. In FIG. 9B, a structure including a battery 9635 and a DCDC converter 9636 is shown as an example of the charge-discharge control circuit 9632.

Since the tablet terminal is a foldable, the housing 9630 can be closed when the tablet terminal is not in use. As a result, the display portion 9631a and the display portion 9631b can be protected; Therefore, a tablet terminal having excellent durability and excellent reliability can be provided in terms of long-term use.

In addition, the tablet terminal shown in A and B of FIG. 9 has a function of displaying various types of data (eg, still images, moving pictures, and text images), and displaying a calendar, date, time, etc. on the display unit. It may have a function, a touch-input function of operating or editing data displayed on the display unit through a touch input, a function of controlling processing by various types of software (programs), and the like.

The solar cell 9633 provided on the surface of the tablet terminal may supply power to a touch panel, a display unit, a video signal processing unit, and the like. It should be noted that the solar cell 9633 can be provided on one or both of the surfaces of the housing 9630 so that the battery 963 can be efficiently charged. The use of a lithium ion battery as the battery 9635 is advantageous in terms of size reduction and the like.

The structure and operation of the charge-discharge control circuit 9634 shown in FIG. 9B will be described with reference to the block diagram of FIG. 9C. A solar cell 9633, a battery 9635, a DCDC converter 9636, a converter 9637, switches SW1 to SW3, and a display unit 9631 are shown in C of FIG. 9, and a battery 9635, The DCDC converter 9636, the converter 9637, and the switches SW1 to SW3 correspond to the charge-discharge control circuit 9634 shown in FIG. 9B.

First, an operation example in which power is generated by the solar cell 9633 using external light will be described. The voltage of the power generated by the solar cell 9633 is stepped up or down by the DCDC converter 9636 so that the power has a voltage for charging the battery 9635. Thereafter, when the power from the solar cell 9633 is used for the operation of the display unit 9631, the switch SW1 is turned on, and the voltage of the power becomes a voltage required for the display unit 9631, so that the converter 9637 ) Increases or decreases step by step. In addition, when the display on the display unit 9631 is not performed, the switch SW1 is turned off and the switch SW2 is turned on so that the battery 9635 can be charged.

The solar cell 9633 is described as an example of power generation means; Without limitation to this, it should be noted that the battery 963 can be charged using other power generation means such as a piezoelectric element or a thermoelectric conversion element (Peltier element). For example, a non-contact power transmission module for wirelessly transmitting or receiving power to charge the battery 9635 or a combination of the solar cell 9633 and other charging means may be used.

The configurations, methods, and the like described in this embodiment may be appropriately combined with any of the configurations, methods, and the like described in other embodiments.

[Example 1]

In this example, results of evaluating the quality of silicon nitride films formed by the plasma CVD method will be described. In particular, the results of ESR measurements of a silicon nitride film formed using a mixed gas of silane and nitrogen as a feed gas and a silicon nitride film formed using a mixed gas of silane, nitrogen and ammonia as a feed gas are shown herein.

A method of preparing the samples used for ESR measurements in this example is described below.

Samples 1 to 5, which are 300 nm thick silicon nitride films formed on quartz substrates, were used for ESR measurements. Each silicon nitride film was formed as follows. The quartz substrate was placed in the film forming chamber of the plasma CVD apparatus, the pressure in the film forming chamber was controlled to be 100 Pa, and a power of 2000 W was supplied from a 27.12 MHz high-frequency power source. The substrate temperature was 350°C. It should be noted that the plasma CVD apparatus is a parallel plate type with an electrode area of 6000 cm 2. Sample 1 was prepared using a mixed gas of silane and nitrogen as a feed gas. Samples 2 to 5 were prepared using a mixed gas of silane, nitrogen, and ammonia as feed gas. Film formation conditions for these samples are shown in Table 1 below.

The prepared samples (1 to 5) were subjected to ESR measurements. ESR measurements were performed under the following conditions. The measurement temperature was -170°C, the 9.2 GHz high frequency power (microwave power) was 1 mW, the direction of the magnetic field was parallel to the surface of the silicon nitride film of each of the samples (1 to 5), and the center of Nc contained in the silicon nitride film The lower limit of detection of the spin density corresponding to the signal appearing at g=2.003 that can be attributed to was 8.1×10 ¹⁵ spins/cm 3.

12A shows the results of ESR measurements. From A of FIG. 12, it was confirmed that Sample 1 prepared through a supply gas containing no ammonia had ^{a spin density of 2.7×10 17} spins/cm 3 that may be attributed to the Nc center, and was a silicon nitride film containing a large number of defects. I can. On the other hand, all of the samples (2 to 5) prepared through the supply gas containing ammonia, respectively, are 5.1×10 ¹⁶ spins/cm 3 and 5.2×10 ¹⁶ spins/cm 3, each of which can be attributed to the center of Nc independently of the flow rate of ammonia. , 6.0×10 ¹⁶ spins/cm 3, and 5.5×10 ¹⁶ spins/cm 3, it was confirmed that the silicon nitride films had a small number of defects.

12B shows first order differential curves obtained by ESR measurements. As shown in Fig. 12B, a high intensity signal, which may be due to defects (Nc center) in the film, was detected at a g-factor of 2.003 in Sample 1. On the other hand, signals of low intensity were observed from samples 2 to 5 at a g-factor of 2.003.

The above results imply that a silicon nitride film containing a small number of defects can be formed using a mixed gas of silane, nitrogen and ammonia as a supply gas at the time of forming the silicon nitride film by the plasma CVD method. This means that a silicon nitride film can be used as a gate insulating layer having a good withstand voltage, and a transistor including such a gate insulating layer can have good resistance to ESD.

[Example 2]

In this example, properties of silicon nitride films formed by the plasma CVD method, as barrier films, are evaluated. 13 shows the evaluation results. As an evaluation method, thermal desorption spectroscopy (TDS) was used.

In this example, samples 6 to 8, which are silicon nitride films formed on crystal substrates by the plasma CVD method, were used for evaluation. How to prepare the samples is described below.

Each silicon nitride film was formed as follows. The quartz substrate was placed in the film forming chamber of the plasma CVD apparatus, the pressure in the film forming chamber was controlled to be 100 Pa, and a power of 2000 W was supplied from a 27.12 MHz high-frequency power source. The substrate temperature was 350°C. It should be noted that the plasma CVD apparatus is a parallel plate type with an electrode area of 6000 cm 2.

As Sample 6, a 300 nm-thick silicon nitride film used a mixed gas of silane, nitrogen, and ammonia (SiH ₄ flow rate: 200 sccm, N ₂ flow rate: 2000 sccm, NH ₃ flow rate: 2000 sccm) as a supply gas. Was formed.

As Sample 7, the first silicon nitride film having a thickness of 275 nm was supplied with a mixed gas of silane, nitrogen, and ammonia ( _{flow rate of SiH 4} : 200 sccm, _{flow rate of N 2} : 2000 sccm, _{flow rate of NH 3} : 2000 sccm). After that, a second silicon nitride film having a thickness of 50 nm was formed using a mixed gas of silane and nitrogen (SiH ₄ flow rate: 200 sccm, N ₂ flow rate: 5000 sccm) in the same film formation chamber. .

As Sample 8, the first silicon nitride film having a thickness of 275 nm used a mixed gas of silane, nitrogen, and ammonia ( _{flow rate of SiH 4} : 200 sccm, _{flow rate of N 2} : 2000 sccm, flow rate of NH ₃ : 2000 sccm) as a feed gas. After that, a second silicon nitride film having a thickness of 50 nm was formed at a low ammonia flow rate (SiH ₄ flow rate: 200 sccm, N ₂ flow rate: 2000 sccm, NH ₃ flow rate: 100 sccm) in the same film formation chamber. .

13 shows the results of TDS measurements of samples at m/z=2 (H _{2 ).} 13A shows the results of TDS measurements of samples 6 and 7 prepared at m/z=2 (H ₂ ) in this example, and FIG. 13B shows the results of m/z=2 (H ₂ ). Results of the TDS measurements of samples 6 and 8 are shown.

13, it can be seen that hydrogen is desorbed from Sample 6, which is a single-layer silicon nitride film having a high hydrogen concentration by heat treatment. On the other hand, hydrogen desorption from samples 7 and 8 in which a silicon nitride film having a low hydrogen concentration is stacked as an upper layer, respectively, occurs at about 450°C where hydrogen desorption occurs from sample 6, and even when heat treatment is further continued. Not doing so, it can be confirmed that hydrogen desorption is significantly suppressed.

Accordingly, it can be confirmed that the hydrogen blocking effect (barrier effect) is achieved by providing the silicon nitride film having a low hydrogen concentration as an upper layer in contact with the silicon nitride film having a high hydrogen concentration.

As described in Example 1, the silicon nitride film formed by the plasma CVD method using silane, nitrogen, and ammonia as supply gases contains a small number of defects and has a high withstand voltage. Therefore, a structure in which a silicon nitride film having a low hydrogen concentration is stacked on a silicon nitride film containing a small number of defects can reduce desorption of hydrogen, which can act as a donor in the oxide semiconductor layer, while maintaining high resistance to ESD. Therefore, this structure is suitable as a gate insulating layer of a transistor.

This application is based on Japanese Patent Application No. 2012-108899 filed with the Japan Intellectual Property Office on May 10, 2012, the entire contents of which are incorporated herein by reference.

300: transistor 310: transistor
330: transistor
340: transistor 400: substrate
402: gate electrode layer 404: gate insulating layer
404a: gate insulating layer 404b: gate insulating layer
404c: gate insulating layer 406: oxide insulating layer
408: oxide semiconductor layer 408a: oxide semiconductor layer
408b: oxide semiconductor layer 410a: source electrode layer
410b: drain electrode layer 412: oxide insulating layer
414: protective insulating layer 414a: protective insulating layer
414b: protective insulating layer 500: substrate
502: gate insulating layer 504: interlayer insulating layer
505: color filter layer 506: insulating layer
507: compartment 510: transistor
511a: gate electrode layer 511b: gate electrode layer
512: oxide insulating layer 513a: conductive layer
513b: conductive layer 514: oxide semiconductor layer
520: capacitor 521a: conducting layer
521b: conductive layer 522: oxide insulating layer
523: conductive layer 524: insulating layer
525: insulating layer 526: oxide semiconductor layer
530: intersection of wiring layers 533: conductive layer
540: light emitting element 541: electrode layer
542: electroluminescent layer 543: electrode layer
601: substrate 602: photodiode
606a: semiconductor film 606b: semiconductor film
606c: semiconductor film 608: adhesive layer
613: substrate 620: gate insulating layer
621: oxide insulating layer 622: optical
623: oxide semiconductor layer 631: insulating layer
632: insulating layer 633: interlayer insulating layer
634: interlayer insulating layer 640: transistor
641a: electrode layer 641b: electrode layer
642: electrode layer 643: conductive layer
645: conductive layer 656: transistor
658: photodiode reset signal line 659: gate signal line
671: photosensor output signal line 672: photosensor reference signal line
4001: substrate 4002: pixel portion
4003: signal line driving circuit 4004: scan line driving circuit
4005: sealing agent 4006: substrate
4008: liquid crystal layer 4010: transistor
4011: transistor 4013: liquid crystal element
4015: connection terminal electrode 4016: terminal electrode
4018: FPC 4019: anisotropic conductive layer
4020a: gate insulating layer 4020b: oxide insulating layer
4021: insulating layer 4030: oxide insulating layer
4031: electrode layer 4032: protective insulating layer
4033: insulating layer 4034: electrode layer
4035: spacer 4038: insulating layer
4510: compartment 4511: electroluminescent layer
4513: light-emitting element 4514: filler
9000: table 9001: housing
9002: leg portion 9003: display portion
9004: display button 9005: power cord
9033: clasp 9034: switch
9035: power switch 9036: power saving switch
9038: operation switch 9100: television device
9101: housing 9103: display unit
9105: stand 9107: display unit
9109: operation key 9110: remote control
9201: main body 9202: housing
9203: display unit 9204: keyboard
9205: external connection part 9206: pointing device
9630: housing 9631: display
9631a: display unit 9631b: display unit
9632a: area 9632b: area
9633: solar cell 9634: charge/discharge control circuit
9635: battery 9636: DCDC converter
9637: converter 9638: operation key
9639: button

Claims (9)

In a semiconductor device:
A gate electrode and an oxide semiconductor layer interposed between the gate insulating layer;
The gate insulating layer and the insulating layer in contact with the oxide semiconductor layer and interposed between the oxide semiconductor layer;
A protective insulating layer over the insulating layer and in contact with the insulating layer;
A source electrode and a drain electrode between the oxide semiconductor layer and the insulating layer; And
A wiring electrically connected to the drain electrode through the opening of the insulating layer,
The insulating layer includes a metal element selected from constituent elements of the oxide semiconductor layer,
The gate insulating layer is in contact with the bottom surface of the oxide semiconductor layer,
The insulating layer is in contact with the upper surface of the oxide semiconductor layer,
The gate insulating layer includes a first gate insulating layer and a second gate insulating layer over the first gate insulating layer,
Each of the first gate insulating layer and the second gate insulating layer includes a silicon film containing nitrogen,
The protective insulating layer includes a silicon film containing nitrogen,
The thickness of the protective insulating layer is thicker than the thickness of the insulating layer,
The semiconductor device, wherein the hydrogen concentration of the second gate insulating layer is lower than the hydrogen concentration of the first gate insulating layer. In a semiconductor device:
A gate electrode and an oxide semiconductor layer interposed between the gate insulating layer;
The gate insulating layer and the insulating layer in contact with the oxide semiconductor layer and interposed between the oxide semiconductor layer;
A protective insulating layer over the insulating layer and in contact with the insulating layer;
A source electrode and a drain electrode between the oxide semiconductor layer and the insulating layer; And
A wiring electrically connected to the drain electrode through the opening of the insulating layer,
The insulating layer includes a metal element selected from constituent elements of the oxide semiconductor layer,
The gate insulating layer is in contact with the bottom surface of the oxide semiconductor layer,
The insulating layer is in contact with the upper surface of the oxide semiconductor layer,
The gate insulating layer includes a first gate insulating layer and a second gate insulating layer over the first gate insulating layer,
The oxide semiconductor layer includes a first oxide semiconductor layer in contact with the gate insulating layer and a second oxide semiconductor layer in contact with the insulating layer,
Each of the first gate insulating layer and the second gate insulating layer includes a silicon film containing nitrogen,
The protective insulating layer includes a silicon film containing nitrogen,
The thickness of the protective insulating layer is thicker than the thickness of the insulating layer,
The semiconductor device, wherein the hydrogen concentration of the second gate insulating layer is lower than the hydrogen concentration of the first gate insulating layer. The method according to claim 1 or 2,
The semiconductor device further comprising an oxide insulating layer between the second gate insulating layer and the oxide semiconductor layer. The method according to claim 1 or 2,
The semiconductor device, wherein the oxide semiconductor layer comprises indium, gallium, and zinc. The method according to claim 1 or 2,
The semiconductor device, wherein the insulating layer contains oxygen. The method according to claim 1 or 2,
The semiconductor device, wherein the gate electrode comprises copper. A display device comprising the semiconductor device according to claim 1 or 2. The method of claim 2,
The semiconductor device, wherein the content of indium in the first oxide semiconductor layer is higher than the content of indium in the second oxide semiconductor layer. The method of claim 2,
The semiconductor device, wherein the content of indium in the second oxide semiconductor layer is lower than the content of gallium in the second oxide semiconductor layer.

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