[go: up one dir, main page]

CN113267118B - A kind of semiconductor conductive film thickness on-line test structure and test method - Google Patents

A kind of semiconductor conductive film thickness on-line test structure and test method Download PDF

Info

Publication number
CN113267118B
CN113267118B CN202110695599.5A CN202110695599A CN113267118B CN 113267118 B CN113267118 B CN 113267118B CN 202110695599 A CN202110695599 A CN 202110695599A CN 113267118 B CN113267118 B CN 113267118B
Authority
CN
China
Prior art keywords
semiconductor
resistance
strip
resistor
thin layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110695599.5A
Other languages
Chinese (zh)
Other versions
CN113267118A (en
Inventor
周再发
宋玉洁
黄庆安
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Southeast University
Original Assignee
Southeast University
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Southeast University filed Critical Southeast University
Priority to CN202110695599.5A priority Critical patent/CN113267118B/en
Publication of CN113267118A publication Critical patent/CN113267118A/en
Application granted granted Critical
Publication of CN113267118B publication Critical patent/CN113267118B/en
Priority to PCT/CN2022/099950 priority patent/WO2022268039A1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • GPHYSICS
    • G01MEASURING; TESTING
    • G01BMEASURING LENGTH, THICKNESS OR SIMILAR LINEAR DIMENSIONS; MEASURING ANGLES; MEASURING AREAS; MEASURING IRREGULARITIES OF SURFACES OR CONTOURS
    • G01B7/00Measuring arrangements characterised by the use of electric or magnetic techniques
    • G01B7/02Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width or thickness
    • G01B7/06Measuring arrangements characterised by the use of electric or magnetic techniques for measuring length, width or thickness for measuring thickness
    • GPHYSICS
    • G01MEASURING; TESTING
    • G01RMEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R27/00Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
    • G01R27/02Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
    • G01R27/14Measuring resistance by measuring current or voltage obtained from a reference source
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02EREDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00Energy generation through renewable energy sources
    • Y02E10/50Photovoltaic [PV] energy

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)

Abstract

The invention discloses an on-line testing structure for the thickness of a semiconductor conductive film, which comprises a four-probe resistance testing bridge structure and a continuous ladder structure, wherein the structure utilizes a plurality of steps to average random errors in the manufacturing process of the steps, and utilizes the plurality of steps to increase the numerical value of resistance change, thereby facilitating measurement. The invention also discloses an on-line testing method for the thickness of the semiconductor conductive film, which is simple, has low requirement on testing equipment, stable testing process and testing parameter values, synchronous processing process and micro-electromechanical device, has no special processing requirement, completely meets the requirement of on-line testing, and is only limited by a simple mathematical formula.

Description

一种半导体导电薄膜厚度在线测试结构及其测试方法A kind of semiconductor conductive film thickness on-line test structure and test method

技术领域technical field

本发明涉及半导体导电薄膜在线测量领域,特别是涉及一种半导体导电薄膜厚度在线测试结构及其测试方法。The invention relates to the field of on-line measurement of semiconductor conductive films, in particular to a structure for on-line testing of the thickness of semiconductor conductive films and a testing method thereof.

背景技术Background technique

微机电薄膜器件的薄膜厚度是影响器件性能的重要参数。通过在线测量薄膜的厚度,可以获得器件的尺寸,控制器件的精度。半导体是表面微加工过程中所用到的重要材料,加工的基本过程是:先在硅片上淀积一层材料,称为牺牲层。然后光刻定义图形层,接下来在牺牲层上面用化学气相淀积等方法制作结构层薄膜。最后刻蚀去除牺牲层,使微型部件的可动部分与牺牲层分离,形成半导体薄膜结构。牺牲层的材料通常为介质材料,结构层为半导体材料。微机电产品的制造厂商希望能够在线监测半导体导电薄膜的厚度,实时反映制造过程中的工艺误差。因此,不离开加工环境并采用便捷设备对微机电产品进行的在线测试成为控制工艺的必要手段。在线测试结构通常采用电学激励和电学测量的方法,通过电学量数值以及针对性的计算方法得到材料的几何参数。The film thickness of MEMS thin-film devices is an important parameter that affects device performance. By measuring the thickness of the thin film online, the size of the device can be obtained and the precision of the device can be controlled. Semiconductor is an important material used in the surface micromachining process. The basic process of processing is: first deposit a layer of material on the silicon wafer, which is called a sacrificial layer. Then, the pattern layer is defined by photolithography, and then the structure layer film is formed on the sacrificial layer by chemical vapor deposition and other methods. Finally, the sacrificial layer is removed by etching, so that the movable part of the micro component is separated from the sacrificial layer to form a semiconductor thin film structure. The material of the sacrificial layer is usually a dielectric material, and the structural layer is a semiconductor material. Manufacturers of MEMS products hope to be able to monitor the thickness of semiconductor conductive films online and reflect process errors in the manufacturing process in real time. Therefore, online testing of MEMS products without leaving the processing environment and using convenient equipment has become a necessary means of controlling the process. The online test structure usually adopts the method of electrical excitation and electrical measurement, and obtains the geometrical parameters of the material through the electrical quantity value and the targeted calculation method.

发明内容SUMMARY OF THE INVENTION

有鉴于此,本发明的目的在于提供一种半导体导电薄膜厚度在线测试结构及其测试方法,用以在不离开加工环境的情况下,并采用便捷设备对半导体导电薄膜厚度进行在线测量。In view of this, the purpose of the present invention is to provide an on-line testing structure and method for measuring the thickness of a semiconductor conductive thin film, which can be used for on-line measurement of the thickness of a semiconductor conductive thin film by using convenient equipment without leaving the processing environment.

为了达到上述的目的,本发明通过以下技术方案来实现:In order to achieve the above-mentioned purpose, the present invention realizes through the following technical solutions:

一种半导体导电薄膜厚度在线测试结构,包括圆形半导体薄层和第一至第四接触电极,所述四个接触电极均匀的设置在所述圆形半导体薄层的周侧并且与所述圆形半导体薄层电连接,所述四个接触电极与所述圆形半导体薄层形成的张开角度为α;还包括:四探针电阻测试桥结构,所述四探针电阻测试桥结构设置在介质层的表面,所述介质层的表面有一部分被蚀刻成多个相互平行的且相同的凹槽,所述凹槽之间形成台阶,所述台阶具有相同的长度,所述多个凹槽以及相应的台阶共同构成连续阶梯结构,所述凹槽的两个侧壁与所述介质层表面存在相同的夹角;所述四探针电阻测试桥结构包括第一四探针半导体电阻桥和第二四探针半导体电阻桥,其中,An on-line test structure for the thickness of a semiconductor conductive thin film, comprising a circular semiconductor thin layer and first to fourth contact electrodes, the four contact electrodes are uniformly arranged on the peripheral side of the circular semiconductor thin layer and are connected with the circular semiconductor thin layer. The four contact electrodes are electrically connected with the circular semiconductor thin layer, and the opening angle formed by the four contact electrodes and the circular semiconductor thin layer is α; it also includes: a four-probe resistance test bridge structure, and the four-probe resistance test bridge structure is provided with On the surface of the dielectric layer, a part of the surface of the dielectric layer is etched into a plurality of mutually parallel and identical grooves, and steps are formed between the grooves, the steps have the same length, and the plurality of grooves are formed. The groove and the corresponding steps together form a continuous ladder structure, and the two sidewalls of the groove and the surface of the dielectric layer have the same included angle; the four-probe resistance test bridge structure includes a first four-probe semiconductor resistance bridge and a second four-probe semiconductor resistor bridge, where,

所述第一四探针半导体电阻桥包括第一半导体电阻条和四个金属电极,其中,在所述第一半导体电阻条的两端处并且每一侧处均电连接一个金属电极,所述第一半导体电阻条的中间部分爬越所述连续阶梯结构,所述第一半导体电阻条的一端与所述圆形半导体薄层连接形成一体结构,另外一端连接所述第二四探针半导体电阻桥;The first four-probe semiconductor resistance bridge includes a first semiconductor resistance strip and four metal electrodes, wherein one metal electrode is electrically connected at both ends and at each side of the first semiconductor resistance strip, the The middle part of the first semiconductor resistance strip climbs over the continuous ladder structure, one end of the first semiconductor resistance strip is connected with the circular semiconductor thin layer to form an integrated structure, and the other end is connected with the second four-probe semiconductor resistance bridge;

所述第二四探针半导体电阻桥包括第二半导体电阻条和两个金属电极,其中,所述第二半导体电阻条设置在所述第一半导体电阻条的另外一端并且与所述第一半导体电阻条连接,所述第二半导体电阻条与所述第一半导体电阻条共用两个金属电极,所述第二半导体电阻条设置在平坦的介质层表面上,所述第二半导体电阻条与所述第一半导体电阻条具有相同的宽度。The second four-probe semiconductor resistance bridge includes a second semiconductor resistance strip and two metal electrodes, wherein the second semiconductor resistance strip is arranged at the other end of the first semiconductor resistance strip and is connected with the first semiconductor resistance strip. Resistor bars are connected, the second semiconductor resistor bars share two metal electrodes with the first semiconductor resistor bars, the second semiconductor resistor bars are arranged on the surface of the flat dielectric layer, and the second semiconductor resistor bars are connected to the first semiconductor resistor bars. The first semiconductor resistance strips have the same width.

进一步的,所述金属电极设置锚区上,所述锚区为将所述介质层的表面进行蚀刻形成。Further, the metal electrode is disposed on an anchor region, and the anchor region is formed by etching the surface of the dielectric layer.

进一步的,所述介质层设置在绝缘衬底之上。Further, the dielectric layer is disposed on the insulating substrate.

一种半导体导电薄膜厚度在线测试方法,包括如下步骤:An on-line test method for the thickness of a semiconductor conductive film, comprising the following steps:

步骤S1、通过将圆形半导体薄层到简单结构的映射,再结合方块电阻的定义,求出所述圆形半导体薄层的方块电阻RsqStep S1, by mapping the circular semiconductor thin layer to a simple structure, combined with the definition of sheet resistance, obtain the sheet resistance R sq of the circular semiconductor thin layer;

步骤S2、对所述第一半导体电阻条同一侧的两个金属电极施加恒定电流,再测量另外一侧的两个金属电极之间的电压,电压与电流的比值即为电阻R1Step S2, applying a constant current to the two metal electrodes on the same side of the first semiconductor resistance strip, and then measuring the voltage between the two metal electrodes on the other side, the ratio of the voltage to the current is the resistance R 1 ;

步骤S3、对所述第二半导体电阻条同一侧的两个金属电极施加恒定电流,再测量另外一侧的两个金属电极之间的电压,电压与电流的比值即为电阻RAStep S3, applying a constant current to the two metal electrodes on the same side of the second semiconductor resistance strip, and then measuring the voltage between the two metal electrodes on the other side, and the ratio of the voltage to the current is the resistance RA ;

步骤S4、根据电阻R1,方块电阻Rsq与所述第二半导体电阻条的几何尺寸关系,根据所述第一半导体电阻条的厚度与所述台阶的几何尺寸关系,以及根据电阻R1,方块电阻Rsq与所述第一半导体电阻条的几何尺寸关系,建立公式组(1),表达式为:Step S4, according to the resistance R 1 , the relationship between the sheet resistance R sq and the geometric dimension of the second semiconductor resistance strip, according to the relationship between the thickness of the first semiconductor resistance strip and the geometric dimension of the step, and according to the resistance R 1 , The relationship between the sheet resistance R sq and the geometric size of the first semiconductor resistance strip is established by formula group (1), and the expression is:

Figure GDA0003539871750000021
Figure GDA0003539871750000021

公式组(1)中,W表示所述第二半导体电阻条的宽度,Rsq表示方块电阻,R1表示第一半导体电阻条的电阻,L1表示第二半导体电阻条的有效长度,RA表示第二半导体电阻条的电阻,S1表示凹槽顶面的长度,S2表示台阶长度的一半,S3表示凹槽侧壁的长度,β表示凹槽侧壁与凹槽底面的夹角,t1表示第一半导体电阻条的厚度,x为引入的一个中间变量,没有具体的物理意义,只是为了使公式(1)显得简洁明了,γ表示为拐角电阻的修正因子,n表示为台阶的数量;In formula group (1), W represents the width of the second semiconductor resistance strip, R sq represents the sheet resistance, R 1 represents the resistance of the first semiconductor resistance strip, L 1 represents the effective length of the second semiconductor resistance strip, R A Represents the resistance of the second semiconductor resistor strip, S 1 represents the length of the top surface of the groove, S 2 represents half the length of the step, S 3 represents the length of the side wall of the groove, β represents the angle between the side wall of the groove and the bottom surface of the groove , t 1 represents the thickness of the first semiconductor resistance strip, x is an intermediate variable introduced, which has no specific physical meaning, just to make the formula (1) appear concise and clear, γ represents the correction factor of the corner resistance, and n represents the step quantity;

步骤S5、将步骤S1得到的方块电阻Rsq,步骤S2得到的电阻R1以及步骤S3得到的电阻RA代入所述公式组(1)中,通过将测量得到的:第二半导体电阻条的有效长度L1、凹槽顶面的长度S1、台阶长度的一半S2、凹槽侧壁的长度S3,台阶的数量n,拐角电阻的修正因子γ以及凹槽侧壁与凹槽底面的夹角β代入所述公式组(1)中,得到所述半导体导电薄膜厚度。Step S5: Substitute the sheet resistance R sq obtained in step S1, the resistance R1 obtained in step S2, and the resistance RA obtained in step S3 into the formula group ( 1 ), obtained by measuring: the resistance of the second semiconductor resistance strip. Effective length L 1 , groove top length S 1 , half step length S 2 , groove side wall length S 3 , number n of steps, correction factor γ for corner resistance, and groove side walls and groove bottom The included angle β of is substituted into the formula group (1) to obtain the thickness of the semiconductor conductive film.

进一步的,所述步骤S1具体包括:Further, the step S1 specifically includes:

步骤S101、对第一接触电极和第四接触电极之间施加恒定电流,并且测量第一接触电极和第四接触电极之间的电压,电压与电流的比值为电阻RaStep S101, applying a constant current between the first contact electrode and the fourth contact electrode, and measuring the voltage between the first contact electrode and the fourth contact electrode, the ratio of the voltage to the current is the resistance Ra ;

步骤S102、对第一接触电极和第四接触电极之间施加恒定电流,并且测量第二接触电极和第四接触电极之间的电压,电压与电流的比值为电阻RbStep S102, applying a constant current between the first contact electrode and the fourth contact electrode, and measuring the voltage between the second contact electrode and the fourth contact electrode, the ratio of the voltage to the current is the resistance R b ;

步骤S103、根据圆形半导体薄层到简单结构的映射以及方块电阻的定义,建立公式组(2):Step S103 , according to the mapping from the circular semiconductor thin layer to the simple structure and the definition of the sheet resistance, formula group (2) is established:

Figure GDA0003539871750000031
Figure GDA0003539871750000031

公式组(2)中,P、Q、S和T均表示中间量,α为未知数,并且表示四个接触电极与圆形半导体薄层形成的张开角度,i为虚数单位,K[·]表示第一类椭圆积分函数,Rsq表示圆形半导体薄层的方块电阻,ga(α)和gb(α)表示只与张开角度α有关的函数;In formula group (2), P, Q, S and T all represent intermediate quantities, α is an unknown number, and represents the opening angle formed by the four contact electrodes and the circular semiconductor thin layer, i is an imaginary unit, K[ ] represents the first kind of elliptic integral function, R sq represents the sheet resistance of the circular semiconductor thin layer, g a (α) and g b (α) represent functions only related to the opening angle α;

步骤S103、将步骤S101得到的电阻Ra以及步骤S102得到的电阻Rb代入公式组(2)中,求出四个接触电极与圆形半导体薄层形成的张开角度α;Step S103: Substitute the resistance R a obtained in step S101 and the resistance R b obtained in step S102 into the formula group (2), and obtain the opening angle α formed by the four contact electrodes and the circular semiconductor thin layer;

步骤S104、将步骤S103求出的张开角度α代入公式(3)中,得到方块电阻Rsq,公式(3)的表达式为:Step S104: Substitute the opening angle α obtained in step S103 into formula (3) to obtain the sheet resistance R sq , and the expression of formula (3) is:

Figure GDA0003539871750000032
Figure GDA0003539871750000032

公式(3)中,ga(α)表示只与张开角度α有关的函数,i为虚数单位,P、Q、S和T均表示中间量。In formula (3), g a (α) represents a function only related to the opening angle α, i is an imaginary unit, and P, Q, S, and T all represent intermediate quantities.

进一步的,在所述步骤S5中,所述半导体导电薄膜厚度,表达式为:Further, in the step S5, the thickness of the semiconductor conductive film is expressed as:

Figure GDA0003539871750000041
Figure GDA0003539871750000041

本发明的有益效果是:The beneficial effects of the present invention are:

1、本发明提供的测试方法简单,测试设备要求低,测试过程及测试参数值稳定。加工过程与微机电器件同步,没有特殊加工要求,完全符合在线测试的要求。计算方法仅限于简单数学公式。1. The test method provided by the present invention is simple, the test equipment requirements are low, and the test process and test parameter values are stable. The processing process is synchronized with the micro-electromechanical device, there is no special processing requirements, and it fully meets the requirements of online testing. Calculation methods are limited to simple mathematical formulas.

2、本发明通过半导体爬越多个牺牲层台阶,利用多个台阶平均了台阶制造过程中的随机误差;利用多个台阶增加了电阻变化的数值,便于测量。测量采用四探针法,对两个半导体电阻进行测试。最后,结合圆形薄层结构得到的方块电阻,计算得到半导体的厚度。2. In the present invention, the semiconductor climbs over multiple steps of the sacrificial layer, and the random errors in the manufacturing process of the steps are averaged by using the multiple steps; the value of the resistance change is increased by using the multiple steps, which is convenient for measurement. The measurement uses the four-probe method to test two semiconductor resistors. Finally, combined with the sheet resistance obtained from the circular thin-layer structure, the thickness of the semiconductor is calculated.

附图说明Description of drawings

图1为圆形半导体薄层的结构示意图。FIG. 1 is a schematic structural diagram of a circular semiconductor thin layer.

图2为四探针电阻测试桥结构的结构示意图。FIG. 2 is a schematic structural diagram of a four-probe resistance test bridge structure.

图3为单个阶梯结构放大后的剖面图。FIG. 3 is an enlarged cross-sectional view of a single stepped structure.

附图中:In the attached picture:

101-第一接触电极、102-第二接触电极、103-第三接触电极、104-第四接触电极、105-圆形半导体薄层、106-第二半导体电阻条、107-凹槽、108-第一半导体电阻条、109,110,111,112,113以及114均表示锚区、115-金属电极、116-半导体层、117-介质层、118-绝缘衬底。101-first contact electrode, 102-second contact electrode, 103-third contact electrode, 104-fourth contact electrode, 105-round semiconductor thin layer, 106-second semiconductor resistance strip, 107-groove, 108 - The first semiconductor resistance strips, 109, 110, 111, 112, 113 and 114 all represent anchor regions, 115 - metal electrode, 116 - semiconductor layer, 117 - dielectric layer, 118 - insulating substrate.

具体实施方式Detailed ways

为使本发明实施例的目的、技术方案和优点更加清楚,下面将结合本发明实施例中的附图,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有做出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。In order to make the purposes, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments These are some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

实施例1Example 1

参见图1、图2和图3,本实施例提供一种半导体导电薄膜厚度在线测试结构,包括圆形半导体薄层105、第一接触电极101、第二接触电极102、第三接触电极103和第四接触电极104,四个接触电极均匀的设置在圆形半导体薄层105的周侧并且与圆形半导体薄层105电连接,四个接触电极与圆形半导体薄层105形成的张开角度为α;具体的说,圆形半导体薄层105用于测量方块电阻,第一至第四接触电极用于施加电流和测量电压。Referring to FIG. 1 , FIG. 2 and FIG. 3 , this embodiment provides an on-line test structure for the thickness of a semiconductor conductive thin film, including a circular semiconductor thin layer 105 , a first contact electrode 101 , a second contact electrode 102 , a third contact electrode 103 and The fourth contact electrode 104, the four contact electrodes are evenly arranged on the peripheral side of the circular semiconductor thin layer 105 and are electrically connected to the circular semiconductor thin layer 105, and the opening angle formed by the four contact electrodes and the circular semiconductor thin layer 105 is α; specifically, the circular semiconductor thin layer 105 is used to measure sheet resistance, and the first to fourth contact electrodes are used to apply current and measure voltage.

半导体导电薄膜厚度在线测试结构还包括:四探针电阻测试桥结构以及连续阶梯结构,四探针电阻测试桥结构设置在介质层117的表面,介质层117设置在绝缘衬底118之上,介质层117的表面有一部分被蚀刻成n个相互平行的且相同的凹槽107,具体请参见图3,凹槽107之间形成台阶,台阶具有相同的长度,凹槽107的两个侧壁与介质层117表面存在相同的夹角β,n个凹槽107以及相依的台阶共同构成上述连续阶梯结构。The semiconductor conductive thin film thickness on-line test structure also includes: a four-probe resistance test bridge structure and a continuous ladder structure. The four-probe resistance test bridge structure is set on the surface of the dielectric layer 117, the dielectric layer 117 is set on the insulating substrate 118, the dielectric A part of the surface of the layer 117 is etched into n parallel and identical grooves 107. Please refer to FIG. 3 for details. Steps are formed between the grooves 107, and the steps have the same length. The surface of the dielectric layer 117 has the same angle β, and the n grooves 107 and the interdependent steps together form the above-mentioned continuous step structure.

四探针电阻测试桥结构包括第一四探针半导体电阻桥和第二四探针半导体电阻桥。The four-probe resistance test bridge structure includes a first four-probe semiconductor resistance bridge and a second four-probe semiconductor resistance bridge.

具体的说,第一四探针半导体电阻桥和第二四探针半导体电阻桥均包括一个半导体电阻条,以及四个金属电极115,用于进行四探针法的测量。并且第一四探针半导体电阻桥和第二四探针半导体电阻桥共用两个金属电极115,在笛卡尔坐标系中,半导体电阻条和与x轴方向平行。更具体的说,第一四探针半导体电阻桥包括第一半导体电阻条108和四个金属电极115,第一半导体电阻条108的最左端的两侧均电连接一个金属电极115,第一半导体电阻条108的最右端的两侧均电连接一个金属电极115,合计四个金属电极115,第一半导体电阻108条的中间部分爬越连续阶梯结构。Specifically, the first four-point probe semiconductor resistance bridge and the second four-point probe semiconductor resistance bridge each include a semiconductor resistance bar and four metal electrodes 115 for performing four-point probe measurement. In addition, the first four-point probe semiconductor resistance bridge and the second four-point probe semiconductor resistance bridge share two metal electrodes 115 , and in the Cartesian coordinate system, the semiconductor resistance bars and the x-axis direction are parallel. More specifically, the first four-probe semiconductor resistance bridge includes a first semiconductor resistance bar 108 and four metal electrodes 115. Both sides of the leftmost end of the first semiconductor resistance bar 108 are electrically connected to a metal electrode 115. Both sides of the rightmost end of the resistor bar 108 are electrically connected to one metal electrode 115 , totaling four metal electrodes 115 , and the middle part of the first semiconductor resistor bar 108 climbs the continuous ladder structure.

第二四探针半导体电阻桥包括第二半导体电阻条106和两个金属电极115,第二半导体电阻条106设置在第一半导体电阻条108的最右端并且与第一半导体电阻条108连接,并且设置在平坦的介质层117表面上。第二半导体电阻条106的最右端的两侧均设置一个金属电极115,第二半导体电阻条106的最左端使用第一半导体电阻条108最右端的两个金属电极115。更具体的说,第一半导体电阻条108和第二半导体电阻条106沿y轴方向的长度为W,凹槽107的设计尺寸沿y轴方向的长度大于半导体电阻条的W值的3倍,x轴方向的长度为S1,第二半导体电阻条106有效长度为L1The second four-probe semiconductor resistance bridge includes a second semiconductor resistance bar 106 and two metal electrodes 115, the second semiconductor resistance bar 106 is disposed at the rightmost end of the first semiconductor resistance bar 108 and is connected to the first semiconductor resistance bar 108, and It is arranged on the surface of the flat dielectric layer 117 . A metal electrode 115 is provided on both sides of the rightmost end of the second semiconductor resistance bar 106 , and the leftmost end of the second semiconductor resistance bar 106 uses the two metal electrodes 115 at the rightmost end of the first semiconductor resistance bar 108 . More specifically, the length of the first semiconductor resistance strip 108 and the second semiconductor resistance strip 106 along the y-axis direction is W, and the design dimension of the groove 107 along the y-axis direction is greater than 3 times the W value of the semiconductor resistance strip, The length in the x-axis direction is S 1 , and the effective length of the second semiconductor resistance strip 106 is L 1 .

具体的说,本实施例中的金属电极115设置在相应的六个锚区上,六个锚区是通过将介质层117的表面进行蚀刻形成,在本实施中,四探针电阻测试桥结构下侧的3个锚区从从左至右,依次为:锚区109、锚区110、锚区111;四探针电阻测试桥结构下侧的3个锚区从从右至左,依次为:锚区112、锚区113、锚区114。Specifically, the metal electrodes 115 in this embodiment are disposed on the corresponding six anchor regions, and the six anchor regions are formed by etching the surface of the dielectric layer 117. In this embodiment, the four-probe resistance test bridge structure The three anchor areas on the lower side are from left to right: anchor area 109, anchor area 110, anchor area 111; the three anchor areas on the lower side of the four-probe resistance test bridge structure are from right to left, in order: : Anchor area 112, Anchor area 113, Anchor area 114.

参见图3,图3是单个凹槽结构放大后的A-A剖面图,118为绝缘衬底,其上淀积一层介质层117,厚度为t2,刻蚀出凹槽107,其设计尺寸沿x轴方向的长度为S1,由于工艺限制,凹槽107侧壁存在一定角度的倾斜,记为β。淀积一层厚度为t1的半导体层116,在凹槽107处爬越台阶,并形成以凹槽107的垂直中分线为对称轴的对称结构。该对称结构包括以下几部分:在凹槽107两侧未被刻蚀的介质层117表面,分别有一段长为S2的半导体电阻条;在凹槽107底部的衬底表面有一段长为S1-2x的半导体电阻条;两个凹槽107侧壁分别由一段长为S3的半导体电阻条覆盖,并与前面两部分通过四个拐角半导体电阻相连接。由n个图3所示的阶梯结构串联起来,就得到了图2中的连续阶梯结构。Referring to FIG. 3, FIG. 3 is an enlarged AA cross-sectional view of a single groove structure, 118 is an insulating substrate, on which a dielectric layer 117 is deposited with a thickness of t 2 , and the groove 107 is etched, and its design size is along The length in the x-axis direction is S 1 . Due to process limitations, the sidewall of the groove 107 is inclined at a certain angle, which is denoted as β. A layer of semiconductor layer 116 with a thickness of t1 is deposited, climbs over the steps at the groove 107, and forms a symmetrical structure with the vertical midline of the groove 107 as the symmetry axis. The symmetrical structure includes the following parts: on the surfaces of the unetched dielectric layer 117 on both sides of the groove 107, there is a semiconductor resistance strip with a length of S 2 ; 1-2x semiconductor resistance strips ; the side walls of the two grooves 107 are respectively covered by a semiconductor resistance strip with a length of S 3 , and are connected with the front two parts through four corner semiconductor resistances. By connecting n number of ladder structures shown in FIG. 3 in series, the continuous ladder structure in FIG. 2 is obtained.

实施例2Example 2

参见图1和图2,本实施例提供一种半导体导电薄膜厚度在线测试方法,本实施例的方法基于实施例1中的测试结构进行实现,具体包括如下步骤:Referring to FIG. 1 and FIG. 2 , this embodiment provides an on-line test method for the thickness of a semiconductor conductive film. The method of this embodiment is implemented based on the test structure in Embodiment 1, and specifically includes the following steps:

步骤S1、通过将圆形半导体薄层105到简单结构的映射,再结合方块电阻的定义,求出所述圆形半导体薄层105的方块电阻RsqStep S1, by mapping the circular semiconductor thin layer 105 to a simple structure, and then combining with the definition of the sheet resistance, obtain the sheet resistance R sq of the circular semiconductor thin layer 105;

步骤S1,具体采用四探针法进行测量,具体包括:In step S1, the four-probe method is specifically used for measurement, which specifically includes:

步骤S101、对第一接触电极101和第四接触电极104之间施加恒定电流,并且测量第一接触电极101和第四接触电极104之间的电压,电压与电流的比值为电阻RaStep S101, applying a constant current between the first contact electrode 101 and the fourth contact electrode 104, and measuring the voltage between the first contact electrode 101 and the fourth contact electrode 104, the ratio of the voltage to the current is the resistance Ra ;

步骤S102、对第一接触电极101和第四接触电极104之间施加恒定电流,并且测量第二接触电极102和第四接触电极104之间的电压,电压与电流的比值为电阻RbStep S102, applying a constant current between the first contact electrode 101 and the fourth contact electrode 104, and measuring the voltage between the second contact electrode 102 and the fourth contact electrode 104, the ratio of the voltage to the current is the resistance Rb ;

步骤S103、根据圆形半导体薄层105到简单结构的映射以及方块电阻的定义,建立下述公式组:Step S103, according to the mapping from the circular semiconductor thin layer 105 to the simple structure and the definition of the sheet resistance, establish the following formula group:

Figure GDA0003539871750000061
Figure GDA0003539871750000061

公式组中,P、Q、S和T均表示中间量,α为未知数,并且表示四个接触电极与圆形半导体薄层105形成的张开角度,i为虚数单位,K[·]表示第一类椭圆积分函数,Rsq表示圆形半导体薄层105的方块电阻,ga(α)和gb(α)表示只与张开角度α有关的函数;In the formula group, P, Q, S, and T all represent intermediate quantities, α is an unknown number, and represents the opening angle formed by the four contact electrodes and the circular semiconductor thin layer 105, i is an imaginary unit, and K[ ] represents the first A class of elliptic integral functions, R sq represents the sheet resistance of the circular semiconductor thin layer 105, g a (α) and g b (α) represent functions only related to the opening angle α;

步骤S103、将步骤S101得到的电阻Ra以及步骤S102得到的电阻Rb代入上述公式组中,求出四个接触电极101-104与圆形半导体薄层105形成的张开角度α;Step S103: Substitute the resistance R a obtained in step S101 and the resistance R b obtained in step S102 into the above formula group, and obtain the opening angle α formed by the four contact electrodes 101-104 and the circular semiconductor thin layer 105;

步骤S104、将步骤S103求出的张开角度α代入下述公式中,得到方块电阻Rsq,其表达式为:Step S104: Substitute the opening angle α obtained in step S103 into the following formula to obtain the sheet resistance R sq , the expression of which is:

Figure GDA0003539871750000071
Figure GDA0003539871750000071

公式中,ga(α)表示只与张开角度α有关的函数,i为虚数单位,P、Q、S和T均表示中间量。In the formula, ga (α) represents a function only related to the opening angle α, i is an imaginary unit, and P, Q, S and T all represent intermediate quantities.

步骤S2、对第一半导体电阻条108的锚区109和锚区110之间施加恒定电流,再测量另外一侧的锚区113和锚区114之间的电压,电压与电流的比值即为电阻R1Step S2, apply a constant current between the anchor region 109 and the anchor region 110 of the first semiconductor resistance strip 108, and then measure the voltage between the anchor region 113 and the anchor region 114 on the other side, and the ratio of the voltage to the current is the resistance R 1 ;

步骤S3、对第二半导体电阻条106锚区112和锚区113之间施加恒定电流,再测量锚区110和锚区111之间的电压,电压与电流的比值即为电阻RAStep S3, applying a constant current between the anchor region 112 and the anchor region 113 of the second semiconductor resistance strip 106, and then measuring the voltage between the anchor region 110 and the anchor region 111, and the ratio of the voltage to the current is the resistance RA ;

步骤S4、根据电阻R1,方块电阻Rsq与第二半导体电阻条106的几何尺寸关系,根据第一半导体电阻条108的厚度与台阶的几何尺寸关系,以及根据电阻R1,方块电阻Rsq与第一半导体电阻条108的几何尺寸关系,建立公式组,表达式为:Step S4, according to the resistance R 1 , the sheet resistance R sq and the geometrical dimension relationship of the second semiconductor resistance strip 106 , according to the thickness of the first semiconductor resistance strip 108 and the geometric dimension relationship of the steps, and according to the resistance R 1 , the square resistance R sq The relationship with the geometric size of the first semiconductor resistance strip 108 is established, and a formula group is established, and the expression is:

Figure GDA0003539871750000072
Figure GDA0003539871750000072

公式组中,W表示第二半导体电阻条106的宽度,Rsq表示方块电阻,R1表示第一半导体电阻条108的电阻,L1表示第二半导体电阻条106的有效长度,RA表示第二半导体电阻条106的电阻,S1表示凹槽107顶面的长度,S2表示台阶长度的一半,S3表示凹槽107侧壁的长度,β表示凹槽107侧壁与凹槽107底面的夹角,t1表示第一半导体电阻条108的厚度,x为引入的一个中间变量,没有具体的物理意义,只是为了使公式(1)显得简洁明了,γ表示为拐角电阻的修正因子,n表示为台阶的数量;In the formula group, W represents the width of the second semiconductor resistance strip 106, R sq represents the sheet resistance, R 1 represents the resistance of the first semiconductor resistance strip 108, L 1 represents the effective length of the second semiconductor resistance strip 106, and R A represents the first semiconductor resistance strip 106. The resistance of the two semiconductor resistance strips 106, S1 represents the length of the top surface of the groove 107, S2 represents half the length of the step, S3 represents the length of the sidewall of the groove 107, β represents the sidewall of the groove 107 and the bottom surface of the groove 107 , t 1 represents the thickness of the first semiconductor resistance strip 108, x is an intermediate variable introduced, which has no specific physical meaning, just to make the formula (1) appear concise and clear, γ represents the correction factor of the corner resistance, n represents the number of steps;

步骤S5、将步骤S1得到的方块电阻Rsq,步骤S2得到的电阻R1以及步骤S3得到的电阻RA代入公式组(1)中,通过将测量得到的:第二半导体电阻条106的有效长度L1、凹槽107顶面的长度S1、台阶长度的一半S2、凹槽107侧壁的长度S3,台阶的数量n,拐角电阻的修正因子γ以及凹槽107侧壁与凹槽107底面的夹角β代入步骤S4建立的公式组中,得到半导体导电薄膜厚度,表达式为:Step S5: Substitute the sheet resistance R sq obtained in step S1, the resistance R1 obtained in step S2, and the resistance RA obtained in step S3 into the formula group ( 1 ), obtained by measuring: the effective value of the second semiconductor resistance strip 106 The length L 1 , the length S 1 of the top surface of the groove 107 , the half of the step length S 2 , the length S 3 of the side walls of the groove 107 , the number n of the steps, the correction factor γ of the corner resistance, and the side walls of the groove 107 and the groove 107 . The included angle β of the bottom surface of the groove 107 is substituted into the formula set established in step S4 to obtain the thickness of the semiconductor conductive film, and the expression is:

Figure GDA0003539871750000073
Figure GDA0003539871750000073

综上所述,本发明的测试方法简单,采用简单的直流电流源作为激励源,采用普通的电压测试设备,完成所有的激励与测试过程。测试结构采用基本的微机电加工工艺完成。To sum up, the testing method of the present invention is simple, using a simple DC current source as the excitation source, and using common voltage testing equipment to complete all excitation and testing processes. The test structure was completed using a basic MEMS process.

参见图3,下面以典型的两层半导体微机电表面加工工艺说明测试结构的制作过程。Referring to FIG. 3 , the fabrication process of the test structure is illustrated below with a typical two-layer semiconductor MEMS surface processing process.

选择N型半导体硅片,热生长100纳米厚度的二氧化硅层,通过低压化学气相沉积工艺淀积一层500纳米厚度的氮化硅,形成绝缘衬底118。采用低压化学气相沉积工艺沉积一层300纳米的半导体并进行N型重掺杂使该层半导体成为导体,通过光刻工艺刻蚀形成锚区(109-114)的一部分。使用低压化学气相沉积工艺沉积2000纳米厚度的介质层117,通过光刻工艺形成锚区(109-114)的图形以及凹槽107。An N-type semiconductor silicon wafer is selected, a silicon dioxide layer with a thickness of 100 nanometers is thermally grown, and a layer of silicon nitride with a thickness of 500 nanometers is deposited by a low pressure chemical vapor deposition process to form an insulating substrate 118 . A layer of 300 nm semiconductor is deposited by a low pressure chemical vapor deposition process and heavily doped with N type to make this layer of semiconductor a conductor, and a part of the anchor region (109-114) is formed by etching through a photolithography process. The dielectric layer 117 with a thickness of 2000 nm is deposited by a low pressure chemical vapor deposition process, and the patterns of the anchor regions (109-114) and the grooves 107 are formed by a photolithography process.

利用低压化学气相沉积工艺淀积一层1500纳米厚度的半导体层116,对半导体层116进行N型重掺杂,光刻工艺形成半导体测试结构图形和锚区(109-114),锚区(109-114)的厚度为两次半导体的厚度之和。A layer of semiconductor layer 116 with a thickness of 1500 nanometers is deposited by a low pressure chemical vapor deposition process, N-type heavy doping is performed on the semiconductor layer 116, and a photolithography process is used to form a semiconductor test structure pattern and anchor regions (109-114), anchor regions (109 The thickness of -114) is the sum of the thicknesses of the two semiconductors.

本发明未详述之处,均为本领域技术人员的公知技术。The parts that are not described in detail in the present invention are known techniques of those skilled in the art.

以上详细描述了本发明的较佳具体实施例。应当理解,本领域的普通技术人员无需创造性劳动就可以根据本发明的构思作出诸多修改和变化。因此,凡本技术领域中技术人员依本发明的构思在现有技术的基础上通过逻辑分析、推理或者有限的实验可以得到的技术方案,皆应在由权利要求书所确定的保护范围内。The preferred embodiments of the present invention have been described in detail above. It should be understood that those skilled in the art can make many modifications and changes according to the concept of the present invention without creative efforts. Therefore, any technical solutions that can be obtained by those skilled in the art through logical analysis, reasoning or limited experiments on the basis of the prior art according to the concept of the present invention shall fall within the protection scope determined by the claims.

Claims (6)

1. The thickness online test structure for the semiconductor conductive thin film comprises a circular semiconductor thin layer and first to fourth contact electrodes, wherein the four contact electrodes are uniformly arranged on the peripheral side of the circular semiconductor thin layer and are electrically connected with the circular semiconductor thin layer, and the opening angle formed by the four contact electrodes and the circular semiconductor thin layer is alpha; it is characterized by also comprising: the four-probe resistance testing bridge structure is arranged on the surface of the dielectric layer, a part of the surface of the dielectric layer is etched into a plurality of mutually parallel and same grooves, steps are formed among the grooves and have the same length, the grooves and the corresponding steps form a continuous stepped structure together, and the two side walls of the grooves and the surface of the dielectric layer have the same included angle; the four-probe resistance test bridge structure includes a first four-probe semiconductor resistance bridge and a second four-probe semiconductor resistance bridge, wherein,
the first four-probe semiconductor resistance bridge comprises a first semiconductor resistance strip and four metal electrodes, wherein one metal electrode is electrically connected to each side of the two ends of the first semiconductor resistance strip, the middle part of the first semiconductor resistance strip climbs over the continuous ladder structure, one end of the first semiconductor resistance strip is connected with the round semiconductor thin layer to form an integral structure, and the other end of the first semiconductor resistance strip is connected with the second four-probe semiconductor resistance bridge;
the second four-probe semiconductor resistance bridge comprises a second semiconductor resistance strip and two metal electrodes, wherein the second semiconductor resistance strip is arranged at the other end of the first semiconductor resistance strip and is connected with the first semiconductor resistance strip, the second semiconductor resistance strip and the first semiconductor resistance strip share the two metal electrodes, the second semiconductor resistance strip is arranged on the surface of a flat dielectric layer, and the second semiconductor resistance strip and the first semiconductor resistance strip have the same width.
2. The structure of claim 1, wherein the metal electrode is disposed on an anchor region formed by etching a surface of the dielectric layer.
3. The structure of claim 2, wherein the dielectric layer is disposed on the insulating substrate.
4. A method for testing a semiconductor conductive film thickness on-line test structure according to any one of claims 1-3, comprising the steps of:
step S1, obtaining the square resistance R of the circular semiconductor thin layer by mapping the circular semiconductor thin layer to a simple structure and combining the definition of the square resistancesq
Step S2, applying constant current to the two metal electrodes on the same side of the first semiconductor resistor strip, and measuring the voltage between the two metal electrodes on the other side, wherein the ratio of the voltage to the current is the resistor R1
Step S3, applying constant current to the two metal electrodes on the same side of the second semiconductor resistor strip, and measuring the voltage between the two metal electrodes on the other side, wherein the ratio of the voltage to the current is the resistor RA
Step S4, according to the resistance R1Square resistance RsqThe geometrical relation with the second semiconductor resistor strip, the geometrical relation between the thickness of the first semiconductor resistor strip and the step, and the relation between the resistance R1Square resistance RsqEstablishing a formula set (1) according to the relation of the geometric dimension of the first semiconductor resistor strip, wherein the formula is as follows:
Figure FDA0003128202640000021
in the formula group (1), W represents the width of the second semiconductor resistor strip, RsqDenotes the square resistance, R1Representing the resistance, L, of the first semiconducting resistor strip1Representing the effective length, R, of the second semiconducting resistive trackARepresenting the resistance, S, of the second semiconductor resistor strip1Indicates the length of the top surface of the groove, S2Representing half the length of the step, S3Indicating the length of the side wall of the grooveBeta represents the angle between the side wall and the bottom of the groove, t1The thickness of the first semiconductor resistor strip is expressed, an intermediate variable is introduced, no specific physical significance is realized, gamma is expressed as a correction factor of corner resistance, and n is expressed as the number of steps;
step S5, the sheet resistance R obtained in step S1sqResistance R obtained in step S21And the resistance R obtained in step S3ASubstituting into said set of equations (1), obtained by measuring: effective length L of second semiconductor resistor strip1Length S of the top surface of the groove1Half of step length S2Length S of side wall of groove3The number n of the steps, the correction factor gamma of the corner resistor and the included angle beta of the side wall of the groove and the bottom surface of the groove are substituted into the formula set (1) to obtain the thickness of the semiconductor conductive film.
5. The method as claimed in claim 4, wherein the step S1 specifically comprises:
step S101, applying a constant current between the first contact electrode and the fourth contact electrode, and measuring a voltage between the first contact electrode and the fourth contact electrode, wherein the ratio of the voltage to the current is a resistor Ra
Step S102, applying a constant current between the first contact electrode and the fourth contact electrode, and measuring a voltage between the second contact electrode and the fourth contact electrode, wherein the ratio of the voltage to the current is a resistor Rb
Step S103, establishing a formula set (2) according to the mapping from the circular semiconductor thin layer to the simple structure and the definition of the square resistance:
Figure FDA0003128202640000031
in formula group (2), P, Q, S and T both represent intermediate quantities, α is an unknown number, and represents the opening angle formed by the four contact electrodes and the circular semiconductor thin layer, and i is an imaginary unit,K[·]Representing an elliptic integral function of the first kind, RsqDenotes the square resistance, g, of a circular semiconductor thin layera(. alpha.) and gb(α) represents a function related only to the opening angle α;
step S103, the resistor R obtained in step S101aAnd the resistance R obtained in step S102bSubstituting the four contact electrodes into a formula group (2) to obtain the opening angle alpha formed by the four contact electrodes and the circular semiconductor thin layer;
step S104, substituting the opening angle alpha obtained in step S103 into formula (3) to obtain the square resistance RsqThe expression of formula (3) is:
Figure FDA0003128202640000032
in the formula (3), gaAnd (alpha) represents a function related to the opening angle alpha only, i is an imaginary unit, and P, Q, S and T both represent intermediate quantities.
6. The method as claimed in claim 5, wherein in step S5, the semiconductor conductive film thickness is expressed as:
Figure FDA0003128202640000033
CN202110695599.5A 2021-06-23 2021-06-23 A kind of semiconductor conductive film thickness on-line test structure and test method Active CN113267118B (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
CN202110695599.5A CN113267118B (en) 2021-06-23 2021-06-23 A kind of semiconductor conductive film thickness on-line test structure and test method
PCT/CN2022/099950 WO2022268039A1 (en) 2021-06-23 2022-06-20 Online thickness measurement structure for semiconductor conductive thin film and measurement method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110695599.5A CN113267118B (en) 2021-06-23 2021-06-23 A kind of semiconductor conductive film thickness on-line test structure and test method

Publications (2)

Publication Number Publication Date
CN113267118A CN113267118A (en) 2021-08-17
CN113267118B true CN113267118B (en) 2022-05-17

Family

ID=77235614

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110695599.5A Active CN113267118B (en) 2021-06-23 2021-06-23 A kind of semiconductor conductive film thickness on-line test structure and test method

Country Status (2)

Country Link
CN (1) CN113267118B (en)
WO (1) WO2022268039A1 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113267118B (en) * 2021-06-23 2022-05-17 东南大学 A kind of semiconductor conductive film thickness on-line test structure and test method

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE19510579C2 (en) * 1995-03-23 1997-08-21 Inst Physikalische Hochtech Ev Angle of rotation or speed sensor
JP5065614B2 (en) * 2006-04-14 2012-11-07 株式会社アルバック Eddy current film thickness meter
FR2946775A1 (en) * 2009-06-15 2010-12-17 St Microelectronics Rousset DEVICE FOR DETECTING SUBSTRATE SLIP DETECTION OF INTEGRATED CIRCUIT CHIP
CN102539930A (en) * 2012-01-19 2012-07-04 蚌埠玻璃工业设计研究院 Method for testing photoelectric performance of semiconductor thin film
CN102701146B (en) * 2012-05-31 2014-11-12 东南大学 Device for testing thickness of phosphorosilicate glass and polycrystalline silicon synchronously on line
CN104183052B (en) * 2013-05-24 2016-08-17 北京嘉岳同乐极电子有限公司 Thickness detection apparatus and manufacture method thereof
CN104390580B (en) * 2014-12-04 2018-06-22 上海集成电路研发中心有限公司 Metal film film thickness measurement system and the method that film thickness measurement is carried out using the system
US20190390949A1 (en) * 2018-06-21 2019-12-26 Applied Materials, Inc. Methods, apparatuses and systems for conductive film layer thickness measurements
CN112097626A (en) * 2020-10-23 2020-12-18 泉州师范学院 A method for measuring the thickness of metal thin films based on resistance method
CN112320754B (en) * 2020-10-28 2023-09-29 东南大学 Online testing structure and method for line width of semiconductor conductive film
CN113267118B (en) * 2021-06-23 2022-05-17 东南大学 A kind of semiconductor conductive film thickness on-line test structure and test method

Also Published As

Publication number Publication date
WO2022268039A1 (en) 2022-12-29
CN113267118A (en) 2021-08-17

Similar Documents

Publication Publication Date Title
CN112320754B (en) Online testing structure and method for line width of semiconductor conductive film
US10332811B2 (en) Film test structure and array substrate
CN113267118B (en) A kind of semiconductor conductive film thickness on-line test structure and test method
JPH0927529A (en) Semiconductor device for detecting alignment
CN110473909A (en) Standard wafer and its manufacturing method
JPS6410109B2 (en)
CN202609923U (en) Online synchronous testing device of thickness of phosphorosilicate glass and polycrystalline silicon
CN102701146B (en) Device for testing thickness of phosphorosilicate glass and polycrystalline silicon synchronously on line
KR20110043067A (en) Thin film thickness measuring instrument using 4-probe method
CN118625236B (en) An on-chip capacitance standard unit and its manufacturing method and linear value setting method
JP2021097106A (en) Electrostatic chuck inspection board, electrostatic chuck inspection system, and electrostatic chuck inspection method
WO2023279857A1 (en) Measurement method and system for semiconductor structure
KR100684268B1 (en) Planar Multi-junction Thermoelectric Converter for Accurately Measuring AC Voltage and Current and Manufacturing Method Thereof
KR101547892B1 (en) Device and method for generating metal to insulator transition
JPH10335229A (en) Mask misalignment evaluation test pattern
CN105446033A (en) Method for monitoring thickness of metal film
CN118882901A (en) Six-axis force sensor and manufacturing method thereof
CN119673794A (en) Method for testing surface stress of piezoelectric film of acoustic device
CN106933422B (en) A kind of touch sensor and preparation method of touch sensor
CN114582837A (en) Electrical test structure and method for monitoring Fin spacing drift in FinFET process
JP2006278421A (en) Structure for electric resistance measurement and method of evaluating contact resistance
JPH02277263A (en) Resistance network
CN115200729A (en) Array type thin film temperature difference sensor and preparation method thereof
JP2004288999A (en) Semiconductor device and method for manufacturing same
JPH04359448A (en) Semiconductor device and its estimation method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant