CN119673794A - Method for testing surface stress of piezoelectric film of acoustic device - Google Patents
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- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 5
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Abstract
本发明公开了一种声学器件压电薄膜表面应力的测试方法，包括：在晶圆上依次沉积下电极、压电薄膜和上电极，并在上电极表面通过光刻显影形成两组插指结构，然后测量其基准频率。在对测试晶圆加工后再次测量插指结构的测试频率并根据基准频率和测试频率的差异判断压电薄膜的应力类型和应力数值，涉及压电薄膜技术领域，解决了通过观察微结构是否发生变化判断晶圆内是否产生应力，但是这种方式难以准确获取应力的类型和大小的技术问题；根据基准频率与测试频率的差值、压电薄膜材料本身的性质及其厚度能够计算具体的应力大小，能够对后续的生产工艺进行调节提供具体的参考方向，在MEMS器件的生产制造过程中，可以更精确地控制和调节工艺参数。
The present invention discloses a method for testing the surface stress of a piezoelectric film of an acoustic device, comprising: depositing a lower electrode, a piezoelectric film and an upper electrode on a wafer in sequence, and forming two groups of interdigitated finger structures on the surface of the upper electrode by photolithography, and then measuring the reference frequency thereof. After processing the test wafer, the test frequency of the interdigitated finger structure is measured again, and the stress type and stress value of the piezoelectric film are judged according to the difference between the reference frequency and the test frequency. The method relates to the technical field of piezoelectric films, solves the technical problem that it is difficult to accurately obtain the type and magnitude of stress by observing whether the microstructure changes and judging whether stress is generated in the wafer; the specific stress magnitude can be calculated according to the difference between the reference frequency and the test frequency, the properties of the piezoelectric film material itself and its thickness, and a specific reference direction can be provided for adjusting the subsequent production process. In the production and manufacturing process of MEMS devices, the process parameters can be more accurately controlled and adjusted.
Description
Technical Field
The invention belongs to the technical field of piezoelectric film testing, and particularly relates to a method for testing surface stress of a piezoelectric film of an acoustic device.
Background
In the production and manufacture of MEMS (microelectromechanical systems) devices, multilayer piezoelectric films play a vital role. Piezoelectric thin films are typically deposited onto a substrate surface by Physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), or other process techniques, followed by photolithography and etching, to ultimately form a variety of precision device products.
In the deposition process of the piezoelectric film, the influence of residual stress on the device performance is very remarkable. Residual stresses can be categorized into external stresses and internal stresses, which are caused by the external environment and the internal structure, respectively. The stress of the piezoelectric film can be divided into tensile stress and compressive stress, and the generation mechanism is complex, and the stress relates to various aspects such as material characteristics, deposition conditions, environmental factors and the like.
The presence of stress can cause changes in the mechanical and electrical properties of the thin film material, affecting the sensitivity, reliability and lifetime of the device. Too much tensile stress can cause cracking of the film, while too much compressive stress can result in wrinkling or delamination of the film. Therefore, in MEMS processes, controlling and optimizing the stress of the thin film is a major goal, ensuring good performance and stability of the device during use.
However, the mechanism of stress generation of the piezoelectric thin film is complex, and there are external stress and internal stress, tensile force and compressive force, and the like. Therefore, the method is particularly important for stress characterization, but at present, the traditional stress characterization is mainly to manufacture a microstructure on the surface of a wafer, and judge whether the stress is generated in the wafer or not by observing whether the microstructure is changed or not, but the method is difficult to accurately acquire the type and the size of the stress, and only whether the production process needs to be regulated or not can be provided in the subsequent production process, and a specific reference direction cannot be provided.
Disclosure of Invention
The invention aims to at least solve one of the technical problems in the prior art, and therefore, the invention provides a method for testing the surface stress of a piezoelectric film of an acoustic device, which is used for solving the technical problems that whether the stress is generated in a wafer or not is judged by observing whether the microstructure is changed, but the type and the size of the stress are difficult to accurately acquire in the mode.
To achieve the above object, a first aspect of the present invention provides a method for testing surface stress of a piezoelectric film of an acoustic device, comprising the steps of:
S1, depositing a lower electrode, a piezoelectric film and an upper electrode on the surface of a wafer at one time to obtain a test wafer;
s2, planning an effective area on the surface of an upper electrode of the test wafer, and forming two groups of interdigital structures on the effective area on the surface of the test wafer through photoetching development;
S3, respectively connecting one ends of two groups of interdigital structures on the test wafer to a vector network analyzer, measuring the reference frequency F0 of the two groups of interdigital structures through the vector network analyzer, and disconnecting the interdigital structures from the vector network analyzer;
s4, after the test wafer is processed, one ends of the two groups of the interdigital structures on the test wafer are connected to a vector network analyzer, and the test frequency F1 of the two groups of the interdigital structures is measured through the vector network analyzer;
S5, judging the stress type and the stress value of the piezoelectric film according to the reference frequency F0 and the test frequency F1.
By comparing the reference frequency with the test frequency, the tensile stress and the compressive stress of the piezoelectric film can be clearly distinguished, and a clear direction is provided for process adjustment and device optimization. Meanwhile, the method can provide quantitative stress data, is favorable for accurately controlling the stress state of the film, and improves the performance and reliability of the device. The high sensitivity is convenient for early detection of slight stress variation, and the operation is simple and efficient.
Preferably, the determining the stress type and the stress value of the piezoelectric film according to the reference frequency F0 and the test frequency F1 includes:
comparing the reference frequency F0 with the test frequency F1;
when the reference frequency F0 is larger than the test frequency F1, marking the stress type of the surface of the piezoelectric film as tensile stress;
when the reference frequency F0 is smaller than the test frequency F1, marking the stress type of the surface of the piezoelectric film as compressive stress;
and calculating stress values according to the reference frequency F0 and the test frequency F1, wherein the stress values comprise tensile stress values and compressive stress values.
Preferably, the calculation formula for calculating the stress value according to the reference frequency F0 and the test frequency F1 is shown as sigma=K (F0-F1), wherein sigma is the stress value, and K is the influence coefficient.
The influence coefficient K needs to be determined according to the material and the characteristics of the device structure.
Preferably, the calculation formula of the influence coefficient is as follows
Wherein E is Young's modulus of the piezoelectric film, t is thickness of the piezoelectric film, ρ is density of the piezoelectric film, and v is Bobby ratio of the piezoelectric film.
The specific stress can be calculated according to the difference between the reference frequency and the test frequency, the property of the piezoelectric film material and the thickness thereof, and the specific reference direction can be provided when the subsequent production process is regulated according to the stress type and the size data.
Preferably, the finger inserting structure comprises a connecting end and finger inserting ends, the two groups of finger inserting structures are arranged in a mirror image mode, and the finger inserting ends on the two groups of finger inserting structures are arranged in a staggered mode.
The symmetrical mirror structure can effectively reduce the influence of parasitic capacitance and parasitic inductance, so that the measurement result is more reliable, the effective area of the interdigital structure can be increased by the staggered arrangement, the sensitivity is improved, and the more tiny frequency change can be detected.
The adjacent two finger ends have a certain gap.
Preferably, the planning of the effective area on the surface of the upper electrode of the test wafer includes the following steps:
taking the central line of the test wafer as a boundary line, taking n of the length of the central line to obtain a segmented line segment, overlapping the central point of the segmented line segment with the central point of the test wafer, and overlapping the segmented line segment with the central line, and making a boundary line perpendicular to the segmented line segment at two ends of the segmented line segment to obtain an interdigital area positioned at the central position and a connecting area positioned at two sides, wherein n is less than or equal to 1/2;
Extending the central line of the test wafer positioned in the connecting area to the two sides to a connecting width L1 to obtain a connecting area;
Calculating the length of the interpolation finger according to the formula D=2m×L1+ (2m+1) x L0, and marking a region surrounded by the interpolation length as a long segmentation line segment and the interpolation length as a width as an interpolation finger region, wherein L0 is the interval gap between two adjacent interpolation finger ends (2).
It should be noted that the connection width is set by itself based on the connection requirement.
Preferably, the materials of the lower electrode and the upper electrode are aluminum Al, platinum Pt, gold Au or molybdenum Mo.
Preferably, the piezoelectric film material is piezoelectric ceramic PZT or aluminum nitride AlN.
Preferably, the method further comprises the step S31 of forming a cavity structure on the effective area of the test wafer through deep silicon etching;
The deep silicon etching comprises the steps of cleaning a test wafer, depositing a hard mask material in an effective area of the wafer to be tested, and etching the test wafer through DRIE equipment, wherein the hard mask material is silicon dioxide or silicon nitride.
The cavity structure formed by deep silicon etching can accurately form the cavity structure with high depth-to-width ratio, and is applied to MEMS device manufacturing, and the cost is low due to abundant process experience and equipment support.
Preferably, the method comprises the steps of S1, forming a cavity structure on a wafer through a front release process to obtain a sacrificial material, adjusting the wafer, filling the cavity structure through the sacrificial material, depositing a lower electrode, a piezoelectric film and an upper electrode on the surface of the adjusting wafer at one time to obtain a test wafer, and releasing the sacrificial layer material through release holes etched in the piezoelectric film.
The release process is to use gas-phase hydrofluoric acid dry etching to form a cavity on the surface of the wafer to be tested.
It should be noted that, the etched position is the surface of the area to be tested of the wafer to be tested, the position and the size of the cavity can be controlled more precisely through the front release process, the consistency and the performance of the device are improved, the cavity structure is formed first, then the deposition of the electrode and the film is carried out, the stress and the deformation introduced in the deposition process can be reduced, the release process is directly carried out on the front, the wafer does not need to be turned over, the process flow is simplified, the production efficiency is improved, and the front release process can realize the design requirement more flexibly for the complex MEMS device needing to form the cavity in a plurality of areas.
Compared with the prior art, the method has the advantages that two groups of finger inserting structures are formed on the surface of the upper electrode of the test wafer, frequencies between the two end finger inserting structures are measured respectively by using the vector network analyzer to obtain the reference frequency and the test frequency, whether the stress on the surface of the piezoelectric film is the internal stress or the tensile stress can be obtained through the comparison of the frequencies of the two times, the specific stress size can be calculated according to the difference value of the reference frequency and the test frequency and the property and the thickness of the piezoelectric film material, the specific reference direction can be provided when the subsequent production process is regulated according to the stress type and the size data, the regulation effect of the production process can be more obviously realized by continuously using the method for multiple times, and the requirements of microstructure observation and other indirect stress measuring methods are reduced, so that the material and time cost in the production process are reduced, the whole manufacturing cost is reduced, the negative influence of the residual stress on the device performance can be controlled and regulated more accurately in the production and manufacturing process of MEMS devices, and the product quality and reliability are improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic flow chart of an embodiment of the first aspect of the present invention;
FIG. 2 is a schematic view of an interdigital structure according to an embodiment of the first aspect of the present invention;
FIG. 3 is a schematic view of an interdigital structure according to a second embodiment of the present invention;
In the figure, 1 is a connecting end, 2 is an inserting finger end.
Detailed Description
The technical solutions of the present invention will be clearly and completely described in connection with the embodiments, and it is obvious that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, an embodiment of the present invention provides a method for testing surface stress of a piezoelectric film of an acoustic device, including the following steps:
S1, depositing a lower electrode, a piezoelectric film and an upper electrode on the surface of a wafer at one time to obtain a test wafer;
s2, planning an effective area on the surface of an upper electrode of the test wafer, and forming two groups of interdigital structures on the effective area on the surface of the test wafer through photoetching development;
S3, respectively connecting one ends of two groups of interdigital structures on the test wafer to a vector network analyzer, measuring the reference frequency F0 of the two groups of interdigital structures through the vector network analyzer, and disconnecting the interdigital structures from the vector network analyzer;
S31, forming a cavity structure on an effective area of the test wafer through deep silicon etching;
s4, after the test wafer is processed, one ends of the two groups of the interdigital structures on the test wafer are connected to a vector network analyzer, and the test frequency F1 of the two groups of the interdigital structures is measured through the vector network analyzer;
S5, judging the stress type and the stress value of the piezoelectric film according to the reference frequency F0 and the test frequency F1.
The deep silicon etching includes cleaning the test wafer to remove impurities and oxide layers on the surface of the test wafer so as to ensure surface uniformity and cleanliness in the etching process, and etching the test wafer through a DRIE device after depositing a hard mask material in an effective area of the wafer to be tested, wherein the hard mask material is silicon dioxide or silicon nitride.
The cavity structure formed by deep silicon etching can accurately form the cavity structure with high depth-to-width ratio, and is applied to MEMS device manufacturing, and the cost is low due to abundant process experience and equipment support.
In this embodiment, the stress type and stress value of the piezoelectric film are determined according to the reference frequency F0 and the test frequency F1, and specifically include the following steps:
comparing the reference frequency F0 with the test frequency F1;
when the reference frequency F0 is larger than the test frequency F1, marking the stress type of the surface of the piezoelectric film as tensile stress;
when the reference frequency F0 is smaller than the test frequency F1, marking the stress type of the surface of the piezoelectric film as compressive stress;
and calculating stress values according to the reference frequency F0 and the test frequency F1, wherein the stress values comprise tensile stress values and compressive stress values.
The calculation formula for calculating the stress value according to the reference frequency F0 and the test frequency F1 is shown as sigma=K (F0-F1), wherein sigma is the stress value, and K is the influence coefficient.
The calculation formula of the influence coefficient is as followsWhere E is the Young's modulus of the piezoelectric film, t is the thickness of the piezoelectric film, ρ is the density of the piezoelectric film, and v is the Poisson's ratio of the piezoelectric film.
That is to say,
The piezoelectric film is made of aluminum nitride AlN, and has Young's modulus E of 330GPa, density ρ of 3260kg/m 3, thickness t of 2 μm, poisson's ratio of 0.28, reference frequency of 1MHz, test frequency of 0.95MHz, and influence coefficientThe stress value σ= 5.4936MPa, the stress at this time is a tensile stress, and the stress value is 5.4936MPa.
By comparing the reference frequency F0 and the test frequency F1, the stress type of the surface of the piezoelectric film can be determined as tensile stress or compressive stress, the stress type can be directly distinguished, a specific direction is provided for subsequent process adjustment and device optimization, quantitative stress data can be provided, the stress state of the film can be accurately controlled, the performance and reliability of the device are improved, the mode has high sensitivity, the problem of slight stress change is found in early stage, the mode is simple and efficient, and the mode is convenient when continuous test is carried out.
Referring to fig. 2, the finger inserting structure in this embodiment includes a connection end 1 and a finger inserting end 2, the two sets of finger inserting structures are mirror images, and the finger inserting ends 2 on the two sets of finger inserting structures are staggered.
The design of the interdigital structure can enhance the frequency response characteristic of the piezoelectric film, ensure that the reference frequency and the test frequency reflect the real stress change, provide more accurate stress measurement data, and the misplacement uniform distribution is favorable for optimizing the electric field distribution, and can reduce the locally concentrated electric field intensity, thereby improving the linearity and accuracy of measurement.
In order to form an interdigital structure on the surface of a test wafer, the embodiment plans an effective area on the surface of an upper electrode of the test wafer, and includes the following steps:
taking the central line of the test wafer as a boundary line, taking n of the length of the central line to obtain a segmented line segment, overlapping the central point of the segmented line segment with the central point of the test wafer, and overlapping the segmented line segment with the central line, and making a boundary line perpendicular to the segmented line segment at two ends of the segmented line segment to obtain an interdigital area positioned at the central position and a connecting area positioned at two sides, wherein n is less than or equal to 1/2;
Extending the central line of the test wafer positioned in the connecting area to the two sides to a connecting width L1 to obtain a connecting area;
Calculating the length of the interpolation finger according to the formula D=2m×L1+ (2m+1) ×L0, and marking a region surrounded by the interpolation length as a long segmentation line segment and the interpolation length as a width as an interpolation finger region, wherein L0 is the interval gap between two adjacent interpolation finger ends 2.
For example, the center line length of the test wafer is 10mm, n=1/2, the length of the segment is 5mm, and the center point of the segment is overlapped with the center point of the test wafer, so that the segment overlaps with the center line.
And (3) making a dividing line perpendicular to the dividing line at two ends of the dividing line to obtain an interdigital area at the central position and connecting areas at two sides.
The test wafer center line in the connection region is extended to the connection width L1 from both sides, the connection width L1 is set to 0.5mm, and the connection region width is 2×L1=1×0.5 mm=0.5 mm
When the connection width L1=0.5 mm, the interval gap L0=0.05 between two adjacent finger ends and the number m=8 of the fingers, calculating the finger length by the formula D=2m×L1+ (2m+1) ×L0;
the finger length D is calculated as follows:
D=2×8×0.5mm+ (2×8+1) ×0.05mm=8.85 mm, the size of the finger insertion region is a rectangle having a length of 8.85 and a width of 5mm and centered on the test wafer, and an interpolation structure is formed inside so that it is located at the center position, so that the accuracy of the test can be ensured.
The materials of the lower electrode and the upper electrode can be aluminum Al, platinum Pt, gold Au or molybdenum Mo;
specifically, aluminum Al is used as a material of the lower electrode and the upper electrode, and is suitable for large-scale production and application due to relatively low cost, has excellent conductivity, can ensure the current transmission efficiency of the electrodes, and is easy to deposit and process by sputtering, vapor deposition and other methods;
Platinum Pt is used as a material for the lower electrode and the upper electrode, and because in certain MEMS and sensor applications, the catalytic performance of platinum can improve the sensitivity of the device, and platinum has high chemical stability under high temperature and corrosive environments, and platinum also has high conductivity, so that the platinum is suitable for being used as an electrode material;
Gold Au is used as a material of the lower electrode and the upper electrode, can effectively reduce resistance and energy loss due to high conductivity, is inert to most chemical substances, is not easy to oxidize and corrode, is suitable for being used in a severe environment, and is excellent in high-reliability application due to stability and conductivity;
molybdenum Mo is used as the material of the lower electrode and the upper electrode, and is suitable for being used in a high-temperature environment due to the high melting point of molybdenum, has high mechanical strength and hardness, can improve the structural strength and durability of the electrode, has good conductivity, and can provide stable electrical performance in high-temperature and high-pressure application.
In this embodiment, gold Au is preferred for the lower electrode and upper electrode materials, since each material has its own advantages.
In this embodiment, the piezoelectric thin film material is piezoelectric ceramic PZT and aluminum nitride AlN.
The specific aluminum nitride AlN is used as a piezoelectric film material, and the aluminum nitride material has good stability in high-temperature and chemical corrosion environments, so that the piezoelectric film material is suitable for being used in severe environments, and the piezoelectric ceramic PZT material keeps stable piezoelectric performance in a wide temperature range and is suitable for being used in various extreme environments, so that the aluminum nitride AlN can be adopted as the piezoelectric film material.
In a second aspect, please participate in fig. 3, as another embodiment of the present invention, unlike the above embodiment, S1, a cavity structure is formed on a wafer by a front release process to obtain a sacrificial material and an adjustment wafer, the cavity structure is filled with the sacrificial material;
s2, planning an effective area on the surface of an upper electrode of the test wafer, and forming two groups of interdigital structures on the effective area on the surface of the test wafer through photoetching development;
S3, respectively connecting one ends of two groups of interdigital structures on the test wafer to a vector network analyzer, measuring the reference frequency F0 of the two groups of interdigital structures through the vector network analyzer, and disconnecting the interdigital structures from the vector network analyzer;
s4, after the test wafer is processed, one ends of the two groups of the interdigital structures on the test wafer are connected to a vector network analyzer, and the test frequency F1 of the two groups of the interdigital structures is measured through the vector network analyzer;
S5, judging the stress type and the stress value of the piezoelectric film according to the reference frequency F0 and the test frequency F1.
The release process is to use gas-phase hydrofluoric acid dry etching to form a cavity on the surface of the wafer to be tested.
The position and the size of the cavity can be controlled more accurately through the front release process, the consistency and the performance of the device are improved, the cavity structure is formed firstly, then the deposition of the electrode and the film is carried out, the stress and the deformation introduced in the deposition process can be reduced, the release process is directly carried out on the front, the wafer is not required to be turned over, the process flow is simplified, the production efficiency is improved, and the front release process can more flexibly realize the design requirement for complex MEMS devices needing to form the cavity in a plurality of areas.
The method comprises the steps of obtaining a plurality of data, wherein part of data in the formula is obtained by removing dimensions and taking the numerical calculation, the formula is a formula closest to the actual situation by simulating a large amount of collected data through software, and preset parameters and preset thresholds in the formula are set by a person skilled in the art according to the actual situation or are obtained through simulating the large amount of data.
The above embodiments are only for illustrating the technical method of the present invention and not for limiting the same, and it should be understood by those skilled in the art that the technical method of the present invention may be modified or substituted without departing from the spirit and scope of the technical method of the present invention.
Claims (10)
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