CN118625236B - An on-chip capacitance standard unit and its manufacturing method and linear value setting method - Google Patents
An on-chip capacitance standard unit and its manufacturing method and linear value setting method Download PDFInfo
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Abstract
The invention belongs to the technical field of standard capacitors, in particular to an on-chip capacitor standard sample unit, a manufacturing method thereof and a linear fixed value method, wherein the on-chip capacitor standard unit comprises a basic capacitor and a standard capacitor, the standard capacitor is obtained by adding the logarithm of an interdigital electrode on the basic capacitor, the standard capacitance value of the on-chip capacitance standard unit is the difference between the capacitance values of the standard capacitance and the basic capacitance, and the standard capacitance value and the interdigital electrode pair number of the standard capacitance are in linear relation under the nominal stepping capacitance value of the standard capacitance. The standard capacitance value of the on-chip capacitance standard cell is determined based on the nominal step capacitance value and the interdigital electrode pair number of the standard capacitance, so that the standard capacitance value changes linearly with the interdigital electrode pair number. According to the invention, the standard capacitance value and the interdigital electrode logarithm of the standard capacitance are linearly related through the nominal stepping capacitance value, and once the nominal stepping capacitance value is determined, the capacitance standard unit can be fixed according to the interdigital electrode logarithm, so that the method is very convenient and efficient.
Description
Technical Field
The invention belongs to the technical field of standard capacitors, and particularly relates to an on-chip capacitor standard sample unit, a manufacturing method thereof and a linear fixed value method.
Background
Integrated circuit testing is of vital importance in the electronics industry, and plays a vital role in ensuring the functionality, reliability and security of electronic products. And the process monitoring (PCM) in the semiconductor process monitors the key process quality in the semiconductor production process by measuring the electrical parameters on the PCM graph, and judges whether the thickness of the medium meets the design requirement by detecting the capacitance value, thereby effectively ensuring the process consistency.
Semiconductor capacitors are typically either picofarad (pF) or nanofarad (nF) levels. Some applications require very sensitive capacitance measurements at the fly-front (fF) level, including measuring metal-to-metal capacitance, interconnect capacitance on a wafer, capacitance between terminals on MEMS devices such as switches, or nano-devices. Meanwhile, as the critical dimensions of the integrated circuit chip are continuously reduced, the feature dimensions of the MOSFET are smaller and smaller, the proportion of the parasitic capacitance around the gate in the overall capacitance is larger and larger, and the parasitic effect of the capacitance is more and more serious. Parasitic capacitance will have effects on circuit delay, frequency characteristics, stability, etc. There is an increasing demand in numerous fields for metering small capacitances on-chip of the femtofarad (fF) class. Accurate on-chip capacitance measurement of an integrated circuit requires accurate on-chip capacitance standard samples, however, related research on small on-chip capacitance standard samples of fF stage in China is relatively less, and particularly calibration of the on-chip capacitance standard samples of fF stage is realized.
Chinese patent (CN 112666506 a) discloses an integrated circuit calibration on-chip capacitance standard sample, which requires multiple iterations of capacitance size to find the optimal capacitance size using complex scaling structures when reproducing a specific capacitance value.
Disclosure of Invention
The invention aims to solve the problems in the prior art and provides an on-chip capacitance standard sample unit, a manufacturing method thereof and a linear fixed value method.
The invention is realized by the following technical scheme:
the standard capacitance value of the standard capacitance unit on the chip is the difference between the capacitance values of the standard capacitance and the base capacitance, and the standard capacitance value is in linear relation with the interdigital electrode pair number of the standard capacitance under the nominal stepping capacitance value of the standard capacitance, wherein the nominal stepping capacitance value is the capacitance value which is increased correspondingly by adding a pair of interdigital electrodes.
Further, the basic capacitor comprises two composite electrodes, each composite electrode comprises a probe contact electrode and interdigital electrodes, the number of the interdigital electrodes is 1, the interdigital electrodes are connected with the probe contact electrodes through connecting wires, the two composite electrodes are oppositely arranged, and the interdigital electrodes are mutually parallel to form an interdigital electrode pair.
Furthermore, the standard capacitor comprises two composite electrodes, each composite electrode comprises a probe contact electrode and interdigital electrodes, the number of the interdigital electrodes is n, n is more than or equal to 2, the interdigital electrodes are arranged at equal intervals and are electrically connected with the probe contact electrodes through the same connecting wire, the two composite electrodes are oppositely arranged, and the interdigital electrodes form n interdigital electrode pairs through the interval between the interdigital electrodes of each other.
Further, the substrate of the basic capacitor or the standard capacitor is made of borosilicate glass, sapphire or fused quartz.
The invention also provides a manufacturing method of the on-chip capacitance standard unit, which is used for manufacturing the on-chip capacitance standard unit with different names and meanings for capacitance values, and comprises the following steps:
simulating the on-chip capacitance standard unit under the set stepping capacitance value;
acquiring capacitance parameters of a simulation on-chip capacitance standard unit with corresponding stepping capacitance values;
determining a capacitance parameter range according to the capacitance parameter, and manufacturing real objects of a plurality of on-chip capacitance standard units in the capacitance parameter range;
Measuring the step capacitance value of the real object, and acquiring the capacitance parameter of the real object closest to the set step capacitance value as an optimal capacitance parameter;
Calculating theoretical capacitance value C w of a single pair of interdigital electrodes according to the optimal capacitance parameter, and calculating influence coefficient m between the interdigital electrode pairs according to a calculation formula of a stepping capacitance value, wherein the influence coefficient m between the interdigital electrode pairs is applicable to the same series of standard capacitances, and the same series of standard capacitances are standard capacitances with only different electrode lengths;
Changing the length of the interdigital electrode according to the influence coefficient m between the interdigital electrode pairs to calculate the nominal stepping capacitance value of the same series of standard capacitors;
and manufacturing an on-chip capacitance standard unit according to the capacitance parameter corresponding to the nominal stepping capacitance value.
The invention also provides a linear constant value method of the on-chip capacitance standard unit, which comprises the following steps:
Acquiring a nominal stepping capacitance value of the standard capacitor;
And determining the standard capacitance value of the on-chip capacitance standard unit based on the nominal stepping capacitance value and the interdigital electrode pair number of the standard capacitance, so that the standard capacitance value linearly changes along with the interdigital electrode pair number.
Further, the calculation formula of the nominal step capacitance value is as follows:
CSp＝2mCw
Wherein C Sp represents a nominal stepping capacitance value, C w represents a theoretical capacitance value of a single pair of interdigital electrodes, and m represents an influence coefficient between the interdigital electrode pairs.
Further, the inter-electrode influence coefficient m in the standard capacitance is determined as follows:
simulating the on-chip capacitance standard unit under the set stepping capacitance value;
acquiring capacitance parameters of a simulation on-chip capacitance standard unit with corresponding stepping capacitance values;
determining a capacitance parameter range according to the capacitance parameter, and manufacturing real objects of a plurality of on-chip capacitance standard units in the capacitance parameter range;
Measuring the step capacitance value of the real object, and acquiring the capacitance parameter of the real object closest to the set step capacitance value as an optimal capacitance parameter;
And calculating a theoretical capacitance value C w of the single pair of interdigital electrodes according to the optimal capacitance parameter, and calculating an influence coefficient m between the interdigital electrode pairs according to a calculation formula of the stepping capacitance value.
Further, the calculation formula of the standard capacitance value is as follows:
C=CSp(n-1)
Wherein, C represents a standard capacitance value, C Sp represents a nominal stepping capacitance value, n represents the logarithm of interdigital electrodes of the standard capacitance, and n is more than or equal to 2.
Further, the capacitance parameters comprise the size parameters and the dielectric constants of the interdigital capacitors formed by the interdigital electrode pairs, other capacitance parameters are unchanged, and the capacitance parameter range is determined by setting the upper limit and the lower limit of the length of the interdigital electrodes.
Compared with the prior art, the invention has the beneficial effects that:
1. The invention eliminates the interference of extra capacitors except the interdigital capacitor structure (formed by the interdigital electrode pairs) in the standard capacitor through the base capacitor, wherein the standard capacitor value of the on-chip capacitor standard unit is the difference between the standard capacitor and the base capacitor, that is to say, the standard capacitor value corresponds to the capacitance value of the interdigital capacitor after the base capacitor is subtracted by the standard capacitor, and the capacitance value of the interdigital capacitor is smaller, so that the requirement of the flying method grade value can be met.
2. The invention considers the mutual influence between the interdigital electrode pairs, namely introduces the influence coefficient m between the interdigital electrode pairs, can more accurately represent the nominal stepping capacitance value and improves the precision of the standard capacitance value.
3. After the influence coefficient m between the interdigital electrode pairs under a certain electrode length is determined, the stepping capacitance value of the same series of standard capacitors can be expanded, namely the influence coefficient m of the same series of standard capacitors is the same, the theoretical capacitance value C w of the single pair of interdigital electrodes of the same series of standard capacitors is different, the same series of standard capacitors only have differences in electrode length, and other capacitance parameters are the same, so that the theoretical capacitance value C w of the single pair of interdigital electrodes of the same series of standard capacitors can be calculated according to the electrode length, and then the theoretical capacitance value C w and the influence coefficient m are substituted into a calculation formula of the nominal stepping capacitance value to calculate the nominal stepping capacitance value of the same series of standard capacitors.
4. According to the invention, the standard capacitance value and the interdigital electrode pair number of the standard capacitance are linearly related through the nominal stepping capacitance value, once the nominal stepping capacitance value is determined, the capacitance standard unit can be fixed according to the interdigital electrode pair number, and the repeated size iteration is not required as in the prior art, so that the method is very convenient and efficient.
Drawings
FIG. 1 is a schematic diagram of a standard capacitor;
FIG. 2 is a schematic diagram of a basic capacitor structure;
FIG. 3 is a schematic diagram of a structure of an interdigital electrode pair;
FIG. 4 is a graph comparing simulation values to theoretical calculation values for pairs of interdigitated electrodes of different lengths;
FIG. 5 is a graph showing the change in capacitance of the interdigital capacitor after the interdigital electrode pair number is increased;
FIG. 6 is a flow chart of a capacitor making process;
FIG. 7 shows the standard capacitance values corresponding to different electrode pairs for an interdigital electrode length of 180 μm;
FIG. 8 is a schematic view of the direction of increase of the interdigital electrode pairs;
Fig. 9 is a graph showing the measured value of the capacitance standard cell at a nominal step capacitance of 10 fF.
Detailed Description
The on-chip capacitance standard sample wafer solves the on-chip small capacitance parameter calibration and calibration metering requirements, and aims at different capacitance structures, and capacitance standard units with different capacitance values are needed. In order to obtain on-chip capacitance standard units with different capacitance values, the geometric dimensions of the interdigital electrodes need to be changed. Every time a capacitor with different capacitance is manufactured, repeated iterations of the geometry of the interdigital electrode are performed to obtain an accurate capacitance.
The invention provides an on-chip capacitance standard unit, which comprises a base capacitance and a standard capacitance, wherein the standard capacitance is obtained by adding the logarithm of an interdigital electrode on the base capacitance, the standard capacitance value of the on-chip capacitance standard unit is the difference between the capacitance values of the standard capacitance and the base capacitance, the standard capacitance value is in linear relation with the interdigital electrode logarithm of the standard capacitance under the nominal stepping capacitance value of the standard capacitance, and the nominal stepping capacitance value is the capacitance value which is added correspondingly to each pair of interdigital electrodes.
According to the invention, the linear stepping of the capacitance value is realized by changing the logarithm of the interdigital electrode on the standard capacitor, so that the calibration of the capacitor standard sample on the fly-by-fly chip becomes efficient and convenient.
The invention is described in detail below with reference to the accompanying drawings. It should be noted that the described embodiments are only intended to facilitate an understanding of the invention and do not have any limiting effect on it.
First), fly-level capacitance standard cell modeling
Referring to fig. 1, a standard capacitor includes two composite electrodes, each of which includes a probe contact electrode 1 and an interdigital electrode 3, the number of interdigital electrodes 3 is n, n is equal to or greater than 2, the interdigital electrodes 3 are arranged at equal intervals and are connected with the probe contact electrode 1 through the same connecting wire 2, the two composite electrodes are oppositely arranged, and the interdigital electrodes form n interdigital electrode pairs through the interval between the interdigital electrodes of each pair, the interdigital electrode pairs form an interdigital capacitor, and the capacitance value of the interdigital capacitor can reach the level of the femtofarads.
Because the standard capacitor comprises capacitance structures except the interdigital capacitor, such as additional capacitors of the capacitance between the contact electrodes of the probe, the capacitance between the connecting wires and the like, the capacitance value of the standard deviation value capacitor is difficult to directly measure. To eliminate the effect of the extra capacitance, a base capacitance is introduced.
The only difference between the basic capacitance and the standard capacitance is the number of interdigital electrode pairs, which is smaller than that of the standard capacitance. For example, a standard capacitor having 3 pairs of interdigital electrodes may be used as the base capacitor, and a standard capacitor having 2 pairs of interdigital electrodes may be used as the base capacitor.
In this embodiment, in order to improve the versatility of the base capacitance, a standard capacitance having a pair of interdigital electrodes is used as the base capacitance. Referring to fig. 2, a basic capacitor includes two composite electrodes, each of which includes a probe contact electrode and an interdigital electrode, the number of interdigital electrodes is 1, the interdigital electrodes are connected with the probe contact electrode through a connecting wire, the two composite electrodes are disposed opposite to each other, and the interdigital electrodes thereof are parallel to each other to form an interdigital electrode pair.
The capacitance value of the capacitance standard unit is obtained by subtracting the capacitance value of the basic capacitance from the standard capacitance value, and the capacitance value is expressed as follows by adopting a formula:
C=CT-C0; (1)
Wherein, C represents the capacitance value of the standard capacitance unit, C T represents the total capacitance value of the standard capacitance, and C 0 represents the capacitance value of the basic capacitance.
The basic capacitance structure has the effects of eliminating external interference, capacitance between transmission lines, capacitance between test probes and interference of redundant structures except the interdigital electrodes, and ensuring that the capacitance value is linearly increased when the interdigital electrode pair number is increased.
Second), determining the stepping capacitance value C sp
As shown in fig. 3, which is a top view and a cross-sectional view of one interdigital electrode pair, the capacitance C w between two interdigital electrodes is mainly composed of C 1,C2,C3, and the calculation formula is as follows:
Cw＝C1+C2+C3
Wherein C 2 is the capacitance of the plate capacitor structure formed by the opposite interdigital electrodes, and C 1、C3 is the lateral capacitance of the plate capacitor structure.
C 2 is a common plate capacitor structure, and can be calculated by formula (2):
where ε is the dielectric constant of the medium between the plates, L is the electrode length, T is the electrode thickness, d is the relative distance of the plates (i.e., the relative distance of the interdigital electrodes), and d=2a.
C 1 and C 3 are equal and can be calculated by the method of the Schwarz-Kelitofe corner-preserving transformation, as shown in formula (3):
Wherein K () is a first type of complete elliptic integral, a is half of the distance between electrodes, b is the electrode width, L is the electrode length, ε 1 is the relative permittivity of the upper half space of the electrodes, ε 2 is the permittivity of the lower half space of the electrodes, ε 0 is the permittivity of vacuum.
Since the upper half space of the electrode is typically air, epsilon 1 in this embodiment uses the dielectric constant of air. Obviously, the lower half space of the electrode is the substrate of the capacitor, and epsilon 2 is the relative dielectric constant of the substrate of the capacitor.
After the relative dielectric constant is obtained, the dielectric constant can be calculated according to the formula dielectric constant=relative dielectric constant×dielectric constant of vacuum.
The theoretical calculated capacitance for a single pair of interdigitated electrodes, C w, is the sum of C 1、C2 and C 3. Under the condition that other parameters of the capacitance are unchanged, single-pair interdigital electrodes with different lengths are obtained by changing the lengths of the electrodes, capacitance theoretical calculation values C w of each pair of interdigital electrodes are calculated respectively, and simulation is carried out correspondingly to obtain capacitance simulation values of each pair of interdigital electrodes, as shown in a simulation and theoretical comparison diagram of C w in FIG. 4, the simulation values and the theoretical calculation values basically coincide, the simulation values and the calculation values are mutually verified, and the simulation and calculation are accurate.
Fig. 5 is a schematic diagram showing the increase of the number of pairs of the interdigital electrodes, and (a), (b), and (c) represent the cases where the number of pairs of the interdigital electrodes is 1,2, and 3, respectively. A-E represent the capacitance between the two electrodes. When the electrode pair is changed from 0 to 1 as in fig. 5 (a), the capacitance a is increased. When the electrode pair is changed from 1 to 2 as in fig. 5 (B), the capacitances B and C are increased. When the electrode pair is changed from 2 to 3 as in fig. 5 (c), the capacitances D and E are increased. So the change in capacitance is not linear when the interdigital electrode pair number starts to increase from 0 to zero. Meanwhile, when the number of the interdigital electrode pairs is increased, adjacent interdigital electrodes can be mutually influenced, such as B and A in fig. 5 (B), namely the values of the capacitance A in fig. 5 (a) and 5 (B) are different, and the capacitance A in fig. 5 (B) and 5 (c) are the same, so in order to ensure the linearity of the capacitance change when the number of the interdigital electrodes is increased, the basic capacitance should be designed to be composed of a probe contact electrode, a connecting wire and one interdigital electrode pair, as shown in fig. 2.
The capacitance value of the interdigital capacitor after the interdigital electrode pair is increased is calculated based on the capacitance value of the single interdigital electrode pair, but when the interdigital electrode pair is increased, adjacent interdigital electrodes are mutually affected, so that the capacitance value C w of one pair of interdigital electrodes cannot be calculated simply by multiplying the interdigital electrode pair by 2 times. Also should multiply by a factor m, then there is:
CT＝C0+2mCw(n-1) (4)
Wherein C T represents the capacitance value of the standard capacitor, C 0 represents the capacitance value of the base capacitor, the theoretical capacitance calculation value C w of a single pair of interdigital electrodes, n represents the interdigital electrode pair number of the standard capacitor, n is more than or equal to 2, and m represents the influence coefficient between the interdigital electrode pairs.
Combining equation (1) with equation (4) yields:
C=2mCw(n-1) (5)
wherein, C represents the capacitance value of a capacitance standard unit, namely the standard capacitance value, C w represents the capacitance theoretical calculation value of a pair of interdigital electrodes, n represents the interdigital electrode pair number, and n is more than or equal to 2.
To achieve linearization of the constant value, a stepped capacitance value C Sp is introduced:
CSp＝2mCw (6)
And (3) combining the formulas (5) and (6) to obtain:
C=CSp(n-1) (7)
according to the formula (7), at a certain step capacitance value C Sp, the standard capacitance value and the interdigital electrode logarithm are in linear relation.
The inter-electrode influence coefficient m in the standard capacitance is determined as follows:
S1, simulating an on-chip capacitance standard unit under a set stepping capacitance value.
In the specific embodiment, finite element simulation is adopted, in order to obtain an accurate stepping capacitance value, when simulation is carried out, the electrode pair number of the basic capacitor is more than or equal to 2, and the interdigital electrode pair number of the standard capacitor is more than 1 than the interdigital electrode pair number of the basic capacitor, so that the capacitance value added by each pair of interdigital electrodes added on the standard capacitor can be obtained by subtracting the simulation value of the basic capacitor from the simulation value of the standard capacitor, namely the stepping capacitance value.
In the simulation, the number of the interdigital electrode pairs of the standard capacitor can be 2 or more than that of the interdigital electrode pairs of the base capacitor, and then the difference between the simulation value of the standard capacitor and the simulation value of the base capacitor is divided by the difference between the interdigital electrode pairs of the standard capacitor and the base capacitor in the step capacitor value calculation.
And S2, acquiring capacitance parameters of the simulation on-chip capacitance standard unit with the corresponding stepping capacitance value.
The capacitance parameters comprise the size parameters and dielectric constants of the interdigital capacitors formed by the interdigital electrode pairs;
The dimensional parameters of the capacitor include the relative distance d of the interdigital electrodes, the electrode length L of the interdigital electrodes and the thickness T.
The dielectric constants include the dielectric constants epsilon of the medium between the flat plates in the formula (2) and the formula (3), and the dielectric constant epsilon 1 of the upper half space of the electrode is the dielectric constant epsilon 2,ε0 of the lower half space of the electrode is the dielectric constant of vacuum.
And S3, determining a capacitance parameter range according to the capacitance parameter, and manufacturing real objects of a plurality of on-chip capacitance standard units in the capacitance parameter range.
In this embodiment, the capacitance parameter range is determined by setting the upper and lower limits of the length of the interdigital electrode, with the other capacitance parameters unchanged.
For example, the electrode length of the simulation on-chip capacitance standard unit with the corresponding stepping capacitance value is 150nm, the capacitance parameter range is set to be 100,200, and a plurality of parameters are selected in the capacitance parameter range to manufacture the simulation on-chip capacitance standard unit, the simulation on-chip capacitance standard unit can be selected according to a certain step length, the step length is set to be 10nm, and the length parameters of each electrode are different by 10nm.
A series of on-chip capacitance standard units within the capacitance parameter range are manufactured on the same substrate. The micro-nano processing technology such as photoresist patterning, film etching and the like is realized through magnetron sputtering deposition film and ultraviolet exposure.
The specific process flow is shown in fig. 6. The method comprises the following steps of (1) cleaning a substrate, namely cleaning and removing organic pollution on the surface of borosilicate glass by using acetone, ethanol and isopropyl alcohol (IPA), cleaning and removing metal pollution ions remained on the surface of the substrate by using concentrated sulfuric acid and hydrogen peroxide, (2) photoetching, namely carrying out photoetching exposure by using a designed photoetching plate to define a capacitor structure pattern, and (3) depositing metal by using a metal sputtering or evaporating process. And (4) removing redundant metal by adopting a wet etching process.
And S4, measuring the step capacitance value of the real object, and obtaining the capacitance parameter of the real object closest to the set step capacitance value as an optimal capacitance parameter.
And each on-chip capacitance standard unit (entity) comprises a base capacitance and a standard capacitance, and capacitance values of the base capacitance and the standard capacitance are measured respectively, namely, the probe is contacted with a probe contact electrode through a probe station, and capacitance values of the base capacitance and the standard capacitance are measured respectively through an LCR (inductance capacitance ratio) meter.
And then subtracting the capacitance value of the measured basic capacitance from the capacitance value of the measured standard capacitance to obtain a stepping capacitance value.
And S5, calculating a theoretical capacitance value C w of the single pair of interdigital electrodes according to the optimal capacitance parameter, and calculating an influence coefficient m between the interdigital electrode pairs according to a calculation formula of the stepping capacitance value.
The theoretical capacitance value C w of a single pair of interdigital electrodes corresponds to the case of only one pair of interdigital electrodes, i.e., the case of no interaction between electrode pairs.
Substituting the calculated theoretical capacitance value C w of the single pair of interdigital electrodes and the set stepping capacitance value C Sp into a formula (6) to calculate the influence coefficient m between the interdigital electrode pairs. The coefficient m is a positive number smaller than 1, and the value range of m is 0.7-0.8.
In order to verify whether the physical step capacitance value can carry out linearization fixed value on the capacitance standard unit, simulation and actual measurement are carried out, the set step capacitance value is 10fF, the capacitance parameters are epsilon is the dielectric constant of a medium between flat plates, epsilon 1 is the dielectric constant of air, epsilon 2 is the dielectric constant of borosilicate glass, the relative dielectric constant is 4.6, the relative distance d between the flat plates is 12 microns, the electrode length L is 180 microns, and the electrode thickness T is 800nm.
Simulation and measured values are compared, and as shown in fig. 7, the standard capacitance value of the capacitance standard cell increases linearly with the increase of the interdigital electrode pair, and each of the measured value and the simulation value increases by about 10 fF.
Third), making serial capacitance standard unit
After the influence coefficient m between the interdigital electrode pair under a certain electrode length is determined, the stepping capacitance value of the same series of standard capacitors can be expanded, and the specific steps are as follows:
And calculating theoretical capacitance value C w of a single pair of interdigital electrodes according to the optimal capacitance parameter, and calculating influence coefficient m between the interdigital electrode pairs according to a calculation formula of a stepping capacitance value, wherein the influence coefficient m between the interdigital electrode pairs is suitable for the same series of standard capacitances, and the same series of standard capacitances are standard capacitances with only different electrode lengths.
Changing the length of the interdigital electrode according to the influence coefficient m between the interdigital electrode pairs to calculate the nominal stepping capacitance value of the same series of standard capacitors;
As shown in fig. 8, the increasing direction of the pair of interdigital electrodes is along the X-axis direction and the increasing direction of the length of the interdigital electrodes is along the Y-axis direction, so that the influence between the pair of interdigital electrodes occurs in the X-axis direction, and thus the influence between the pair of interdigital electrodes is independent of the length. The same series standard capacitors only have differences in electrode lengths, other capacitance parameters are the same, the influence coefficients m of the same series standard capacitors are the same, and the theoretical capacitance values C w of the single pair of interdigital electrodes are different, so that the theoretical capacitance values C w of the single pair of interdigital electrodes of the same series standard capacitors can be calculated according to the electrode lengths, and then the nominal stepping capacitance values of the same series standard capacitors can be calculated by substituting the theoretical capacitance values C w and the influence coefficients m into a calculation formula (6) of the nominal stepping capacitance values.
And manufacturing an on-chip capacitance standard unit according to the capacitance parameter corresponding to the nominal stepping capacitance value.
Fourth), realizing linear change of standard capacitance value through change of interdigital electrode logarithm
On-chip capacitors with a step value of 10fF in the range of 10fF-100fF were fabricated on BOROFLOAT substrates.
BOROFLOAT 33 is a high quality borosilicate glass with a low coefficient of thermal expansion and a dielectric constant of 4.6. When a capacitor with a larger step value needs to be manufactured, a sapphire (dielectric constant of 11.6) material can be used as a substrate, and when a smaller loss is required, a fused quartz (dielectric constant of 3.4) material can be used as a substrate. Table 1and fig. 9 show the actual measurement values. The test instrument adopts an EB series probe platform, a 73CT-APTA type coaxial probe and an AH2700A multi-frequency capacitance bridge, and the uncertainty of a measurement standard is less than or equal to 0.5 percent C+100aF (C is a capacitance value).
During measurement, a standard capacitance value C of the fly-level capacitance standard sample wafer is calculated by adopting a formula (1):
C=CT-C0; (1)
Wherein, C T represents the total capacitance value of the fly-stage capacitance standard sample, and C 0 represents the capacitance value of the basic capacitance structure.
TABLE 1 actual measurement of 10fF step capacitance
The nominal value of the sample wafer to be measured refers to the nominal value of the capacitance standard cell, and can be said to be the theoretical value of formula 7.
As can be seen from the above test, accurate stepping of the on-chip capacitance fF level can be achieved, and typical deviation of specific capacitance values formed by stepping is less than or equal to + -5%.
The foregoing technical solutions are merely specific embodiments of the present invention, and various modifications and variations can be easily made by those skilled in the art based on the principles disclosed in the present invention, and are not limited to the technical solutions described in the foregoing specific embodiments of the present invention, therefore, the foregoing description is only preferred and not in any limiting sense.
Claims (6)
1. The manufacturing method of the on-chip capacitance standard unit is characterized by being used for manufacturing the on-chip capacitance standard unit with capacitance values of different name and meaning steps, and comprising the following steps:
simulating the on-chip capacitance standard unit under the set stepping capacitance value;
acquiring capacitance parameters of a simulation on-chip capacitance standard unit with corresponding stepping capacitance values;
determining a capacitance parameter range according to the capacitance parameter, and manufacturing real objects of a plurality of on-chip capacitance standard units in the capacitance parameter range;
Measuring the step capacitance value of the real object, and acquiring the capacitance parameter of the real object closest to the set step capacitance value as an optimal capacitance parameter;
Calculating theoretical capacitance value C w of a single pair of interdigital electrodes according to the optimal capacitance parameter, and calculating influence coefficient m between the interdigital electrode pairs according to a calculation formula of a stepping capacitance value, wherein the influence coefficient m between the interdigital electrode pairs is applicable to the same series of standard capacitances, and the same series of standard capacitances are standard capacitances with only different electrode lengths;
Changing the length of the interdigital electrode according to the influence coefficient m between the interdigital electrode pairs to calculate the nominal stepping capacitance value of the same series of standard capacitors;
manufacturing an on-chip capacitance standard unit according to capacitance parameters corresponding to the nominal stepping capacitance value;
the calculation formula of the stepping capacitance value is as follows:
CSp＝2mCw
wherein C Sp represents a nominal step capacitance value;
The standard on-chip capacitance unit comprises a basic capacitance and a standard capacitance, wherein the standard capacitance is obtained by adding the logarithm of an interdigital electrode on the basic capacitance, the standard capacitance value of the standard on-chip capacitance unit is the difference between the capacitance values of the standard capacitance and the basic capacitance, the standard capacitance value is in linear relation with the interdigital electrode logarithm of the standard capacitance under the nominal stepping capacitance value of the standard capacitance, and the nominal stepping capacitance value refers to the capacitance value which is added by adding a pair of interdigital electrodes correspondingly;
the basic capacitor comprises two composite electrodes, each composite electrode comprises a probe contact electrode and interdigital electrodes, the number of the interdigital electrodes is 1, the interdigital electrodes are connected with the probe contact electrodes through connecting wires, the two composite electrodes are oppositely arranged, and the interdigital electrodes are mutually parallel to form an interdigital electrode pair;
the standard capacitor comprises two composite electrodes, each composite electrode comprises a probe contact electrode and interdigital electrodes, the number of the interdigital electrodes is n, n is more than or equal to 2, the interdigital electrodes are arranged at equal intervals and are electrically connected with the probe contact electrodes through the same connecting wire, the two composite electrodes are oppositely arranged, and the interdigital electrodes form n interdigital electrode pairs through mutual insertion of the interdigital electrodes.
2. A method for linear scaling of an on-chip capacitance standard cell, the on-chip capacitance standard cell being fabricated by the method of claim 1, comprising the steps of:
Acquiring a nominal stepping capacitance value of the standard capacitor;
And determining the standard capacitance value of the on-chip capacitance standard unit based on the nominal stepping capacitance value and the interdigital electrode pair number of the standard capacitance, so that the standard capacitance value linearly changes along with the interdigital electrode pair number.
3. The method for linear scaling of standard cells of on-chip capacitance according to claim 2, wherein the nominal step capacitance is calculated as:
CSp＝2mCw
Wherein C Sp represents a nominal stepping capacitance value, C w represents a theoretical capacitance value of a single pair of interdigital electrodes, and m represents an influence coefficient between the interdigital electrode pairs.
4. A method of linear scaling of standard cells of on-chip capacitance according to claim 3, characterized in that the inter-electrode influence coefficient m in the standard capacitance is determined as follows:
simulating the on-chip capacitance standard unit under the set stepping capacitance value;
acquiring capacitance parameters of a simulation on-chip capacitance standard unit with corresponding stepping capacitance values;
determining a capacitance parameter range according to the capacitance parameter, and manufacturing real objects of a plurality of on-chip capacitance standard units in the capacitance parameter range;
Measuring the step capacitance value of the real object, and acquiring the capacitance parameter of the real object closest to the set step capacitance value as an optimal capacitance parameter;
And calculating a theoretical capacitance value C w of the single pair of interdigital electrodes according to the optimal capacitance parameter, and calculating an influence coefficient m between the interdigital electrode pairs according to a calculation formula of the stepping capacitance value.
5. The method for linear scaling of standard cells of on-chip capacitance of claim 4 wherein the standard capacitance is calculated as:
C=CSp(n-1)
Wherein, C represents a standard capacitance value, C Sp represents a nominal stepping capacitance value, n represents the logarithm of interdigital electrodes of the standard capacitance, and n is more than or equal to 2.
6. The method of claim 4, wherein the capacitance parameter comprises a size parameter and a dielectric constant of an interdigital capacitor formed by the interdigital electrode pair, and the capacitance parameter range is determined by setting an upper limit and a lower limit of a length of the interdigital electrode without changing other capacitance parameters.
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