[go: up one dir, main page]

CN101027772A - 在相同工艺流程内被独立访问的双栅和三栅晶体管 - Google Patents

在相同工艺流程内被独立访问的双栅和三栅晶体管 Download PDF

Info

Publication number
CN101027772A
CN101027772A CNA2005800323149A CN200580032314A CN101027772A CN 101027772 A CN101027772 A CN 101027772A CN A2005800323149 A CNA2005800323149 A CN A2005800323149A CN 200580032314 A CN200580032314 A CN 200580032314A CN 101027772 A CN101027772 A CN 101027772A
Authority
CN
China
Prior art keywords
gate
main body
silicon
insulating component
tri
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CNA2005800323149A
Other languages
English (en)
Other versions
CN101027772B (zh
Inventor
B·多伊尔
P·常
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN101027772A publication Critical patent/CN101027772A/zh
Application granted granted Critical
Publication of CN101027772B publication Critical patent/CN101027772B/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/056—Making the transistor the transistor being a FinFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/053—Making the transistor the transistor being at least partially in a trench in the substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/36—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the transistor being a FinFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/017—Manufacture or treatment using dummy gates in processes wherein at least parts of the final gates are self-aligned to the dummy gates, i.e. replacement gate processes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H10D86/011—Manufacture or treatment comprising FinFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI
    • H10D86/215—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI comprising FinFETs

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Thin Film Transistor (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)

Abstract

描述了一种在同一工艺流程中制造的独立访问的双栅和三栅晶体管。一绝缘塞从I－栅器件而不是三栅器件的半导体主体上去除。这例如能够允许金属化以形成在三栅器件的三个侧面上，并允许用于I－栅器件的独立栅极。

Description

在相同工艺流程内被独立访问的双栅和三栅晶体管
发明领域
本发明涉及半导体加工工艺领域。
现有技术和相关领域
半导体加工工艺中一个新近的发展是独立受控的双栅(I-栅)晶体管。该晶体管具有被放置在一沟道的相对两侧的两个栅极，每个栅极都受到独立控制。独立的栅极控制提供了某些独特的晶体管特性，并能够实现例如单体、动态随机存取存储器(DRAM)单元。
半导体加工工艺中的另一个新近的发展是三栅晶体管。此处，在沟道区的三个侧面上各形成一栅极。该晶体管特别是在与高k值绝缘体和金属栅一起使用的情况下，能够大幅改进性能。
现已提出了若干I-栅结构。此种和其他相关技术在如下文献中有所描述：C.Kuo跟随M.Chan发表在1994年1月的Electron Device Letters上之后而在2002年12月在IEDM上发表的；C.Kuo等人发表在2002年12月的IEDM上的“AHypothetical Construction of the Double Gate Floating Body Cell”；T.Ohsawa等人发表在2002年11月的IEEE Journal of Solid-State Circuits.第11期卷37；David M.Fried等人发表在2004年4月的IEEE Electron Device Letters.第4期卷25的“High-Performance P-Type Independent-Gate FinFETs”以及David M.Fried等人发表在2003年9月的IEEE Electron Device Letters.第9期卷24上的“ImprovedIndependent Gate N-Type FinFET Fabrication and Characterization”。
三栅极结构在例如公开号为U.S.2004-0036127-A1的美国专利中有所描述。
附图简述
图1A是包括带有覆盖其上的绝缘构件的两个硅主体的衬底的立体图。
图1B是沿图1A中的线段1B-1B切开的图1的结构的横截面正视图。
图2A示出了图案化牺牲层之后的图1的结构。
图2B是沿图2A中的线段2B-2B切开的图2的结构的横截面正视图。
图3是沉积了层间电介质(ILD)之后的图2A的结构的立体图。
图4A是平坦化之后的图2A的结构的立体图。
图4B是沿图4A中的线段4B-4B切开的横截面正视图。
图5是覆盖了其上制造I-栅晶体管的部分衬底之后的图4的结构的立体图。
图6A是蚀刻步骤之后的图5的结构的立体图。
图6B是沿图6A中的线段6B-6B切开的图6的结构的横截面正视图。
图7A是去除了图案化的牺牲层之后的图6A的结构的立体图。
图7B是沿图7A中的线段7B-7B切开的图7的结构的横截面正视图。
图8是形成了绝缘层和金属层之后的图7A的结构的立体图。
图9A是平坦化金属层之后的图8的结构的立体图。
图9B是去除了ILD的图9A的结构的横截面正视图。
详细描述
在以下描述中记述了一种在公共衬底上被独立访问的双栅(I-栅)晶体管和三栅晶体管的制造。将阐明诸如特定材料等多个具体细节以提供对本发明的透彻理解。本领域普通技术人员显而易见的是无需这些具体细节也能实践本发明。在其他实例中，不会详细描述已知的加工步骤以免淡化本发明的主题。例如，对已知的清洗步骤以及在集成电路制造中经常使用的某些保护层将不作描述。
如下的方法描述了在单个工艺流程中I-栅晶体管和三栅晶体管的同时形成。虽然仅示出了单个I-栅晶体管和单个三栅晶体管的制造，但是本领域普通技术人员显而易见的是在典型的集成电路中可以同时制造多个此类晶体管。此外，可以在集成电路中需要的任何地方制造I-栅和三栅晶体管。于是，诸如缓冲器等单个电路也可以同时具有I-栅和三栅晶体管。在某些情况下，例如在DRAM中，可以制造仅使用I栅晶体管的存储器单元阵列并将其连接至同时使用I-栅和三栅晶体管的外围电路。使用I-栅存储器单元的存储器在由于2004年3月31日提交的题为“Memorywith Split-Gate Devices and Method of Fabrication”且序列号为No.10/816,282的专利申请中有所描述，该申请转让给本发明的受让人。
在一个实施例中，在形成于硅衬底12上的氧化层10上制造晶体管。晶体管主体由放置在层10上的单晶硅层14(如在图1A和1B中的点划线所示)制得。绝缘体上硅(SOI)衬底在半导体行业中是公知的，其中如图所示层14被放置在层10上。例如，SOI衬底可以通过将氧化层10和硅层14粘合在衬底12上，并在随后平坦化层14以使其相对较薄而制成。这一相对较薄的低底(low body)效应层可用于形成上述有源器件主体。用于形成SOI衬底的其他技术包括例如将氧气注入硅衬底以形成掩埋氧化层。在随后的横截面视图中，晶体管被示出在氧化层10上制造，而其下的硅衬底12则未示出。
层14可在要制造n沟道器件的区域中用n型掺杂物来选择性地离子注入，并在要制造p沟道器件的区域中用p型掺杂物来选择性地离子注入。这可用于提供通常可在CMOS集成电路中制造的MOS器件的沟道区中找到的相对较轻的掺杂。I-栅和三栅晶体管可由上述工艺制成p沟道或n沟道器件。(对晶体管沟道区的掺杂可以在诸如图1A或7A所示的工艺流程中的点等工艺流程中的其他点处实现。)
在用于一个实施例的加工工艺中，在沉积了氮化硅层之后在硅层14上放置保护性氧化物(未示出)。对氮化物层进行掩模以定义多个绝缘构件，诸如图1A和图1B中的构件17和18。随后与这些构件对齐地蚀刻其下的硅层14，从而得到硅主体15和16。
硅主体15和16的宽度在具体工艺中可以是临界尺寸，例如在30纳米(nm)栅极长度工艺中，这些主体可以具有30nm的宽度。层14以及形成构件17和18的氮化硅层的厚度例如各自可以位于10-50nm范围之间。
现在，可以在氧化层10上的图1A的结构上沉积一牺牲层。在一个实施例中，该层可以是50-100nm厚的多晶硅层。其他材料也可用于该牺牲层。用于该牺牲层的材料应该能够保护器件的沟道区在如下将描述的源极和漏极区的形成期间免于离子注入。此外，牺牲层应该能够被蚀刻而不损坏在如下将描述的图案化之后围绕牺牲层形成的ILD的完整性。此外，绝缘构件必须能够在有牺牲层存在的情况下被选择性地蚀刻。
接着，牺牲层被图案化为如图2A的构件20和22所示的栅极定义构件。构件20占据了在其中制造用于I-栅晶体管的两个栅极的区域以及允许这些栅极与将在随后示出的栅极相接触的“翅片”。构件22占据了在其中制造用于三栅晶体管的三栅的区域以及同样用于接触的翅片。
在加工工艺的这一点处，可以与构件20和22对齐地蚀刻氮化硅构件17和18，由此露出下面的硅主体15和16的某些部分。如箭头25所示，这些硅主体因未被构件20和22覆盖而被离子注入以形成用于I-栅和三栅晶体管的源极和漏极区。通常会实现但未示出的是，为p沟道和n沟道器件使用分开的离子注入步骤，其中保护层被用于允许用于p沟道和n沟道器件的源极和漏极分开注入。
可选地，氮化硅构件17和18可以保持在原位，而源极和漏极区则以一角度被注入，使得掺杂物进入硅主体15和16的各侧。
此外，可以形成隔片以允许与沟道区相邻地注入的更轻掺杂的源极和漏极区，以及与沟道区隔开的更重掺杂的源极和漏极区。这在以上引用的序列号为10/816,282的申请中有所描述。
现如图3所示在绝缘层10上形成ILD 30。ILD 30围绕构件20和22，并如可以见到的，允许一旦在去除多晶硅之后就进行金属镶嵌。ILD 30例如可以是化学气相沉积(CVD)二氧化硅层。
现在例如可在化学机械抛光(CMP)工艺的条件下平坦化图3的结构以露出氮化硅绝缘构件17和18。这在图4A和4B中都有示出。注意到构件17和18可以与构件20和22一样也与ILD 30的上表面齐平。
现在在图4A和4B的结构上沉积光刻胶层并形成图案以保留在I-栅晶体管区域上的原位。光刻胶层50覆盖绝缘构件17。如图5所示，光刻胶层50让三栅晶体管器件的绝缘构件18得以露出。
随后，如图6A和6B所示，可使用蚀刻工艺来去除塞形氮化硅构件18。使用在氮化硅与ILD 30和牺牲层之间区别对待的蚀刻剂来使ILD 30和构件22保持基本完整。可以使用干法或湿法蚀刻剂。一旦去除了构件18，则如图6B所示露出其下的硅主体16。
接着可以使用例如湿法蚀刻工艺来去除多晶硅牺牲层。所得的结构如图7A和7B所示。剩余的ILD 30现在定义了在其中可以制造用于晶体管的栅极的形状。
从图8中可知，栅介电层60在每个半导体主体15和16之上和周围形成。更具体地，可以沉积栅极电介质以使其覆盖半导体主体16和绝缘构件17的顶面以及每一半导体主体的相对的侧壁。该栅极电介质理想地具有高介电常数，诸如HfO2或ZrO等金属氧化物电介质或者诸如PZT或BST等其他高k电介质。高k介电膜可通过诸如化学汽相沉积(CVD)等任何已知技术形成。另外，栅极电介质可以是生长电介质。在一个实施例中，栅介电层60可以是使用干法/湿法氧化工艺生长的二氧化硅膜。例如，二氧化硅膜可以生长至5至50的厚度。(被保形沉积的介电层如图8所示)。
接着如图8所示，在栅介电层60上形成栅电极(金属)层61。栅电极层61可通过合适的栅电极材料的毯式沉积来形成。在一个实施例中，栅电极材料包括诸如钨、钽、钛和/或其氮化物和合金等金属膜。对于n沟道I-栅和三栅晶体管而言，可以使用范围在4.0至4.6eV的功函数。对于p沟道I-栅和三栅晶体管而言，可以使用范围在4.6至5.2eV的功函数。因此对于带有n沟道和p沟道晶体管的衬底而言，就需要使用两个分开的金属沉积工艺。
金属层61例如可使用CMP来平坦化，并且该平坦化至少持续到如图9A所示露出绝缘构件17的上表面。这样做是为了确保没有金属跨越构件17，因为否则的话I-栅晶体管中的栅极将被一并缩短。从图9中可见，存在用于I-栅晶体管的两个独立栅极62和64以及用于三栅晶体管器件的单个栅极65。
用于三栅晶体管的栅极65具有与底面相对的顶面，并且具有可从图9B中最佳了解的邻近三栅结构形成的相对侧壁。这些侧壁可以连接到硅主体的上表面上。由此，栅极围绕三栅晶体管三侧上的沟道区。对于I-栅晶体管而言，两个独立的栅极62和64由绝缘构件17分隔，而这同样可从ILD被示为已去除的图9B中最佳地了解。
同样可从图9B中最佳地了解，示出了硅主体15和16位于绝缘层10上。沿着漏极区71和72示出了用于每个晶体管的源极区68和70。独立栅极62和64连同其被正交放置的翅片一起可以被很容易地观察到。对于栅极65而言也是一样的。如接触区80、81和82所示，这些翅片允许更容易地形成从覆盖其上的金属化层到栅极的接触。虽然未在图9B中示出，但是可以形成从覆盖其上的金属化层到源极和漏极区以及栅极的接触，尽管该接触未示出。
I-栅晶体管可与三栅晶体管一并用于逻辑电路。I-栅晶体管具有合乎某些电路需要的特性。例如，单个I-栅晶体管可以取决于施加在一个或两个栅极上的电位而提供高电流和中间电流器件。这些器件可以提供“强截止”器件以降低休眠模式或断电模式下的漏电流。I-栅晶体管通过允许滴流(trickle current)还提供用于预充电行的器件。在上述专利申请中，I-栅器件可用作DRAM单元，而上述工艺则可以结合该DRAM制造一并使用。在此情况下，硅主体15是在多个平行且隔开的行内形成的细长体并可在DRAM单元阵列中使用。
虽然在附图中示出了两个分隔的硅主体，但是应该理解也可以使用单个主体。于是就可制造相互串联的三栅和I-栅晶体管。在此情况下，串联的晶体管具有一个源极/漏极区。
以上描述了一种工艺以及所得的用于集成电路的在一公共衬底上同时具有I-栅和三栅结构的结构。

Claims (20)

1.一种方法，包括：
形成具有覆盖其上的绝缘构件的至少两个硅主体；
图案化定义栅极区并与所述硅主体相交的牺牲层；
将所述图案化的牺牲层封入一介电材料；
覆盖所述绝缘构件之一；
去除所述绝缘构件中的另一个；
去除所述图案化的牺牲层；
在所述栅极区内形成绝缘层和金属层。
2.如权利要求1所述的方法，其特征在于，包括平坦化所述介电材料以露出所述绝缘构件。
3.如权利要求2所述的方法，其特征在于，所述硅主体包括单晶硅。
4.如权利要求3所述的方法，其特征在于，所述绝缘构件包括氮化硅。
5.如权利要求4所述的方法，其特征在于，所述牺牲层包括多晶硅。
6.如权利要求5所述的方法，其特征在于，所述平坦化包括化学机械抛光。
7.如权利要求1所述的方法，其特征在于，包括去除所述绝缘构件以达到在所述牺牲层的图案化之后能够被露出的程度。
8.如权利要求1所述的方法，其特征在于，包括在所述牺牲层的图案化之后在所述硅主体内形成源极和漏极区。
9.如权利要求8所述的方法，其特征在于，在两个掺杂过程中完成对所述源极和漏极区的掺杂，一个掺杂过程在侧壁隔片形成之前，而另一个在侧壁隔片形成之后。
10.如权利要求1所述的方法，其特征在于，使用对所述绝缘构件的蚀刻率高于对所述介电材料的蚀刻率的蚀刻剂来完成对所述绝缘构件中的另一个的去除。
11.一种方法，包括：
在绝缘层上定义各自带有第一和第二绝缘构件的第一和第二硅主体；
去除所述第一绝缘构件的至少一部分同时将所述第二绝缘构件保持在原位；
在所述第二硅主体的相对两侧上形成第一栅极结构，所述第一栅极结构具有两个独立的栅极；以及
在所述第二硅主体的三个侧面上形成第二栅极结构。
12.如权利要求11所述的方法，其特征在于，所述第一和第二栅极结构是通过高k绝缘体与它们各自的硅主体绝缘的金属。
13.如权利要求12所述的方法，其特征在于，所述栅极结构是通过去除被层间电介质围绕的牺牲层而形成的。
14.如权利要求13所述的方法，其特征在于，所述牺牲层包括多晶硅，并且所述绝缘构件包括氮化硅。
15.一种集成电路，包括：
衬底；
在所述衬底上并具有第一主体的第一晶体管，所述第一主体在三个侧面上被第一金属栅极围绕；以及
在所述衬底上并具有第二主体的第二晶体管，所述第二主体具有在所述第二主体的相对两侧上的两个独立金属栅极。
16.如权利要求15所述的电路，其特征在于，所述第一和第二主体包括单晶硅。
17.如权利要求16所述的电路，其特征在于，包括放置在所述独立栅极之间的第二主体上的绝缘构件。
18.如权利要求17所述的电路，其特征在于，所述绝缘构件包括氮化硅。
19.如权利要求15所述的电路，其特征在于，包括多个所述第一和第二晶体管，所述晶体管中的某一些是n沟道晶体管，而其他是p沟道晶体管。
20.如权利要求19所述的电路，其特征在于，所述晶体管的主体包括单晶硅。
CN2005800323149A 2004-09-29 2005-09-29 在相同工艺流程内被独立访问的双栅和三栅晶体管及其制造方法 Expired - Fee Related CN101027772B (zh)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US10/955,670 2004-09-29
US10/955,670 US7422946B2 (en) 2004-09-29 2004-09-29 Independently accessed double-gate and tri-gate transistors in same process flow
PCT/US2005/035380 WO2006039600A1 (en) 2004-09-29 2005-09-29 Independently accessed double-gate and tri-gate transistors in same process flow

Publications (2)

Publication Number Publication Date
CN101027772A true CN101027772A (zh) 2007-08-29
CN101027772B CN101027772B (zh) 2011-01-12

Family

ID=35645730

Family Applications (1)

Application Number Title Priority Date Filing Date
CN2005800323149A Expired - Fee Related CN101027772B (zh) 2004-09-29 2005-09-29 在相同工艺流程内被独立访问的双栅和三栅晶体管及其制造方法

Country Status (6)

Country Link
US (5) US7422946B2 (zh)
KR (1) KR100900831B1 (zh)
CN (1) CN101027772B (zh)
DE (1) DE112005002428B4 (zh)
TW (1) TWI287867B (zh)
WO (1) WO2006039600A1 (zh)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103839810A (zh) * 2012-11-21 2014-06-04 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管芯片及其制造方法
CN103928348A (zh) * 2014-04-28 2014-07-16 上海华力微电子有限公司 双栅极的分离方法
CN103928349A (zh) * 2014-04-28 2014-07-16 上海华力微电子有限公司 鳍式场效晶体管中栅极的分离方法
CN103943484A (zh) * 2014-04-28 2014-07-23 上海华力微电子有限公司 自对准的栅极分离方法
CN103972103A (zh) * 2014-04-28 2014-08-06 上海华力微电子有限公司 增加光刻对准的栅极分离方法
WO2015143697A1 (zh) * 2014-03-28 2015-10-01 江苏宏微科技股份有限公司 一种双栅mos结构的功率晶体管及其制作方法
CN106504983A (zh) * 2015-09-06 2017-03-15 中国科学院微电子研究所 半导体器件制造方法

Families Citing this family (103)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7087506B2 (en) * 2003-06-26 2006-08-08 International Business Machines Corporation Method of forming freestanding semiconductor layer
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US7456476B2 (en) 2003-06-27 2008-11-25 Intel Corporation Nonplanar semiconductor device with partially or fully wrapped around gate electrode and methods of fabrication
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US7253650B2 (en) * 2004-05-25 2007-08-07 International Business Machines Corporation Increase productivity at wafer test using probe retest data analysis
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7361958B2 (en) * 2004-09-30 2008-04-22 Intel Corporation Nonplanar transistors with metal gate electrodes
US7212432B2 (en) * 2004-09-30 2007-05-01 Infineon Technologies Ag Resistive memory cell random access memory device and method of fabrication
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
US20060202266A1 (en) 2005-03-14 2006-09-14 Marko Radosavljevic Field effect transistor with metal source/drain regions
US7858481B2 (en) * 2005-06-15 2010-12-28 Intel Corporation Method for fabricating transistor with thinned channel
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US7402875B2 (en) 2005-08-17 2008-07-22 Intel Corporation Lateral undercut of metal gate in SOI device
US7606066B2 (en) 2005-09-07 2009-10-20 Innovative Silicon Isi Sa Memory cell and memory cell array having an electrically floating body transistor, and methods of operating same
US20070090416A1 (en) 2005-09-28 2007-04-26 Doyle Brian S CMOS devices with a single work function gate electrode and method of fabrication
US7479421B2 (en) 2005-09-28 2009-01-20 Intel Corporation Process for integrating planar and non-planar CMOS transistors on a bulk substrate and article made thereby
US7341916B2 (en) * 2005-11-10 2008-03-11 Atmel Corporation Self-aligned nanometer-level transistor defined without lithography
US7485503B2 (en) 2005-11-30 2009-02-03 Intel Corporation Dielectric interface for group III-V semiconductor device
US7439588B2 (en) * 2005-12-13 2008-10-21 Intel Corporation Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate
US7495290B2 (en) 2005-12-14 2009-02-24 Infineon Technologies Ag Semiconductor devices and methods of manufacture thereof
US20070152266A1 (en) * 2005-12-29 2007-07-05 Intel Corporation Method and structure for reducing the external resistance of a three-dimensional transistor through use of epitaxial layers
US7301210B2 (en) * 2006-01-12 2007-11-27 International Business Machines Corporation Method and structure to process thick and thin fins and variable fin to fin spacing
US20070232002A1 (en) * 2006-03-29 2007-10-04 Chang Peter L D Static random access memory using independent double gate transistors
US7492632B2 (en) 2006-04-07 2009-02-17 Innovative Silicon Isi Sa Memory array having a programmable word length, and method of operating same
US7933142B2 (en) 2006-05-02 2011-04-26 Micron Technology, Inc. Semiconductor memory cell and array using punch-through to program and read same
US7670928B2 (en) * 2006-06-14 2010-03-02 Intel Corporation Ultra-thin oxide bonding for S1 to S1 dual orientation bonding
US8069377B2 (en) 2006-06-26 2011-11-29 Micron Technology, Inc. Integrated circuit having memory array including ECC and column redundancy and method of operating the same
US7542340B2 (en) 2006-07-11 2009-06-02 Innovative Silicon Isi Sa Integrated circuit including memory array having a segmented bit line architecture and method of controlling and/or operating same
WO2008007331A2 (en) * 2006-07-11 2008-01-17 Nxp B.V. Semiconductor devices and methods of manufacture thereof
US8143646B2 (en) 2006-08-02 2012-03-27 Intel Corporation Stacking fault and twin blocking barrier for integrating III-V on Si
US20080029827A1 (en) * 2006-08-04 2008-02-07 Ibrahim Ban Double gate transistor, method of manufacturing same, and system containing same
US8264041B2 (en) 2007-01-26 2012-09-11 Micron Technology, Inc. Semiconductor device with electrically floating body
WO2009031052A2 (en) * 2007-03-29 2009-03-12 Innovative Silicon S.A. Zero-capacitor (floating body) random access memory circuits with polycide word lines and manufacturing methods therefor
US8064274B2 (en) 2007-05-30 2011-11-22 Micron Technology, Inc. Integrated circuit having voltage generation circuitry for memory cell array, and method of operating and/or controlling same
US8085594B2 (en) 2007-06-01 2011-12-27 Micron Technology, Inc. Reading technique for memory cell with electrically floating body transistor
US7859044B2 (en) * 2007-07-24 2010-12-28 International Business Machines Corporation Partially gated FINFET with gate dielectric on only one sidewall
US8194487B2 (en) * 2007-09-17 2012-06-05 Micron Technology, Inc. Refreshing data of memory cells with electrically floating body transistors
US20090108351A1 (en) * 2007-10-26 2009-04-30 International Business Machines Corporation Finfet memory device with dual separate gates and method of operation
US8536628B2 (en) 2007-11-29 2013-09-17 Micron Technology, Inc. Integrated circuit having memory cell array including barriers, and method of manufacturing same
EP2070533B1 (en) * 2007-12-11 2014-05-07 Apoteknos Para La Piel, s.l. Use of a compound derived from P-hydroxyphenyl propionic acid for the treatment of psoriasis
US8349662B2 (en) 2007-12-11 2013-01-08 Micron Technology, Inc. Integrated circuit having memory cell array, and method of manufacturing same
US8773933B2 (en) 2012-03-16 2014-07-08 Micron Technology, Inc. Techniques for accessing memory cells
US8014195B2 (en) 2008-02-06 2011-09-06 Micron Technology, Inc. Single transistor memory cell
US8189376B2 (en) 2008-02-08 2012-05-29 Micron Technology, Inc. Integrated circuit having memory cells including gate material having high work function, and method of manufacturing same
US20090206405A1 (en) * 2008-02-15 2009-08-20 Doyle Brian S Fin field effect transistor structures having two dielectric thicknesses
US7957206B2 (en) 2008-04-04 2011-06-07 Micron Technology, Inc. Read circuitry for an integrated circuit having memory cells and/or a memory cell array, and method of operating same
US7800166B2 (en) * 2008-05-30 2010-09-21 Intel Corporation Recessed channel array transistor (RCAT) structures and method of formation
US8362566B2 (en) 2008-06-23 2013-01-29 Intel Corporation Stress in trigate devices using complimentary gate fill materials
US7781283B2 (en) * 2008-08-15 2010-08-24 International Business Machines Corporation Split-gate DRAM with MuGFET, design structure, and method of manufacture
US7979836B2 (en) * 2008-08-15 2011-07-12 International Business Machines Corporation Split-gate DRAM with MuGFET, design structure, and method of manufacture
US7947543B2 (en) 2008-09-25 2011-05-24 Micron Technology, Inc. Recessed gate silicon-on-insulator floating body device with self-aligned lateral isolation
US7933140B2 (en) * 2008-10-02 2011-04-26 Micron Technology, Inc. Techniques for reducing a voltage swing
US7924630B2 (en) 2008-10-15 2011-04-12 Micron Technology, Inc. Techniques for simultaneously driving a plurality of source lines
US8223574B2 (en) 2008-11-05 2012-07-17 Micron Technology, Inc. Techniques for block refreshing a semiconductor memory device
US7888192B2 (en) * 2008-11-10 2011-02-15 Texas Instruments Incorporated Process for forming integrated circuits with both split gate and common gate FinFET transistors
US8213226B2 (en) 2008-12-05 2012-07-03 Micron Technology, Inc. Vertical transistor memory cell and array
US8319294B2 (en) 2009-02-18 2012-11-27 Micron Technology, Inc. Techniques for providing a source line plane
US8710566B2 (en) * 2009-03-04 2014-04-29 Micron Technology, Inc. Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device
US8184472B2 (en) * 2009-03-13 2012-05-22 International Business Machines Corporation Split-gate DRAM with lateral control-gate MuGFET
US8748959B2 (en) 2009-03-31 2014-06-10 Micron Technology, Inc. Semiconductor memory device
US8139418B2 (en) 2009-04-27 2012-03-20 Micron Technology, Inc. Techniques for controlling a direct injection semiconductor memory device
US8508994B2 (en) 2009-04-30 2013-08-13 Micron Technology, Inc. Semiconductor device with floating gate and electrically floating body
US8498157B2 (en) 2009-05-22 2013-07-30 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8053318B2 (en) * 2009-06-25 2011-11-08 International Business Machines Corporation FET with replacement gate structure and method of fabricating the same
US8537610B2 (en) 2009-07-10 2013-09-17 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9076543B2 (en) 2009-07-27 2015-07-07 Micron Technology, Inc. Techniques for providing a direct injection semiconductor memory device
US8199595B2 (en) 2009-09-04 2012-06-12 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US8174881B2 (en) 2009-11-24 2012-05-08 Micron Technology, Inc. Techniques for reducing disturbance in a semiconductor device
US9420770B2 (en) 2009-12-01 2016-08-23 Indiana University Research & Technology Corporation Methods of modulating thrombocytopenia and modified transgenic pigs
US8310893B2 (en) 2009-12-16 2012-11-13 Micron Technology, Inc. Techniques for reducing impact of array disturbs in a semiconductor memory device
CN102122645B (zh) 2010-01-08 2014-03-12 中芯国际集成电路制造(上海)有限公司 集成电路结构、其制造方法和使用方法
US9922878B2 (en) 2010-01-08 2018-03-20 Semiconductor Manufacturing International (Shanghai) Corporation Hybrid integrated semiconductor tri-gate and split dual-gate FinFET devices and method for manufacturing
US8416636B2 (en) 2010-02-12 2013-04-09 Micron Technology, Inc. Techniques for controlling a semiconductor memory device
US8576631B2 (en) 2010-03-04 2013-11-05 Micron Technology, Inc. Techniques for sensing a semiconductor memory device
US8411513B2 (en) 2010-03-04 2013-04-02 Micron Technology, Inc. Techniques for providing a semiconductor memory device having hierarchical bit lines
US8369177B2 (en) 2010-03-05 2013-02-05 Micron Technology, Inc. Techniques for reading from and/or writing to a semiconductor memory device
EP2548227B1 (en) 2010-03-15 2021-07-14 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US8411524B2 (en) 2010-05-06 2013-04-02 Micron Technology, Inc. Techniques for refreshing a semiconductor memory device
US9214529B2 (en) 2011-03-14 2015-12-15 Globalfoundries Inc. Fin Fet device with independent control gate
US8531878B2 (en) 2011-05-17 2013-09-10 Micron Technology, Inc. Techniques for providing a semiconductor memory device
US9559216B2 (en) 2011-06-06 2017-01-31 Micron Technology, Inc. Semiconductor memory device and method for biasing same
US8426283B1 (en) 2011-11-10 2013-04-23 United Microelectronics Corp. Method of fabricating a double-gate transistor and a tri-gate transistor on a common substrate
US20130173214A1 (en) * 2012-01-04 2013-07-04 International Business Machines Corporation Method and structure for inline electrical fin critical dimension measurement
JP5398853B2 (ja) * 2012-01-26 2014-01-29 東京エレクトロン株式会社 プラズマ処理方法及びプラズマ処理装置
US8877623B2 (en) 2012-05-14 2014-11-04 United Microelectronics Corp. Method of forming semiconductor device
US8716751B2 (en) 2012-09-28 2014-05-06 Intel Corporation Methods of containing defects for non-silicon device engineering
US8716094B1 (en) * 2012-11-21 2014-05-06 Global Foundries Inc. FinFET formation using double patterning memorization
JP6018607B2 (ja) 2013-07-12 2016-11-02 株式会社半導体エネルギー研究所 半導体装置
DE102014220672A1 (de) 2013-10-22 2015-05-07 Semiconductor Energy Laboratory Co., Ltd. Halbleitervorrichtung
US9093387B1 (en) 2014-01-08 2015-07-28 International Business Machines Corporation Metallic mask patterning process for minimizing collateral etch of an underlayer
US20150214331A1 (en) * 2014-01-30 2015-07-30 Globalfoundries Inc. Replacement metal gate including dielectric gate material
KR102217246B1 (ko) 2014-11-12 2021-02-18 삼성전자주식회사 집적회로 소자 및 그 제조 방법
KR102290793B1 (ko) 2014-12-18 2021-08-19 삼성전자주식회사 반도체 장치, 반도체 장치의 패턴 형성 방법 및 반도체 장치의 제조 방법
US10153355B2 (en) * 2015-12-04 2018-12-11 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor mixed gate structure
US9536789B1 (en) 2016-01-27 2017-01-03 International Business Mashines Corporation Fin-double-gated junction field effect transistor
US10497576B1 (en) * 2018-08-20 2019-12-03 Globalfoundries Inc. Devices with slotted active regions
US12080561B2 (en) * 2022-01-26 2024-09-03 Nanya Technology Corporation Method of processing substrate
TWI803299B (zh) * 2022-01-26 2023-05-21 南亞科技股份有限公司 基板的處理方法
US12034034B2 (en) 2022-01-26 2024-07-09 Nanya Technology Corporation Method of manufacturing capacitor array

Family Cites Families (426)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US81794A (en) * 1868-09-01 Improved machine for separating ores
US167007A (en) * 1875-08-24 Improvement in farm-fences
US647869A (en) * 1898-07-05 1900-04-17 Nat Tube Co Furnace-charging apparatus.
US3387820A (en) 1965-05-24 1968-06-11 Continental Aviat & Engineerin Turbine engine construction
US4231149A (en) 1978-10-10 1980-11-04 Texas Instruments Incorporated Narrow band-gap semiconductor CCD imaging device and method of fabrication
JPS5673454A (en) 1979-11-21 1981-06-18 Sumitomo Metal Mining Co Ltd Manufacture of stepped semiconductor substrate
JPS59145538A (ja) 1983-10-21 1984-08-21 Hitachi Ltd 半導体装置の製造方法
GB2156149A (en) 1984-03-14 1985-10-02 Philips Electronic Associated Dielectrically-isolated integrated circuit manufacture
US4487652A (en) 1984-03-30 1984-12-11 Motorola, Inc. Slope etch of polyimide
US4711701A (en) 1986-09-16 1987-12-08 Texas Instruments Incorporated Self-aligned transistor method
US5514885A (en) 1986-10-09 1996-05-07 Myrick; James J. SOI methods and apparatus
US4818715A (en) * 1987-07-09 1989-04-04 Industrial Technology Research Institute Method of fabricating a LDDFET with self-aligned silicide
US4907048A (en) * 1987-11-23 1990-03-06 Xerox Corporation Double implanted LDD transistor self-aligned with gate
US4905063A (en) * 1988-06-21 1990-02-27 American Telephone And Telegraph Company, At&T Bell Laboratories Floating gate memories
JPH0214578A (ja) 1988-07-01 1990-01-18 Fujitsu Ltd 半導体装置
KR910010043B1 (ko) 1988-07-28 1991-12-10 한국전기통신공사 스페이서를 이용한 미세선폭 형성방법
US4994873A (en) * 1988-10-17 1991-02-19 Motorola, Inc. Local interconnect for stacked polysilicon device
US5346834A (en) 1988-11-21 1994-09-13 Hitachi, Ltd. Method for manufacturing a semiconductor device and a semiconductor memory device
US4906589A (en) * 1989-02-06 1990-03-06 Industrial Technology Research Institute Inverse-T LDDFET with self-aligned silicide
US5278012A (en) * 1989-03-29 1994-01-11 Hitachi, Ltd. Method for producing thin film multilayer substrate, and method and apparatus for detecting circuit conductor pattern of the substrate
JPH02302044A (ja) 1989-05-16 1990-12-14 Fujitsu Ltd 半導体装置の製造方法
US5328810A (en) 1990-05-07 1994-07-12 Micron Technology, Inc. Method for reducing, by a factor or 2-N, the minimum masking pitch of a photolithographic process
KR930003790B1 (ko) * 1990-07-02 1993-05-10 삼성전자 주식회사 반도체 장치의 캐패시터용 유전체
JP3061406B2 (ja) 1990-09-28 2000-07-10 株式会社東芝 半導体装置
JP3202223B2 (ja) * 1990-11-27 2001-08-27 日本電気株式会社 トランジスタの製造方法
US5218213A (en) 1991-02-22 1993-06-08 Harris Corporation SOI wafer with sige
US5521859A (en) 1991-03-20 1996-05-28 Fujitsu Limited Semiconductor memory device having thin film transistor and method of producing the same
JPH05152293A (ja) * 1991-04-30 1993-06-18 Sgs Thomson Microelectron Inc 段差付き壁相互接続体及びゲートの製造方法
US5346836A (en) 1991-06-06 1994-09-13 Micron Technology, Inc. Process for forming low resistance contacts between silicide areas and upper level polysilicon interconnects
US5292670A (en) 1991-06-10 1994-03-08 Texas Instruments Incorporated Sidewall doping technique for SOI transistors
US5179037A (en) * 1991-12-24 1993-01-12 Texas Instruments Incorporated Integration of lateral and vertical quantum well transistors in the same epitaxial stack
US5391506A (en) 1992-01-31 1995-02-21 Kawasaki Steel Corporation Manufacturing method for semiconductor devices with source/drain formed in substrate projection.
JPH05243572A (ja) 1992-02-27 1993-09-21 Fujitsu Ltd 半導体装置
US5405454A (en) 1992-03-19 1995-04-11 Matsushita Electric Industrial Co., Ltd. Electrically insulated silicon structure and producing method therefor
JP2572003B2 (ja) * 1992-03-30 1997-01-16 三星電子株式会社 三次元マルチチャンネル構造を有する薄膜トランジスタの製造方法
JPH0793441B2 (ja) 1992-04-24 1995-10-09 ヒュンダイ エレクトロニクス インダストリーズ カンパニー リミテッド 薄膜トランジスタ及びその製造方法
KR960002088B1 (ko) * 1993-02-17 1996-02-10 삼성전자주식회사 에스오아이(SOI : silicon on insulator) 구조의 반도체 장치 제조방법
US5357119A (en) 1993-02-19 1994-10-18 Board Of Regents Of The University Of California Field effect devices having short period superlattice structures using Si and Ge
JPH06310547A (ja) 1993-02-25 1994-11-04 Mitsubishi Electric Corp 半導体装置及びその製造方法
EP0623963A1 (de) 1993-05-06 1994-11-09 Siemens Aktiengesellschaft MOSFET auf SOI-Substrat
US5739544A (en) 1993-05-26 1998-04-14 Matsushita Electric Industrial Co., Ltd. Quantization functional device utilizing a resonance tunneling effect and method for producing the same
GB2282736B (en) 1993-05-28 1996-12-11 Nec Corp Radio base station for a mobile communications system
US6730549B1 (en) * 1993-06-25 2004-05-04 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method for its preparation
JP3778581B2 (ja) 1993-07-05 2006-05-24 三菱電機株式会社 半導体装置およびその製造方法
JP3460863B2 (ja) 1993-09-17 2003-10-27 三菱電機株式会社 半導体装置の製造方法
US5479033A (en) 1994-05-27 1995-12-26 Sandia Corporation Complementary junction heterostructure field-effect transistor
JP3361922B2 (ja) 1994-09-13 2003-01-07 株式会社東芝 半導体装置
JP3378414B2 (ja) 1994-09-14 2003-02-17 株式会社東芝 半導体装置
US5497019A (en) * 1994-09-22 1996-03-05 The Aerospace Corporation Silicon-on-insulator gate-all-around MOSFET devices and fabrication methods
JPH08153880A (ja) * 1994-09-29 1996-06-11 Toshiba Corp 半導体装置及びその製造方法
US5602049A (en) 1994-10-04 1997-02-11 United Microelectronics Corporation Method of fabricating a buried structure SRAM cell
JPH08125152A (ja) * 1994-10-28 1996-05-17 Canon Inc 半導体装置、それを用いた相関演算装置、ａｄ変換器、ｄａ変換器、信号処理システム
US5576227A (en) 1994-11-02 1996-11-19 United Microelectronics Corp. Process for fabricating a recessed gate MOS device
JP3078720B2 (ja) 1994-11-02 2000-08-21 三菱電機株式会社 半導体装置およびその製造方法
GB2295488B (en) 1994-11-24 1996-11-20 Toshiba Cambridge Res Center Semiconductor device
US5716879A (en) * 1994-12-15 1998-02-10 Goldstar Electron Company, Ltd. Method of making a thin film transistor
US5539229A (en) 1994-12-28 1996-07-23 International Business Machines Corporation MOSFET with raised STI isolation self-aligned to the gate stack
JPH08204191A (ja) 1995-01-20 1996-08-09 Sony Corp 電界効果トランジスタ及びその製造方法
US5665203A (en) 1995-04-28 1997-09-09 International Business Machines Corporation Silicon etching method
JP3303601B2 (ja) 1995-05-19 2002-07-22 日産自動車株式会社 溝型半導体装置
KR0165398B1 (ko) 1995-05-26 1998-12-15 윤종용 버티칼 트랜지스터의 제조방법
US5658806A (en) * 1995-10-26 1997-08-19 National Science Council Method for fabricating thin-film transistor with bottom-gate or dual-gate configuration
US5814895A (en) 1995-12-22 1998-09-29 Sony Corporation Static random access memory having transistor elements formed on side walls of a trench in a semiconductor substrate
KR100205442B1 (ko) 1995-12-26 1999-07-01 구본준 박막트랜지스터 및 그의 제조방법
US5595919A (en) * 1996-02-20 1997-01-21 Chartered Semiconductor Manufacturing Pte Ltd. Method of making self-aligned halo process for reducing junction capacitance
DE19607209A1 (de) 1996-02-26 1997-08-28 Gregor Kohlruss Reinigungsvorrichtung zum Reinigen von flächigen Gegenständen
JPH09293793A (ja) 1996-04-26 1997-11-11 Mitsubishi Electric Corp 薄膜トランジスタを有する半導体装置およびその製造方法
US5793088A (en) 1996-06-18 1998-08-11 Integrated Device Technology, Inc. Structure for controlling threshold voltage of MOSFET
JP3710880B2 (ja) * 1996-06-28 2005-10-26 株式会社東芝 不揮発性半導体記憶装置
TW548686B (en) * 1996-07-11 2003-08-21 Semiconductor Energy Lab CMOS semiconductor device and apparatus using the same
US5817560A (en) * 1996-09-12 1998-10-06 Advanced Micro Devices, Inc. Ultra short trench transistors and process for making same
US6399970B2 (en) * 1996-09-17 2002-06-04 Matsushita Electric Industrial Co., Ltd. FET having a Si/SiGeC heterojunction channel
US6063675A (en) 1996-10-28 2000-05-16 Texas Instruments Incorporated Method of forming a MOSFET using a disposable gate with a sidewall dielectric
US6163053A (en) 1996-11-06 2000-12-19 Ricoh Company, Ltd. Semiconductor device having opposite-polarity region under channel
US5827769A (en) 1996-11-20 1998-10-27 Intel Corporation Method for fabricating a transistor with increased hot carrier resistance by nitridizing and annealing the sidewall oxide of the gate electrode
JPH10150185A (ja) * 1996-11-20 1998-06-02 Mitsubishi Electric Corp 半導体装置及びその製造方法
US5773331A (en) 1996-12-17 1998-06-30 International Business Machines Corporation Method for making single and double gate field effect transistors with sidewall source-drain contacts
US5908313A (en) * 1996-12-31 1999-06-01 Intel Corporation Method of forming a transistor
JP4086926B2 (ja) 1997-01-29 2008-05-14 富士通株式会社 半導体装置及びその製造方法
JPH118390A (ja) 1997-06-18 1999-01-12 Mitsubishi Electric Corp 半導体装置及びその製造方法
US6251763B1 (en) * 1997-06-30 2001-06-26 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing same
US6054355A (en) * 1997-06-30 2000-04-25 Kabushiki Kaisha Toshiba Method of manufacturing a semiconductor device which includes forming a dummy gate
JPH1140811A (ja) 1997-07-22 1999-02-12 Hitachi Ltd 半導体装置およびその製造方法
US5952701A (en) 1997-08-18 1999-09-14 National Semiconductor Corporation Design and fabrication of semiconductor structure having complementary channel-junction insulated-gate field-effect transistors whose gate electrodes have work functions close to mid-gap semiconductor value
US5776821A (en) 1997-08-22 1998-07-07 Vlsi Technology, Inc. Method for forming a reduced width gate electrode
US6066869A (en) 1997-10-06 2000-05-23 Micron Technology, Inc. Circuit and method for a folded bit line memory cell with vertical transistor and trench capacitor
US5976767A (en) 1997-10-09 1999-11-02 Micron Technology, Inc. Ammonium hydroxide etch of photoresist masked silicon
US5963817A (en) 1997-10-16 1999-10-05 International Business Machines Corporation Bulk and strained silicon on insulator using local selective oxidation
US5856225A (en) * 1997-11-24 1999-01-05 Chartered Semiconductor Manufacturing Ltd Creation of a self-aligned, ion implanted channel region, after source and drain formation
US6120846A (en) 1997-12-23 2000-09-19 Advanced Technology Materials, Inc. Method for the selective deposition of bismuth based ferroelectric thin films by chemical vapor deposition
US5888309A (en) * 1997-12-29 1999-03-30 Taiwan Semiconductor Manufacturing Company, Ltd. Lateral etch inhibited multiple for forming a via through a microelectronics layer susceptible to etching within a fluorine containing plasma followed by an oxygen containing plasma
US6117741A (en) * 1998-01-09 2000-09-12 Texas Instruments Incorporated Method of forming a transistor having an improved sidewall gate structure
US6351040B1 (en) * 1998-01-22 2002-02-26 Micron Technology, Inc. Method and apparatus for implementing selected functionality on an integrated circuit device
US6294416B1 (en) 1998-01-23 2001-09-25 Texas Instruments-Acer Incorporated Method of fabricating CMOS transistors with self-aligned planarization twin-well by using fewer mask counts
US6307235B1 (en) 1998-03-30 2001-10-23 Micron Technology, Inc. Another technique for gated lateral bipolar transistors
US6097065A (en) * 1998-03-30 2000-08-01 Micron Technology, Inc. Circuits and methods for dual-gated transistors
US6087208A (en) * 1998-03-31 2000-07-11 Advanced Micro Devices, Inc. Method for increasing gate capacitance by using both high and low dielectric gate material
JP4208331B2 (ja) * 1998-04-24 2009-01-14 東レ株式会社 抗菌性繊維構造物およびその製造方法
US6215190B1 (en) * 1998-05-12 2001-04-10 International Business Machines Corporation Borderless contact to diffusion with respect to gate conductor and methods for fabricating
US6232641B1 (en) * 1998-05-29 2001-05-15 Kabushiki Kaisha Toshiba Semiconductor apparatus having elevated source and drain structure and manufacturing method therefor
US6114201A (en) 1998-06-01 2000-09-05 Texas Instruments-Acer Incorporated Method of manufacturing a multiple fin-shaped capacitor for high density DRAMs
US20010040907A1 (en) 1998-06-12 2001-11-15 Utpal Kumar Chakrabarti Optical device including carbon-doped contact layers
US6165880A (en) 1998-06-15 2000-12-26 Taiwan Semiconductor Manufacturing Company Double spacer technology for making self-aligned contacts (SAC) on semiconductor integrated circuits
US6130123A (en) 1998-06-30 2000-10-10 Intel Corporation Method for making a complementary metal gate electrode technology
JP2000037842A (ja) 1998-07-27 2000-02-08 Dainippon Printing Co Ltd 電磁波吸収化粧材
US6696366B1 (en) * 1998-08-17 2004-02-24 Lam Research Corporation Technique for etching a low capacitance dielectric layer
JP2000156502A (ja) 1998-09-21 2000-06-06 Texas Instr Inc <Ti> 集積回路及び方法
US6114206A (en) 1998-11-06 2000-09-05 Advanced Micro Devices, Inc. Multiple threshold voltage transistor implemented by a damascene process
US6262456B1 (en) 1998-11-06 2001-07-17 Advanced Micro Devices, Inc. Integrated circuit having transistors with different threshold voltages
US5985726A (en) 1998-11-06 1999-11-16 Advanced Micro Devices, Inc. Damascene process for forming ultra-shallow source/drain extensions and pocket in ULSI MOSFET
US6153485A (en) 1998-11-09 2000-11-28 Chartered Semiconductor Manufacturing Ltd. Salicide formation on narrow poly lines by pulling back of spacer
US6200865B1 (en) * 1998-12-04 2001-03-13 Advanced Micro Devices, Inc. Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate
US6362111B1 (en) * 1998-12-09 2002-03-26 Texas Instruments Incorporated Tunable gate linewidth reduction process
TW406312B (en) 1998-12-18 2000-09-21 United Microelectronics Corp The method of etching doped poly-silicon
TW449919B (en) 1998-12-18 2001-08-11 Koninkl Philips Electronics Nv A method of manufacturing a semiconductor device
US6380558B1 (en) 1998-12-29 2002-04-30 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and method of fabricating the same
US6150222A (en) 1999-01-07 2000-11-21 Advanced Micro Devices, Inc. Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions
FR2788629B1 (fr) 1999-01-15 2003-06-20 Commissariat Energie Atomique Transistor mis et procede de fabrication d'un tel transistor sur un substrat semiconducteur
US6174820B1 (en) * 1999-02-16 2001-01-16 Sandia Corporation Use of silicon oxynitride as a sacrificial material for microelectromechanical devices
JP2000243854A (ja) 1999-02-22 2000-09-08 Toshiba Corp 半導体装置及びその製造方法
KR100720842B1 (ko) 1999-03-26 2007-05-25 코닌클리케 필립스 일렉트로닉스 엔.브이. 비디오 코딩 방법 및 대응 비디오 코더
US6093621A (en) * 1999-04-05 2000-07-25 Vanguard International Semiconductor Corp. Method of forming shallow trench isolation
US7045468B2 (en) * 1999-04-09 2006-05-16 Intel Corporation Isolated junction structure and method of manufacture
US6459123B1 (en) 1999-04-30 2002-10-01 Infineon Technologies Richmond, Lp Double gated transistor
DE60001601T2 (de) * 1999-06-18 2003-12-18 Lucent Technologies Inc., Murray Hill Fertigungsverfahren zur Herstellung eines CMOS integrieten Schaltkreises mit vertikalen Transistoren
JP2001015704A (ja) 1999-06-29 2001-01-19 Hitachi Ltd 半導体集積回路
US6218309B1 (en) * 1999-06-30 2001-04-17 Lam Research Corporation Method of achieving top rounding and uniform etch depths while etching shallow trench isolation features
US6501131B1 (en) 1999-07-22 2002-12-31 International Business Machines Corporation Transistors having independently adjustable parameters
TW432594B (en) * 1999-07-31 2001-05-01 Taiwan Semiconductor Mfg Manufacturing method for shallow trench isolation
US6259135B1 (en) 1999-09-24 2001-07-10 International Business Machines Corporation MOS transistors structure for reducing the size of pitch limited circuits
FR2799305B1 (fr) 1999-10-05 2004-06-18 St Microelectronics Sa Procede de fabrication d'un dispositif semi-conducteur a grille enveloppante et dispositif obtenu
EP1091413A3 (en) 1999-10-06 2005-01-12 Lsi Logic Corporation Fully-depleted, fully-inverted, short-length and vertical channel, dual-gate, cmos fet
US6159808A (en) * 1999-11-12 2000-12-12 United Semiconductor Corp. Method of forming self-aligned DRAM cell
US6897009B2 (en) 1999-11-29 2005-05-24 Trustees Of The University Of Pennsylvania Fabrication of nanometer size gaps on an electrode
US6150670A (en) 1999-11-30 2000-11-21 International Business Machines Corporation Process for fabricating a uniform gate oxide of a vertical transistor
US6541829B2 (en) * 1999-12-03 2003-04-01 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6252284B1 (en) * 1999-12-09 2001-06-26 International Business Machines Corporation Planarized silicon fin device
KR100311049B1 (ko) 1999-12-13 2001-10-12 윤종용 불휘발성 반도체 메모리장치 및 그의 제조방법
US6303479B1 (en) 1999-12-16 2001-10-16 Spinnaker Semiconductor, Inc. Method of manufacturing a short-channel FET with Schottky-barrier source and drain contacts
JP4923318B2 (ja) 1999-12-17 2012-04-25 ソニー株式会社 不揮発性半導体記憶装置およびその動作方法
JP4194237B2 (ja) * 1999-12-28 2008-12-10 株式会社リコー 電界効果トランジスタを用いた電圧発生回路及び基準電圧源回路
US7391087B2 (en) 1999-12-30 2008-06-24 Intel Corporation MOS transistor structure and method of fabrication
JP3613113B2 (ja) 2000-01-21 2005-01-26 日本電気株式会社 半導体装置およびその製造方法
US6319807B1 (en) 2000-02-07 2001-11-20 United Microelectronics Corp. Method for forming a semiconductor device by using reverse-offset spacer process
JP3846706B2 (ja) * 2000-02-23 2006-11-15 信越半導体株式会社 ウエーハ外周面取部の研磨方法及び研磨装置
US6483156B1 (en) 2000-03-16 2002-11-19 International Business Machines Corporation Double planar gated SOI MOSFET structure
FR2806832B1 (fr) 2000-03-22 2002-10-25 Commissariat Energie Atomique Transistor mos a source et drain metalliques, et procede de fabrication d'un tel transistor
JP3906005B2 (ja) 2000-03-27 2007-04-18 株式会社東芝 半導体装置の製造方法
KR100332834B1 (ko) 2000-03-29 2002-04-15 윤덕용 비등방성 식각을 이용한 서브마이크론 게이트 제조 방법
TW466606B (en) 2000-04-20 2001-12-01 United Microelectronics Corp Manufacturing method for dual metal gate electrode
JP2001338987A (ja) 2000-05-26 2001-12-07 Nec Microsystems Ltd Ｍｏｓトランジスタのシャロートレンチ分離領域の形成方法
FR2810161B1 (fr) * 2000-06-09 2005-03-11 Commissariat Energie Atomique Memoire electronique a architecture damascene et procede de realisation d'une telle memoire
US6526996B1 (en) * 2000-06-12 2003-03-04 Promos Technologies, Inc. Dry clean method instead of traditional wet clean after metal etch
US6391782B1 (en) 2000-06-20 2002-05-21 Advanced Micro Devices, Inc. Process for forming multiple active lines and gate-all-around MOSFET
KR100360476B1 (ko) 2000-06-27 2002-11-08 삼성전자 주식회사 탄소나노튜브를 이용한 나노 크기 수직 트랜지스터 및 그제조방법
KR100545706B1 (ko) 2000-06-28 2006-01-24 주식회사 하이닉스반도체 반도체 소자 제조방법
EP1299914B1 (de) 2000-07-04 2008-04-02 Qimonda AG Feldeffekttransistor
US6515339B2 (en) * 2000-07-18 2003-02-04 Lg Electronics Inc. Method of horizontally growing carbon nanotubes and field effect transistor using the carbon nanotubes grown by the method
US20020011612A1 (en) * 2000-07-31 2002-01-31 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2002047034A (ja) * 2000-07-31 2002-02-12 Shinetsu Quartz Prod Co Ltd プラズマを利用したプロセス装置用の石英ガラス治具
US6403981B1 (en) 2000-08-07 2002-06-11 Advanced Micro Devices, Inc. Double gate transistor having a silicon/germanium channel region
KR100338778B1 (ko) 2000-08-21 2002-05-31 윤종용 선택적 실리사이드 공정을 이용한 모스 트랜지스터의제조방법
US6358800B1 (en) * 2000-09-18 2002-03-19 Vanguard International Semiconductor Corporation Method of forming a MOSFET with a recessed-gate having a channel length beyond photolithography limit
US6387820B1 (en) 2000-09-19 2002-05-14 Advanced Micro Devices, Inc. BC13/AR chemistry for metal overetching on a high density plasma etcher
JP2002100762A (ja) * 2000-09-22 2002-04-05 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP4044276B2 (ja) 2000-09-28 2008-02-06 株式会社東芝 半導体装置及びその製造方法
US6562665B1 (en) 2000-10-16 2003-05-13 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with a recess in a semiconductor pillar in SOI technology
US7163864B1 (en) 2000-10-18 2007-01-16 International Business Machines Corporation Method of fabricating semiconductor side wall fin
US6645840B2 (en) 2000-10-19 2003-11-11 Texas Instruments Incorporated Multi-layered polysilicon process
US6413802B1 (en) 2000-10-23 2002-07-02 The Regents Of The University Of California Finfet transistor structures having a double gate channel extending vertically from a substrate and methods of manufacture
US6396108B1 (en) * 2000-11-13 2002-05-28 Advanced Micro Devices, Inc. Self-aligned double gate silicon-on-insulator (SOI) device
US6716684B1 (en) 2000-11-13 2004-04-06 Advanced Micro Devices, Inc. Method of making a self-aligned triple gate silicon-on-insulator device
US6472258B1 (en) 2000-11-13 2002-10-29 International Business Machines Corporation Double gate trench transistor
US6479866B1 (en) 2000-11-14 2002-11-12 Advanced Micro Devices, Inc. SOI device with self-aligned selective damage implant, and method
JP2002198441A (ja) 2000-11-16 2002-07-12 Hynix Semiconductor Inc 半導体素子のデュアル金属ゲート形成方法
AU2001267880A1 (en) * 2000-11-22 2002-06-03 Hitachi Ltd. Semiconductor device and method for fabricating the same
US6552401B1 (en) 2000-11-27 2003-04-22 Micron Technology Use of gate electrode workfunction to improve DRAM refresh
US20020100942A1 (en) 2000-12-04 2002-08-01 Fitzgerald Eugene A. CMOS inverter and integrated circuits utilizing strained silicon surface channel MOSFETs
US6921947B2 (en) 2000-12-15 2005-07-26 Renesas Technology Corp. Semiconductor device having recessed isolation insulation film
US6413877B1 (en) * 2000-12-22 2002-07-02 Lam Research Corporation Method of preventing damage to organo-silicate-glass materials during resist stripping
JP2002198368A (ja) 2000-12-26 2002-07-12 Nec Corp 半導体装置の製造方法
US6537901B2 (en) * 2000-12-29 2003-03-25 Hynix Semiconductor Inc. Method of manufacturing a transistor in a semiconductor device
TW561530B (en) 2001-01-03 2003-11-11 Macronix Int Co Ltd Process for fabricating CMOS transistor of IC devices employing double spacers for preventing short-channel effect
US6975014B1 (en) 2001-01-09 2005-12-13 Advanced Micro Devices, Inc. Method for making an ultra thin FDSOI device with improved short-channel performance
US6359311B1 (en) 2001-01-17 2002-03-19 Taiwan Semiconductor Manufacturing Co., Ltd. Quasi-surrounding gate and a method of fabricating a silicon-on-insulator semiconductor device with the same
US20030027486A1 (en) * 2001-02-07 2003-02-06 Lapointe Brian K. Foam toys
US6403434B1 (en) 2001-02-09 2002-06-11 Advanced Micro Devices, Inc. Process for manufacturing MOS transistors having elevated source and drain regions and a high-k gate dielectric
US6475890B1 (en) 2001-02-12 2002-11-05 Advanced Micro Devices, Inc. Fabrication of a field effect transistor with an upside down T-shaped semiconductor pillar in SOI technology
JP2002246310A (ja) 2001-02-14 2002-08-30 Sony Corp 半導体薄膜の形成方法及び半導体装置の製造方法、これらの方法の実施に使用する装置、並びに電気光学装置
US6475869B1 (en) 2001-02-26 2002-11-05 Advanced Micro Devices, Inc. Method of forming a double gate transistor having an epitaxial silicon/germanium channel region
US6410371B1 (en) 2001-02-26 2002-06-25 Advanced Micro Devices, Inc. Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer
FR2822293B1 (fr) 2001-03-13 2007-03-23 Nat Inst Of Advanced Ind Scien Transistor a effet de champ et double grille, circuit integre comportant ce transistor, et procede de fabrication de ce dernier
TW582071B (en) 2001-03-20 2004-04-01 Macronix Int Co Ltd Method for etching metal in a semiconductor
JP3940565B2 (ja) 2001-03-29 2007-07-04 株式会社東芝 半導体装置及びその製造方法
US6458662B1 (en) 2001-04-04 2002-10-01 Advanced Micro Devices, Inc. Method of fabricating a semiconductor device having an asymmetrical dual-gate silicon-germanium (SiGe) channel MOSFET and a device thereby formed
KR100414217B1 (ko) 2001-04-12 2004-01-07 삼성전자주식회사 게이트 올 어라운드형 트랜지스터를 가진 반도체 장치 및그 형성 방법
US6645861B2 (en) 2001-04-18 2003-11-11 International Business Machines Corporation Self-aligned silicide process for silicon sidewall source and drain contacts
US6787402B1 (en) 2001-04-27 2004-09-07 Advanced Micro Devices, Inc. Double-gate vertical MOSFET transistor and fabrication method
US6902947B2 (en) * 2001-05-07 2005-06-07 Applied Materials, Inc. Integrated method for release and passivation of MEMS structures
SG112804A1 (en) 2001-05-10 2005-07-28 Inst Of Microelectronics Sloped trench etching process
KR100363332B1 (en) * 2001-05-23 2002-12-05 Samsung Electronics Co Ltd Method for forming semiconductor device having gate all-around type transistor
US6635923B2 (en) 2001-05-24 2003-10-21 International Business Machines Corporation Damascene double-gate MOSFET with vertical channel regions
US6506692B2 (en) * 2001-05-30 2003-01-14 Intel Corporation Method of making a semiconductor device using a silicon carbide hard mask
US6593625B2 (en) 2001-06-12 2003-07-15 International Business Machines Corporation Relaxed SiGe layers on Si or silicon-on-insulator substrates by ion implantation and thermal annealing
US6737333B2 (en) * 2001-07-03 2004-05-18 Texas Instruments Incorporated Semiconductor device isolation structure and method of forming
JP2003017508A (ja) 2001-07-05 2003-01-17 Nec Corp 電界効果トランジスタ
US6534807B2 (en) * 2001-08-13 2003-03-18 International Business Machines Corporation Local interconnect junction on insulator (JOI) structure
US6501141B1 (en) 2001-08-13 2002-12-31 Taiwan Semiconductor Manufacturing Company, Ltd Self-aligned contact with improved isolation and method for forming
US6764965B2 (en) * 2001-08-17 2004-07-20 United Microelectronics Corp. Method for improving the coating capability of low-k dielectric layer
JP2003100902A (ja) 2001-09-21 2003-04-04 Mitsubishi Electric Corp 半導体装置の製造方法
US6689650B2 (en) * 2001-09-27 2004-02-10 International Business Machines Corporation Fin field effect transistor with self-aligned gate
US6492212B1 (en) * 2001-10-05 2002-12-10 International Business Machines Corporation Variable threshold voltage double gated transistors and method of fabrication
US20030085194A1 (en) * 2001-11-07 2003-05-08 Hopkins Dean A. Method for fabricating close spaced mirror arrays
KR100398874B1 (ko) 2001-11-21 2003-09-19 삼성전자주식회사 티자형의 게이트 전극을 갖는 모스 트랜지스터 및 그 제조방법
US7385262B2 (en) * 2001-11-27 2008-06-10 The Board Of Trustees Of The Leland Stanford Junior University Band-structure modulation of nano-structures in an electric field
US6967351B2 (en) 2001-12-04 2005-11-22 International Business Machines Corporation Finfet SRAM cell using low mobility plane for cell stability and method for forming
US6657259B2 (en) * 2001-12-04 2003-12-02 International Business Machines Corporation Multiple-plane FinFET CMOS
US6610576B2 (en) * 2001-12-13 2003-08-26 International Business Machines Corporation Method for forming asymmetric dual gate transistor
US6555879B1 (en) 2002-01-11 2003-04-29 Advanced Micro Devices, Inc. SOI device with metal source/drain and method of fabrication
US6722946B2 (en) * 2002-01-17 2004-04-20 Nutool, Inc. Advanced chemical mechanical polishing system with smart endpoint detection
US6583469B1 (en) 2002-01-28 2003-06-24 International Business Machines Corporation Self-aligned dog-bone structure for FinFET applications and methods to fabricate the same
KR100442089B1 (ko) * 2002-01-29 2004-07-27 삼성전자주식회사 노치된 게이트 전극을 갖는 모스 트랜지스터의 제조방법
KR100458288B1 (ko) 2002-01-30 2004-11-26 한국과학기술원 이중-게이트 ＦｉｎＦＥＴ 소자 및 그 제조방법
DE10203998A1 (de) 2002-02-01 2003-08-21 Infineon Technologies Ag Verfahren zum Herstellen einer zackenförmigen Struktur, Verfahren zum Herstellen eines Transistors, Verfahren zum Herstellen eines Floating Gate-Transistors, Transistor, Floating Gate-Transistor und Speicher-Anordnung
US6784071B2 (en) 2003-01-31 2004-08-31 Taiwan Semiconductor Manufacturing Company, Ltd. Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement
US20030151077A1 (en) 2002-02-13 2003-08-14 Leo Mathew Method of forming a vertical double gate semiconductor device and structure thereof
JP3782021B2 (ja) 2002-02-22 2006-06-07 株式会社東芝 半導体装置、半導体装置の製造方法、半導体基板の製造方法
US6660598B2 (en) 2002-02-26 2003-12-09 International Business Machines Corporation Method of forming a fully-depleted SOI ( silicon-on-insulator) MOSFET having a thinned channel region
JP4370104B2 (ja) 2002-03-05 2009-11-25 シャープ株式会社 半導体記憶装置
US6639827B2 (en) 2002-03-12 2003-10-28 Intel Corporation Low standby power using shadow storage
US6948237B2 (en) 2002-03-15 2005-09-27 Fuji Photo Film Co., Ltd. Methods for manufacturing film cartridge and for feeding plate material
US6635909B2 (en) 2002-03-19 2003-10-21 International Business Machines Corporation Strained fin FETs structure and method
US6605498B1 (en) * 2002-03-29 2003-08-12 Intel Corporation Semiconductor transistor having a backfilled channel material
FR2838238B1 (fr) * 2002-04-08 2005-04-15 St Microelectronics Sa Dispositif semiconducteur a grille enveloppante encapsule dans un milieu isolant
US6784076B2 (en) 2002-04-08 2004-08-31 Micron Technology, Inc. Process for making a silicon-on-insulator ledge by implanting ions from silicon source
US6762469B2 (en) 2002-04-19 2004-07-13 International Business Machines Corporation High performance CMOS device structure with mid-gap metal gate
US6713396B2 (en) * 2002-04-29 2004-03-30 Hewlett-Packard Development Company, L.P. Method of fabricating high density sub-lithographic features on a substrate
US6537885B1 (en) * 2002-05-09 2003-03-25 Infineon Technologies Ag Transistor and method of manufacturing a transistor having a shallow junction formation using a two step EPI layer
US6642090B1 (en) 2002-06-03 2003-11-04 International Business Machines Corporation Fin FET devices from bulk semiconductor and method for forming
US7074623B2 (en) * 2002-06-07 2006-07-11 Amberwave Systems Corporation Methods of forming strained-semiconductor-on-insulator finFET device structures
US6680240B1 (en) 2002-06-25 2004-01-20 Advanced Micro Devices, Inc. Silicon-on-insulator device with strained device film and method for making the same with partial replacement of isolation oxide
US7105891B2 (en) 2002-07-15 2006-09-12 Texas Instruments Incorporated Gate structure and method
US6974729B2 (en) * 2002-07-16 2005-12-13 Interuniversitair Microelektronica Centrum (Imec) Integrated semiconductor fin device and a method for manufacturing such device
DE10232804A1 (de) 2002-07-19 2004-02-12 Piv Drives Gmbh Landmaschine mit stufenlosem Kegelscheibengetriebe
KR100477543B1 (ko) * 2002-07-26 2005-03-18 동부아남반도체 주식회사 단채널 트랜지스터 형성방법
US6919238B2 (en) 2002-07-29 2005-07-19 Intel Corporation Silicon on insulator (SOI) transistor and methods of fabrication
US6921702B2 (en) 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
JP2004071996A (ja) * 2002-08-09 2004-03-04 Hitachi Ltd 半導体集積回路装置の製造方法
US6833556B2 (en) 2002-08-12 2004-12-21 Acorn Technologies, Inc. Insulated gate field effect transistor having passivated schottky barriers to the channel
US6891234B1 (en) 2004-01-07 2005-05-10 Acorn Technologies, Inc. Transistor with workfunction-induced charge layer
US6984585B2 (en) * 2002-08-12 2006-01-10 Applied Materials Inc Method for removal of residue from a magneto-resistive random access memory (MRAM) film stack using a sacrificial mask layer
JP3865233B2 (ja) 2002-08-19 2007-01-10 富士通株式会社 Ｃｍｏｓ集積回路装置
US7358121B2 (en) * 2002-08-23 2008-04-15 Intel Corporation Tri-gate devices and methods of fabrication
US7163851B2 (en) 2002-08-26 2007-01-16 International Business Machines Corporation Concurrent Fin-FET and thick-body device fabrication
JP5179692B2 (ja) 2002-08-30 2013-04-10 富士通セミコンダクター株式会社 半導体記憶装置及びその製造方法
US6770516B2 (en) 2002-09-05 2004-08-03 Taiwan Semiconductor Manufacturing Company Method of forming an N channel and P channel FINFET device on the same semiconductor substrate
JP3651802B2 (ja) 2002-09-12 2005-05-25 株式会社東芝 半導体装置の製造方法
US6794313B1 (en) 2002-09-20 2004-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Oxidation process to improve polysilicon sidewall roughness
JP3556651B2 (ja) * 2002-09-27 2004-08-18 沖電気工業株式会社 半導体装置の製造方法
US6800910B2 (en) 2002-09-30 2004-10-05 Advanced Micro Devices, Inc. FinFET device incorporating strained silicon in the channel region
KR100481209B1 (ko) 2002-10-01 2005-04-08 삼성전자주식회사 다중 채널을 갖는 모스 트랜지스터 및 그 제조방법
JP4294935B2 (ja) * 2002-10-17 2009-07-15 株式会社ルネサステクノロジ 半導体装置
US8222680B2 (en) 2002-10-22 2012-07-17 Advanced Micro Devices, Inc. Double and triple gate MOSFET devices and methods for making same
US6706571B1 (en) * 2002-10-22 2004-03-16 Advanced Micro Devices, Inc. Method for forming multiple structures in a semiconductor device
US6833588B2 (en) 2002-10-22 2004-12-21 Advanced Micro Devices, Inc. Semiconductor device having a U-shaped gate structure
US6706581B1 (en) 2002-10-29 2004-03-16 Taiwan Semiconductor Manufacturing Company Dual gate dielectric scheme: SiON for high performance devices and high k for low power devices
US6787439B2 (en) 2002-11-08 2004-09-07 Advanced Micro Devices, Inc. Method using planarizing gate material to improve gate critical dimension in semiconductor devices
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US6855990B2 (en) 2002-11-26 2005-02-15 Taiwan Semiconductor Manufacturing Co., Ltd Strained-channel multiple-gate transistor
US6864519B2 (en) * 2002-11-26 2005-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. CMOS SRAM cell configured using multiple-gate transistors
US6709982B1 (en) * 2002-11-26 2004-03-23 Advanced Micro Devices, Inc. Double spacer FinFET formation
US6825506B2 (en) 2002-11-27 2004-11-30 Intel Corporation Field effect transistor and method of fabrication
US6821834B2 (en) 2002-12-04 2004-11-23 Yoshiyuki Ando Ion implantation methods and transistor cell layout for fin type transistors
US6645797B1 (en) 2002-12-06 2003-11-11 Advanced Micro Devices, Inc. Method for forming fins in a FinFET device using sacrificial carbon layer
US6686231B1 (en) * 2002-12-06 2004-02-03 Advanced Micro Devices, Inc. Damascene gate process with sacrificial oxide in semiconductor devices
KR100487922B1 (ko) * 2002-12-06 2005-05-06 주식회사 하이닉스반도체 반도체소자의 트랜지스터 및 그 형성방법
US7728360B2 (en) 2002-12-06 2010-06-01 Taiwan Semiconductor Manufacturing Co., Ltd. Multiple-gate transistor structure
US6869868B2 (en) 2002-12-13 2005-03-22 Taiwan Semiconductor Manufacturing Company, Ltd. Method of fabricating a MOSFET device with metal containing gate structures
US6794718B2 (en) 2002-12-19 2004-09-21 International Business Machines Corporation High mobility crystalline planes in double-gate CMOS technology
ATE481736T1 (de) 2002-12-19 2010-10-15 Ibm Finfet sram-zelle mit invertierten finfet- dünnschichttransistoren
EP1581968B1 (en) 2002-12-20 2010-05-12 International Business Machines Corporation Integrated antifuse structure for finfet and cmos devices
US6780694B2 (en) * 2003-01-08 2004-08-24 International Business Machines Corporation MOS transistor
US7259425B2 (en) 2003-01-23 2007-08-21 Advanced Micro Devices, Inc. Tri-gate and gate around MOSFET devices and methods for making same
US6803631B2 (en) 2003-01-23 2004-10-12 Advanced Micro Devices, Inc. Strained channel finfet
US6762483B1 (en) 2003-01-23 2004-07-13 Advanced Micro Devices, Inc. Narrow fin FinFET
US6885055B2 (en) 2003-02-04 2005-04-26 Lee Jong-Ho Double-gate FinFET device and fabricating method thereof
KR100543472B1 (ko) 2004-02-11 2006-01-20 삼성전자주식회사 소오스/드레인 영역에 디플리션 방지막을 구비하는 반도체소자 및 그 형성 방법
US7304336B2 (en) 2003-02-13 2007-12-04 Massachusetts Institute Of Technology FinFET structure and method to make the same
US6855606B2 (en) * 2003-02-20 2005-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor nano-rod devices
US7105894B2 (en) 2003-02-27 2006-09-12 Taiwan Semiconductor Manufacturing Co., Ltd. Contacts to semiconductor fin devices
KR100499159B1 (ko) 2003-02-28 2005-07-01 삼성전자주식회사 리세스 채널을 갖는 반도체장치 및 그 제조방법
US6921913B2 (en) 2003-03-04 2005-07-26 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel transistor structure with lattice-mismatched zone
US6828628B2 (en) 2003-03-05 2004-12-07 Agere Systems, Inc. Diffused MOS devices with strained silicon portions and methods for forming same
US6787854B1 (en) 2003-03-12 2004-09-07 Advanced Micro Devices, Inc. Method for forming a fin in a finFET device
US6800885B1 (en) 2003-03-12 2004-10-05 Advance Micro Devices, Inc. Asymmetrical double gate or all-around gate MOSFET devices and methods for making same
US6716690B1 (en) * 2003-03-12 2004-04-06 Advanced Micro Devices, Inc. Uniformly doped source/drain junction in a double-gate MOSFET
TW582099B (en) * 2003-03-13 2004-04-01 Ind Tech Res Inst Method of adhering material layer on transparent substrate and method of forming single crystal silicon on transparent substrate
JP4563652B2 (ja) * 2003-03-13 2010-10-13 シャープ株式会社 メモリ機能体および微粒子形成方法並びにメモリ素子、半導体装置および電子機器
US6844238B2 (en) 2003-03-26 2005-01-18 Taiwan Semiconductor Manufacturing Co., Ltd Multiple-gate transistors with improved gate control
US20040191980A1 (en) * 2003-03-27 2004-09-30 Rafael Rios Multi-corner FET for better immunity from short channel effects
US6790733B1 (en) 2003-03-28 2004-09-14 International Business Machines Corporation Preserving TEOS hard mask using COR for raised source-drain including removable/disposable spacer
US6764884B1 (en) 2003-04-03 2004-07-20 Advanced Micro Devices, Inc. Method for forming a gate in a FinFET device and thinning a fin in a channel region of the FinFET device
US6902962B2 (en) 2003-04-04 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Silicon-on-insulator chip with multiple crystal orientations
TWI231994B (en) 2003-04-04 2005-05-01 Univ Nat Taiwan Strained Si FinFET
JP4689969B2 (ja) 2003-04-05 2011-06-01 ローム・アンド・ハース・エレクトロニック・マテリアルズ，エル．エル．シー． Ｉｖａ族およびｖｉａ族化合物の調製
US7442415B2 (en) 2003-04-11 2008-10-28 Sharp Laboratories Of America, Inc. Modulated temperature method of atomic layer deposition (ALD) of high dielectric constant films
JP2004319704A (ja) 2003-04-15 2004-11-11 Seiko Instruments Inc 半導体装置
TW200506093A (en) 2003-04-21 2005-02-16 Aviza Tech Inc System and method for forming multi-component films
WO2004097943A1 (ja) * 2003-04-28 2004-11-11 Matsushita Electric Industrial Co., Ltd. 半導体装置とその製造方法
US7074656B2 (en) 2003-04-29 2006-07-11 Taiwan Semiconductor Manufacturing Company, Ltd. Doping of semiconductor fin devices
US6867433B2 (en) 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
JP3976703B2 (ja) 2003-04-30 2007-09-19 エルピーダメモリ株式会社 半導体装置の製造方法
US6838322B2 (en) 2003-05-01 2005-01-04 Freescale Semiconductor, Inc. Method for forming a double-gated semiconductor device
US6909147B2 (en) 2003-05-05 2005-06-21 International Business Machines Corporation Multi-height FinFETS
US20060170053A1 (en) * 2003-05-09 2006-08-03 Yee-Chia Yeo Accumulation mode multiple gate transistor
US7812340B2 (en) 2003-06-13 2010-10-12 International Business Machines Corporation Strained-silicon-on-insulator single-and double-gate MOSFET and method for forming the same
US6830998B1 (en) 2003-06-17 2004-12-14 Advanced Micro Devices, Inc. Gate dielectric quality for replacement metal gate transistors
US7045401B2 (en) 2003-06-23 2006-05-16 Sharp Laboratories Of America, Inc. Strained silicon finFET device
US20040262683A1 (en) 2003-06-27 2004-12-30 Bohr Mark T. PMOS transistor strain optimization with raised junction regions
US6909151B2 (en) 2003-06-27 2005-06-21 Intel Corporation Nonplanar device with stress incorporation layer and method of fabrication
US6960517B2 (en) 2003-06-30 2005-11-01 Intel Corporation N-gate transistor
US7196372B1 (en) * 2003-07-08 2007-03-27 Spansion Llc Flash memory device
US6716686B1 (en) 2003-07-08 2004-04-06 Advanced Micro Devices, Inc. Method for forming channels in a finfet device
US6921982B2 (en) * 2003-07-21 2005-07-26 International Business Machines Corporation FET channel having a strained lattice structure along multiple surfaces
KR100487566B1 (ko) 2003-07-23 2005-05-03 삼성전자주식회사 핀 전계 효과 트랜지스터 및 그 형성 방법
KR100487567B1 (ko) * 2003-07-24 2005-05-03 삼성전자주식회사 핀 전계효과 트랜지스터 형성 방법
EP1519420A2 (en) 2003-09-25 2005-03-30 Interuniversitaire Microelectronica Centrum vzw ( IMEC) Multiple gate semiconductor device and method for forming same
US6835618B1 (en) 2003-08-05 2004-12-28 Advanced Micro Devices, Inc. Epitaxially grown fin for FinFET
US6787406B1 (en) 2003-08-12 2004-09-07 Advanced Micro Devices, Inc. Systems and methods for forming dense n-channel and p-channel fins using shadow implanting
US7172943B2 (en) * 2003-08-13 2007-02-06 Taiwan Semiconductor Manufacturing Company, Ltd. Multiple-gate transistors formed on bulk substrates
KR100496891B1 (ko) 2003-08-14 2005-06-23 삼성전자주식회사 핀 전계효과 트랜지스터를 위한 실리콘 핀 및 그 제조 방법
US7355253B2 (en) * 2003-08-22 2008-04-08 International Business Machines Corporation Strained-channel Fin field effect transistor (FET) with a uniform channel thickness and separate gates
US6998301B1 (en) * 2003-09-03 2006-02-14 Advanced Micro Devices, Inc. Method for forming a tri-gate MOSFET
US6955969B2 (en) 2003-09-03 2005-10-18 Advanced Micro Devices, Inc. Method of growing as a channel region to reduce source/drain junction capacitance
US6877728B2 (en) 2003-09-04 2005-04-12 Lakin Manufacturing Corporation Suspension assembly having multiple torsion members which cooperatively provide suspension to a wheel
JP4439358B2 (ja) 2003-09-05 2010-03-24 株式会社東芝 電界効果トランジスタ及びその製造方法
US7170126B2 (en) * 2003-09-16 2007-01-30 International Business Machines Corporation Structure of vertical strained silicon devices
US6970373B2 (en) 2003-10-02 2005-11-29 Intel Corporation Method and apparatus for improving stability of a 6T CMOS SRAM cell
US6888199B2 (en) 2003-10-07 2005-05-03 International Business Machines Corporation High-density split-gate FinFET
US6855588B1 (en) * 2003-10-07 2005-02-15 United Microelectronics Corp. Method of fabricating a double gate MOSFET device
WO2005036651A1 (ja) 2003-10-09 2005-04-21 Nec Corporation 半導体装置及びその製造方法
US20050139860A1 (en) 2003-10-22 2005-06-30 Snyder John P. Dynamic schottky barrier MOSFET device and method of manufacture
US6946377B2 (en) * 2003-10-29 2005-09-20 Texas Instruments Incorporated Multiple-gate MOSFET device with lithography independent silicon body thickness and methods for fabricating the same
US7138320B2 (en) * 2003-10-31 2006-11-21 Advanced Micro Devices, Inc. Advanced technique for forming a transistor having raised drain and source regions
KR100515061B1 (ko) 2003-10-31 2005-09-14 삼성전자주식회사 핀 전계 효과 트랜지스터를 갖는 반도체 소자 및 그 형성방법
US6867460B1 (en) 2003-11-05 2005-03-15 International Business Machines Corporation FinFET SRAM cell with chevron FinFET logic
US6831310B1 (en) 2003-11-10 2004-12-14 Freescale Semiconductor, Inc. Integrated circuit having multiple memory types and method of formation
KR100521384B1 (ko) 2003-11-17 2005-10-12 삼성전자주식회사 반도체 소자 및 그 제조 방법
US6885072B1 (en) * 2003-11-18 2005-04-26 Applied Intellectual Properties Co., Ltd. Nonvolatile memory with undercut trapping structure
US7545001B2 (en) 2003-11-25 2009-06-09 Taiwan Semiconductor Manufacturing Company Semiconductor device having high drive current and method of manufacture therefor
US7183137B2 (en) * 2003-12-01 2007-02-27 Taiwan Semiconductor Manufacturing Company Method for dicing semiconductor wafers
US7075150B2 (en) 2003-12-02 2006-07-11 International Business Machines Corporation Ultra-thin Si channel MOSFET using a self-aligned oxygen implant and damascene technique
US7018551B2 (en) * 2003-12-09 2006-03-28 International Business Machines Corporation Pull-back method of forming fins in FinFets
US7388258B2 (en) * 2003-12-10 2008-06-17 International Business Machines Corporation Sectional field effect devices
US7662689B2 (en) 2003-12-23 2010-02-16 Intel Corporation Strained transistor integration for CMOS
US7223679B2 (en) 2003-12-24 2007-05-29 Intel Corporation Transistor gate electrode having conductor material layer
US7105390B2 (en) 2003-12-30 2006-09-12 Intel Corporation Nonplanar transistors with metal gate electrodes
US7045407B2 (en) 2003-12-30 2006-05-16 Intel Corporation Amorphous etch stop for the anisotropic etching of substrates
US7247578B2 (en) 2003-12-30 2007-07-24 Intel Corporation Method of varying etch selectivities of a film
US7078282B2 (en) 2003-12-30 2006-07-18 Intel Corporation Replacement gate flow facilitating high yield and incorporation of etch stop layers and/or stressed films
US6997415B2 (en) * 2003-12-31 2006-02-14 Gulfstream Aerospace Corporation Method and arrangement for aircraft fuel dispersion
US7705345B2 (en) * 2004-01-07 2010-04-27 International Business Machines Corporation High performance strained silicon FinFETs device and method for forming same
US7056794B2 (en) 2004-01-09 2006-06-06 International Business Machines Corporation FET gate structure with metal gate electrode and silicide contact
US6974736B2 (en) 2004-01-09 2005-12-13 International Business Machines Corporation Method of forming FET silicide gate structures incorporating inner spacers
US7268058B2 (en) 2004-01-16 2007-09-11 Intel Corporation Tri-gate transistors and methods to fabricate same
US7385247B2 (en) 2004-01-17 2008-06-10 Samsung Electronics Co., Ltd. At least penta-sided-channel type of FinFET transistor
JP2005209782A (ja) 2004-01-21 2005-08-04 Toshiba Corp 半導体装置
US7250645B1 (en) * 2004-01-22 2007-07-31 Advanced Micro Devices, Inc. Reversed T-shaped FinFET
US7224029B2 (en) 2004-01-28 2007-05-29 International Business Machines Corporation Method and structure to create multiple device widths in FinFET technology in both bulk and SOI
KR100587672B1 (ko) 2004-02-02 2006-06-08 삼성전자주식회사 다마신 공법을 이용한 핀 트랜지스터 형성방법
EP1566844A3 (en) 2004-02-20 2006-04-05 Samsung Electronics Co., Ltd. Multi-gate transistor and method for manufacturing the same
US7060539B2 (en) 2004-03-01 2006-06-13 International Business Machines Corporation Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
JP4852694B2 (ja) 2004-03-02 2012-01-11 独立行政法人産業技術総合研究所 半導体集積回路およびその製造方法
US6921691B1 (en) 2004-03-18 2005-07-26 Infineon Technologies Ag Transistor with dopant-bearing metal in source and drain
KR100576361B1 (ko) 2004-03-23 2006-05-03 삼성전자주식회사 3차원 시모스 전계효과 트랜지스터 및 그것을 제조하는 방법
US6881635B1 (en) 2004-03-23 2005-04-19 International Business Machines Corporation Strained silicon NMOS devices with embedded source/drain
US7141480B2 (en) 2004-03-26 2006-11-28 Texas Instruments Incorporated Tri-gate low power device and method for manufacturing the same
US7049654B2 (en) * 2004-03-31 2006-05-23 Intel Corporation Memory with split gate devices and method of fabrication
US8450806B2 (en) 2004-03-31 2013-05-28 International Business Machines Corporation Method for fabricating strained silicon-on-insulator structures and strained silicon-on insulator structures formed thereby
US7154118B2 (en) 2004-03-31 2006-12-26 Intel Corporation Bulk non-planar transistor having strained enhanced mobility and methods of fabrication
US20050224797A1 (en) 2004-04-01 2005-10-13 Taiwan Semiconductor Manufacturing Company, Ltd. CMOS fabricated on different crystallographic orientation substrates
US7023018B2 (en) 2004-04-06 2006-04-04 Texas Instruments Incorporated SiGe transistor with strained layers
US20050230763A1 (en) 2004-04-15 2005-10-20 Taiwan Semiconductor Manufacturing Co., Ltd. Method of manufacturing a microelectronic device with electrode perturbing sill
KR100642632B1 (ko) 2004-04-27 2006-11-10 삼성전자주식회사 반도체소자의 제조방법들 및 그에 의해 제조된 반도체소자들
US7084018B1 (en) 2004-05-05 2006-08-01 Advanced Micro Devices, Inc. Sacrificial oxide for minimizing box undercut in damascene FinFET
US20050255642A1 (en) 2004-05-11 2005-11-17 Chi-Wen Liu Method of fabricating inlaid structure
US7355233B2 (en) 2004-05-12 2008-04-08 Taiwan Semiconductor Manufacturing Company, Ltd. Apparatus and method for multiple-gate semiconductor device with angled sidewalls
US6864540B1 (en) * 2004-05-21 2005-03-08 International Business Machines Corp. High performance FET with elevated source/drain region
KR100625177B1 (ko) 2004-05-25 2006-09-20 삼성전자주식회사 멀티-브리지 채널형 모오스 트랜지스터의 제조 방법
KR100532564B1 (ko) * 2004-05-25 2005-12-01 한국전자통신연구원 다중 게이트 모스 트랜지스터 및 그 제조 방법
KR100634372B1 (ko) 2004-06-04 2006-10-16 삼성전자주식회사 반도체 소자들 및 그 형성 방법들
US7989855B2 (en) 2004-06-10 2011-08-02 Nec Corporation Semiconductor device including a deflected part
US7132360B2 (en) 2004-06-10 2006-11-07 Freescale Semiconductor, Inc. Method for treating a semiconductor surface to form a metal-containing layer
US7291886B2 (en) 2004-06-21 2007-11-06 International Business Machines Corporation Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
US8669145B2 (en) 2004-06-30 2014-03-11 International Business Machines Corporation Method and structure for strained FinFET devices
US7042009B2 (en) 2004-06-30 2006-05-09 Intel Corporation High mobility tri-gate devices and methods of fabrication
US7348284B2 (en) 2004-08-10 2008-03-25 Intel Corporation Non-planar pMOS structure with a strained channel region and an integrated strained CMOS flow
US20060040054A1 (en) * 2004-08-18 2006-02-23 Pearlstein Ronald M Passivating ALD reactor chamber internal surfaces to prevent residue buildup
US7105934B2 (en) 2004-08-30 2006-09-12 International Business Machines Corporation FinFET with low gate capacitance and low extrinsic resistance
US7250367B2 (en) * 2004-09-01 2007-07-31 Micron Technology, Inc. Deposition methods using heteroleptic precursors
US7071064B2 (en) * 2004-09-23 2006-07-04 Intel Corporation U-gate transistors and methods of fabrication
US7422946B2 (en) 2004-09-29 2008-09-09 Intel Corporation Independently accessed double-gate and tri-gate transistors in same process flow
US7332439B2 (en) 2004-09-29 2008-02-19 Intel Corporation Metal gate transistors with epitaxial source and drain regions
US20060086977A1 (en) 2004-10-25 2006-04-27 Uday Shah Nonplanar device with thinned lower body portion and method of fabrication
US20060138548A1 (en) 2004-12-07 2006-06-29 Thunderbird Technologies, Inc. Strained silicon, gate engineered Fermi-FETs
US7247547B2 (en) 2005-01-05 2007-07-24 International Business Machines Corporation Method of fabricating a field effect transistor having improved junctions
US7875547B2 (en) 2005-01-12 2011-01-25 Taiwan Semiconductor Manufacturing Co., Ltd. Contact hole structures and contact structures and fabrication methods thereof
US7193279B2 (en) 2005-01-18 2007-03-20 Intel Corporation Non-planar MOS structure with a strained channel region
US7326611B2 (en) * 2005-02-03 2008-02-05 Micron Technology, Inc. DRAM arrays, vertical transistor structures and methods of forming transistor structures and DRAM arrays
US20060172480A1 (en) 2005-02-03 2006-08-03 Taiwan Semiconductor Manufacturing Company, Ltd. Single metal gate CMOS device design
US7238564B2 (en) * 2005-03-10 2007-07-03 Taiwan Semiconductor Manufacturing Company Method of forming a shallow trench isolation structure
US7177177B2 (en) 2005-04-07 2007-02-13 International Business Machines Corporation Back-gate controlled read SRAM cell
KR100699839B1 (ko) 2005-04-21 2007-03-27 삼성전자주식회사 다중채널을 갖는 반도체 장치 및 그의 제조방법.
US7429536B2 (en) 2005-05-23 2008-09-30 Micron Technology, Inc. Methods for forming arrays of small, closely spaced features
US7319074B2 (en) 2005-06-13 2008-01-15 United Microelectronics Corp. Method of defining polysilicon patterns
US7547637B2 (en) 2005-06-21 2009-06-16 Intel Corporation Methods for patterning a semiconductor film
US7279375B2 (en) * 2005-06-30 2007-10-09 Intel Corporation Block contact architectures for nanoscale channel transistors
US20070023795A1 (en) * 2005-07-15 2007-02-01 Kabushiki Kaisha Toshiba Semiconductor device and method of fabricating the same
US7352034B2 (en) 2005-08-25 2008-04-01 International Business Machines Corporation Semiconductor structures integrating damascene-body FinFET's and planar devices on a common substrate and methods for forming such semiconductor structures
US7416943B2 (en) 2005-09-01 2008-08-26 Micron Technology, Inc. Peripheral gate stacks and recessed array gates
US20070090408A1 (en) 2005-09-29 2007-04-26 Amlan Majumdar Narrow-body multiple-gate FET with dominant body transistor for high performance
US8513066B2 (en) * 2005-10-25 2013-08-20 Freescale Semiconductor, Inc. Method of making an inverted-T channel transistor
US20070287256A1 (en) * 2006-06-07 2007-12-13 International Business Machines Corporation Contact scheme for FINFET structures with multiple FINs
US20090072279A1 (en) * 2007-08-29 2009-03-19 Ecole Polytechnique Federale De Lausanne (Epfl) Capacitor-less memory and abrupt switch based on hysteresis characteristics in punch-through impact ionization mos transistor (PI-MOS)
US8022487B2 (en) * 2008-04-29 2011-09-20 Intel Corporation Increasing body dopant uniformity in multi-gate transistor devices
US7902009B2 (en) * 2008-12-11 2011-03-08 Intel Corporation Graded high germanium compound films for strained semiconductor devices

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103839810A (zh) * 2012-11-21 2014-06-04 中芯国际集成电路制造(上海)有限公司 鳍式场效应晶体管芯片及其制造方法
WO2015143697A1 (zh) * 2014-03-28 2015-10-01 江苏宏微科技股份有限公司 一种双栅mos结构的功率晶体管及其制作方法
CN103928348A (zh) * 2014-04-28 2014-07-16 上海华力微电子有限公司 双栅极的分离方法
CN103928349A (zh) * 2014-04-28 2014-07-16 上海华力微电子有限公司 鳍式场效晶体管中栅极的分离方法
CN103943484A (zh) * 2014-04-28 2014-07-23 上海华力微电子有限公司 自对准的栅极分离方法
CN103972103A (zh) * 2014-04-28 2014-08-06 上海华力微电子有限公司 增加光刻对准的栅极分离方法
CN103943484B (zh) * 2014-04-28 2016-08-17 上海华力微电子有限公司 自对准的栅极分离方法
CN103972103B (zh) * 2014-04-28 2017-01-18 上海华力微电子有限公司 增加光刻对准的栅极分离方法
CN103928349B (zh) * 2014-04-28 2017-03-15 上海华力微电子有限公司 鳍式场效晶体管中栅极的分离方法
CN106504983A (zh) * 2015-09-06 2017-03-15 中国科学院微电子研究所 半导体器件制造方法

Also Published As

Publication number Publication date
US7859053B2 (en) 2010-12-28
KR20070046203A (ko) 2007-05-02
WO2006039600A1 (en) 2006-04-13
US20130009248A1 (en) 2013-01-10
US7037790B2 (en) 2006-05-02
US8399922B2 (en) 2013-03-19
DE112005002428B4 (de) 2010-11-18
DE112005002428T5 (de) 2009-03-05
US7422946B2 (en) 2008-09-09
TW200625602A (en) 2006-07-16
US20060128131A1 (en) 2006-06-15
US20100297838A1 (en) 2010-11-25
TWI287867B (en) 2007-10-01
KR100900831B1 (ko) 2009-06-04
CN101027772B (zh) 2011-01-12
US20060068550A1 (en) 2006-03-30
US20060071299A1 (en) 2006-04-06
US8268709B2 (en) 2012-09-18

Similar Documents

Publication Publication Date Title
CN101027772B (zh) 在相同工艺流程内被独立访问的双栅和三栅晶体管及其制造方法
US7880231B2 (en) Integration of a floating body memory on SOI with logic transistors on bulk substrate
US7052958B1 (en) FinFET CMOS with NVRAM capability
CN107492542B (zh) 半导体组件及其制造方法
US20090179266A1 (en) Device structures for a metal-oxide-semiconductor field effect transistor and methods of fabricating such device structures
US20050093147A1 (en) Structure for reducing leakage currents and high contact resistance for embedded memory and method for making same
JP2005536893A (ja) 半導体構造体
US5470776A (en) Method for fabricating stacked dynamic random access memory cell
JP2002118255A (ja) 半導体装置およびその製造方法
JP2003512724A (ja) 非浮遊ボディを備える電界効果トランジスタおよびバルクシリコンウェハ上に当該トランジスタを形成するための方法
US7968392B2 (en) Tri-gate integration with embedded floating body memory cell using a high-K dual metal gate
US7390730B2 (en) Method of fabricating a body capacitor for SOI memory
KR101377705B1 (ko) 단위 면적당 고 커패시턴스를 갖는 커패시터를 포함하는 반도체 소자를 제조하기 위한 방법
US20020079525A1 (en) Semiconductor device and method of fabricating the same
US6900102B2 (en) Methods of forming double gate electrodes using tunnel and trench
US6569729B1 (en) Method of fabricating three dimensional CMOSFET devices for an embedded DRAM application
US6664150B2 (en) Active well schemes for SOI technology
US8227301B2 (en) Semiconductor device structures with floating body charge storage and methods for forming such semiconductor device structures
KR20030050995A (ko) 고집적 트랜지스터의 제조 방법
US11355401B1 (en) Field effect transistor
KR20040049552A (ko) 반도체소자의 형성방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CF01 Termination of patent right due to non-payment of annual fee
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20110112

Termination date: 20180929