Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/111—Field plates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/40—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels
  • H10D30/47—FETs having zero-dimensional [0D], one-dimensional [1D] or two-dimensional [2D] charge carrier gas channels having 2D charge carrier gas channels, e.g. nanoribbon FETs or high electron mobility transistors [HEMT]
  • H10D30/471—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT]
  • H10D30/475—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs
  • H10D30/4755—High electron mobility transistors [HEMT] or high hole mobility transistors [HHMT] having wider bandgap layer formed on top of lower bandgap active layer, e.g. undoped barrier HEMTs such as i-AlGaN/GaN HEMTs having wide bandgap charge-carrier supplying layers, e.g. modulation doped HEMTs such as n-AlGaAs/GaAs HEMTs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/343—Gate regions of field-effect devices having PN junction gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
  • H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
  • H10D64/251—Source or drain electrodes for field-effect devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
  • H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
  • H10D62/351—Substrate regions of field-effect devices
  • H10D62/357—Substrate regions of field-effect devices of FETs
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
  • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
  • H10D62/85—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group III-V materials, e.g. GaAs
  • H10D62/8503—Nitride Group III-V materials, e.g. AlN or GaN

Definitions

• the present invention relates to a power semiconductor device used for power control.
• the present invention relates to a lateral type power FET using nitride semiconductor, a Schott y Barrier Diode (SBD) and the like.
• SBD Schott y Barrier Diode
• Power semiconductor devices such as switching device and diode are used for power control circuits such as switching mode power supply and inverter circuit.
• the power semiconductor device requires the following characteristics, that is, high breakdown voltage and low ON resistance.
• device material between breakdown voltage and ON resistance in the power semiconductor device.
• the low ON resistance close to the limitations of the principal device material, that is, silicon is realized in the power semiconductor device.
• the device material needs to be changed.
• Such as GaN and AlGaN nitride semiconductors or silicon carbide (SiC) wide band gap semiconductors are used as switching device material. By doing so, it is possible to improve the trade-off relationship determined by the above materials, and to achieve low ON resistance.
• HEMT High Electron Mobility Transistor
• nitride semiconductors such as GaN and AlGaN
• the document is R. Coffie et al, "p-Capped GaN-AlGaN-GaN High Electron Mobility Transistors (HEMTs) ", IEEE ELECTRON DEVICE LETTERS, VOL. 23, No. 10. OCTOBER 2002, page 598-590.
• HEMTs High Electron Mobility Transistor
• HEMTs p-Capped GaN-AlGaN-GaN High Electron Mobility Transistors
• An object of the present invention is to provide a power semiconductor device, which has high avalanche " withstand capability and ultra-low ON resistance.
• a power semiconductor device comprises : a first semiconductor layer of non-doped Al ⁇ Ga]_- ⁇ N
• the power semiconductor device of the present invention generates two-dimensional electron gas having high mobility by combining AlGaN-based hetero-junction structure, and uses the electron gas thus generated as a carrier when current is carried, and thereby, low ON resistance can be realized.
• the nitride semiconductor having wide band gap is used, and field plate structure is employed, and thereby, high breakdown voltage can be realized.
• the p-type AlGaN layer is formed on the surface of the semiconductor layer, and thereby, it is possible to speedily discharge holes when avalanche breakdown occurs; therefore, high avalanche withstand capability can be obtained.
• FIG. 1 is a cross-sectional view schematically showing a power semiconductor device according to a first embodiment of the present invention
• FIG. 2 is a cross-sectional view schematically showing a power semiconductor device according to a first modification example of the first embodiment
• FIG. 3 is a cross-sectional view schematically showing a power semiconductor device according to a second modification example of the first embodiment
• FIG. 4 is a cross-sectional view schematically showing a power semiconductor device according to a third modification example of the first embodiment
• FIG. 5 is a cross-sectional view schematically showing a power semiconductor device according to a second embodiment of the present invention
• FIG. 6A and FIG. 6B are a cross-sectional view and a characteristic diagram respectively to explain the above second embodiment
• FIG. 7A to FIG. 7C are a cross-sectional view and a characteristic diagram respectively to explain the above second embodiment
• FIG. 8 is a cross-sectional view schematically showing a power semiconductor device according to a third embodiment of the present invention.
• FIG. 9 is a cross-sectional view schematically showing a power semiconductor device according to a fourth embodiment of the present invention.
• FIG. 10 is a cross-sectional view schematically showing a power semiconductor device according to a modification example of the fourth embodiment
• FIG. 11 is a cross-sectional view schematically showing a power semiconductor device according to a fifth embodiment of the present invention.
• FIG. 12 is a cross-sectional view schematically showing a power semiconductor device according to a first modification example of the fifth embodiment
• FIG. 13A and FIG. 13B are a cross-sectional view and a top plan view schematically showing a power semiconductor device according to a second modification example of the fifth embodiment
• FIG. 14 is a cross-sectional view schematically showing a power semiconductor device according to a sixth embodiment of the present invention
• FIG. 15 is a cross-sectional view schematically showing a power semiconductor device according to a seventh embodiment of the present invention.
• FIG. 16A and FIG. 16B are a cross-sectional view and a characteristic diagram respectively to explain the above seventh embodiment.
• FIG. 1 is a cross-sectional view schematically showing the structure of a junction type power HEMT (High Electron Mobility Transistor) according to a first embodiment of the present invention.
• HEMT High Electron Mobility Transistor
• the thickness of the channel layer 1 is set to about 1 to 2 ⁇ m in order to obtain a breakdown voltage of 600 V.
• a barrier layer 2 is formed on the surface (one side) of the channel layer 1 as n-type Al ⁇ Ga ⁇ _ ⁇ N (O ⁇ Y ⁇ l, X ⁇ Y) with a thickness of 0.02 ⁇ m.
• a semiconductor layer 3 is selectively formed on the barrier layer 2 as p-type (0 ⁇ Z ⁇ 1) with a thickness of 0.01 ⁇ m.
• a drain electrode (D: first electrode) 4 and a source electrode (S: second electrode) 5 consisting of Ti/Al/Ni/Au are formed separately from each other at both sides of the above semiconductor layer 3 on the barrier layer 2.
• the above drain and source electrodes 4 and 5 are electrically connected with the surface of the barrier layer 2, respectively.
• a gate electrode (G: control electrode) 6 consisting of Pt or Ni/Au is formed on the semiconductor layer 3.
• the gate electrode 6 is electrically connected with the surface of the semiconductor layer 3.
• An insulating film 7 is formed so as to continuously cover the above gate electrode 6 and the surrounding barrier layer 2.
• a field plate electrode 8 consisting of Ti/Al/Ni/Au is formed on the insulating film 7 so that it can be positioned between the gate electrode 6 and the drain electrode 4. The field plate electrode 8 electrically connected with the source electrode 5.
• the HEMT having the structure described above operates as a junction type FET in which the depth of a depletion layer formed in the surface region of the channel layer 1 is controlled in accordance with the voltage applied to the gate electrode 6.
• a current flowing between the source and drain electrode 5 and 4 is controlled in accordance with the depth of the depletion layer.
• nitride semiconductors such as Al ⁇ Ga ⁇ _ ⁇ N, Al ⁇ Ga]__ ⁇ N and AlzGa- j __zN having wide band gap are used as device material. Therefore, critical field is enhanced, so that high breakdown voltage of the device can be realized.
• the field plate electrode 8 is formed between the gate determining the breakdown voltage and the drain.
• the p-type semiconductor layer 3 is formed on the barrier layer 2; therefore, the following effect is obtained; namely, a gate leak current is reduced.
• the breakdown voltage is determined by an electric field generated in the Schottky junction of the gate.
• an electric field generated in the p-n junction between the p-type semiconductor layer 3 and the n-type barrier layer determines the above breakdown voltage.
• the field plate electrode 8 is connected with the source electrode 5, and thereby, gate/drain capacitance between becomes small; therefore, high-speed switching operation can be realized.
• AlQ.1Gao.9N layer is uniformly formed by crystal growth together with the channel layer 1 and the barrier layer 2. Thereafter, the semiconductor layer 3 may be patterned and formed by etching. Further, the semiconductor layer 3 is formed by crystal growth, thereafter, may be formed by selective oxidation process. Furthermore, the channel layer 1 and the barrier layer 2 are formed by crystal growth; thereafter; the semiconductor layer 3 may be formed on the surface of their layers by selective growth.
• FIG. 2 is a cross-sectional view schematically showing the structure of the power HEMT shown in FIG. 1 according to a first modification example.
• the dielectric layer 7 is formed so as to continuously cover the gate electrode 6 and the surrounding barrier layer 2, and the field plate electrode 8 is electrically connected to the source electrode 5.
• the power HEMT of FIG. 2 has the following structure. That is, the dielectric layer 7 is formed so that it can be positioned between the semiconductor layer 3 and the drain electrode 4 and is adjacent to the semiconductor layer 3.
• the gate electrode 6 is formed so as to extend to the dielectric layer 7 in addition to the upper surface of the semiconductor layer 3.
• the gate electrode 6 functions concurrently as the field plate electrode 8 shown in FIG. 1.
• the power HEMT of the modification example can obtain the same effects as FIG. 1, in addition, the field plate electrode and the gate electrode can be formed together. Therefore, the following effect is obtained; that is, manufacture process can be simplified as compared with FIG. 1. (Second modification example of first embodiment)
• FIG. 3 is a cross-sectional view schematically showing the structure of the power HEMT shown in FIG. 1 according to a second modification example.
• the power HEMT of FIG. 3 differs from that of FIG. 1 in that the gate electrode 6 is formed so as to extend to the surface of the barrier layer 2 adjacent to the side of the drain electrode 4 of the semiconductor layer 3. Namely, in the power HEMT of FIG. 3, the gate electrode 6 forms Schottky junction with the barrier layer 2.
• the gate electrode 6 makes Schottky connection with the barrier layer 2.
• the semiconductor layer 3 is connected with the gate electrode 6, holes are discharged via the semiconductor layer 3 in avalanche breakdown; therefore, high avalanche withstand capability is realized like the case of
• FIG. 1 Beside, the same effect as the case of FIG. 1 is obtained.
• FIG. 4 is a cross-sectional view schematically showing the structure of the power HEMT shown in FIG. 1 according to a third modification example.
• the gate electrode 6 is formed so as to extend to the surface of the barrier layer 2 adjacent to the side of the drain electrode 4 of the semiconductor layer 3.
• the power HEMT of FIG. 3 the gate electrode 6 is formed so as to extend to the surface of the barrier layer 2 adjacent to the side of the drain electrode 4 of the semiconductor layer 3.
• the gate electrode 6 is formed so as to extend to the surface of the barrier layer 2 adjacent to the source electrode 5 of the semiconductor layer 3.
• the gate electrode 6 makes Schottky connection with the barrier layer 2.
• the semiconductor layer 3 is connected with the gate electrode 6, holes are discharged via the semiconductor layer 3 in avalanche breakdown; therefore, high avalanche withstand capability is realized like the case of FIG. 1. Beside, the same effect as the case of FIG. 1 is obtained.
• FIG. 5 is a cross-sectional view schematically showing the structure of a junction type power HEMT according to a second embodiment of the present invention.
• the semiconductor layer 3 including the p-AlGaN layer is formed into the same length as the gate electrode 6. Namely, the end of the semiconductor layer 3 on the side of the drain electrode 4 is aligned in position with the end of the gate electrode 6 on the side of the same.
• the semiconductor layer 3 including the p-AlGaN layer is formed so that the end on the side of the drain electrode 4 can be extended from the end of the gate electrode 6 on the side of the drain electrode 4 toward the side of the drain electrode 4. Further, the semiconductor layer 3 is formed so that the end on the side of the drain electrode 4 can be positioned below the field plate electrode 8.
• FIG. 6A is a cross-sectional view enlarging the end portion of the semiconductor layer 3 of the power HEMT of FIG. 5, and FIG. 6B is a characteristic diagram showing electric field distribution in the barrier layer 2 when the power HEMT of FIG. 5 is operated.
• the semiconductor layer 3 is formed so that the end on the side of the drain electrode 4 can be positioned below the field plate electrode 8.
• the field concentrated points exist in the end of the semiconductor layer 3 and the end of field plate electrode 8.
• (line) 21 shows the case where the insulating film 7 is formed thick in some degree; on the other hand, the characteristic curve 22 shows the case where the insulating film 7 is formed thin in some degree.
• the dielectric layer 7 under the field plate electrode 8 is formed so as to have a proper thickness, and thereby, the point where avalanche breakdown occurs, that is, the electric field becomes highest, is set to the end of the semiconductor layer 3. Therefore, holes are speedily discharged in avalanche breakdown, so that sufficient avalanche withstand capability can be secured.
• FIG. 7A is a cross-sectional view enlarging the end portion of the semiconductor layer 3 of the power HEMT shown in FIG. 5.
• FIG. 7B is a characteristic diagram showing an electric field distribution in the horizontal direction when the power HEMT of FIG. 5 is operated.
• FIG. 7C is characteristic diagram showing an electric field distribution in the vertical direction when the power HEMT of FIG. 5 is operated. In FIG. 7B and FIG.
• the point of the end of the semiconductor layer 3 on the side of drain electrode 4 is set as A
• the point of the barrier layer 2 under the end of the field plate electrode 8 is set as B
• the point of the end of the field plate electrode 8 is set as C.
• the electric fields of above points A to C are set as Ej , Eg and E Q , respectively.
• the distance from the point A to B, that is, the length of the field plate electrode 8 is set as L
• the thickness of the insulating film 7 is set as t .
• a voltage V ⁇ B between the points A and B and a voltage V ⁇ B between the points C and B are expressed by the following equations (1) and (2), respectively.
• V AB (E A + E B ) L 2 - ( 1 )
• V CB E c t -(2)
• the potential of the field plate electrode 8 is approximately equal to that of the semiconductor layer 3; therefore, the voltage V ⁇ £ is equal to the voltage V CB .
• the relationship between the electric fields Eg and EQ is expressed by the following equation (3) .
• ⁇ i ' E C ⁇ s E B ••• (3)
• ⁇ j _ is dielectric constant (relative permittivity) of the dielectric layer 7
• 83 is dielectric constant of the barrier layer 2.
• the above equations (1) to (3) are modified so that the relationship between the electric fields E ⁇ and Eg can be determined.
• the above relationship is expressed by the following equation (4) .
• the electric field E A is set larger than the electric filed E B , and thereby, the avalanche withstand capability becomes large.
• the ratio of E A to E B expressed by the equation (4) is set larger than 1.
• the insulating film 7 consists of Si ⁇ 2, and the composition ratio of the barrier layer 2 including the AlGaN layer is set to 0.2, the dielectric constants ⁇ -j_ and 83 are 3.9 and 9.3, respectively. Therefore, it is desirable that the thickness t of the insulating film 7 is set to 0.83 ⁇ m or more.
• the critical field is close to a dielectric breakdown field of the insulating film. If the dielectric breakdown voltage of the insulating film 7 is smaller than the avalanche breakdown voltage, the dielectric breakdown voltage determines the device breakdown voltage. In this case, if the voltage equivalent to the device breakdown voltage is applied to the device, the device is broken down. If the critical field of the semiconductor layer is equal to the dielectric breakdown field of the insulating film, the electric field E Q of the point C shown in FIG. 7C is made smaller than the electric field E A of the point A shown in FIG. 7B. By doing so, it is possible to avoid dielectric breakdown.
• the ratio expressed by the above equation (6) becomes larger than 1, and thereby, it is possible to avoid dielectric breakdown. Therefore, it is desirable to set the thickness t of the insulating film 7 and the length L of the field plate electrode so that the following equation (7) can be satisfied.
• the insulating film 7 consists of Si ⁇ 2
• the composition ratio of the barrier layer 2 comprising the AlGaN layer is set to 0.2
• the dielectric constants ⁇ j_ and 8 3 are 3.9 and 9.3, respectively. Therefore, it is desirable that the thickness t of the insulating film 7 is set to 1.4 ⁇ m or more.
• FIG. 8 is a cross-sectional view schematically showing the structure of a junction type power HEMT according to a third embodiment of the present invention.
• the distance between gate and drain determines the breakdown voltage of the lateral type power device shown in FIG. 1; therefore, it is desirable to make long the above distance.
• the distance between source and gate having no relation with the breakdown voltage is shortened. This contributes for reducing ON resistance.
• the distance between gate and drain is set wider than the distance between gate and source in order to achieve high breakdown voltage and low ON resistance. More specifically, a distance Lgd is set wider than a distance Lgs .
• the distance Lgd is a length between the end of the gate electrode 6 on the side of the drain electrode 4 and the end of the drain electrode 4 on the side of the gate electrode 6.
• the distance Lgs is a length between the end of the gate electrode 6 on the side of the source electrode 5 and the end of the source electrode 5 on the side of the gate electrode 6.
• FIG. 8 shows the case where the end of the semiconductor layer 3 on the side of the drain electrode 4 is positioned below the field plate electrode 8.
• the third embodiment is not limited to the above arrangement, and as shown in FIG. 1, the semiconductor layer 3 may be formed so that the end on the side of the drain electrode 4 can be aligned with the end of the gate electrode 6.
• the gate electrode 6 may be formed so that it extends to the surface of the barrier layer 2 adjacent to the side of the drain electrode 4 of the semiconductor layer 3, or to the side of the source electrode 5 thereof.
• FIG. 9 is a cross-sectional view schematically showing the structure of a junction type power HEMT according to a fourth embodiment of the present invention.
• a back electrode 10 consisting of Pt is further formed on the surface of the semiconductor layer 3. In this case, the back electrode 10 is electrically connected with the source electrode 5.
• FIG. 10 is a cross-sectional view showing a modification example of the fourth embodiment.
• a thickness td of the channel layer 1 is set smaller than the distance Lgd between the gate electrode 6 and the drain electrode 4.
• the thickness of the channel layer 1 determines the breakdown voltage.
• the thickness of the channel layer 1 is controlled in crystal growth; therefore, it is possible to manufacture a deice having almost no variations of breakdown voltage.
• the concentration of impurities contained in the semiconductor layer 9 is made high; therefore, holes are speedily discharged, and consequently, high avalanche withstand capability can be expected.
• contact formed on the back surface of the channel layer 1 with respect to the semiconductor layer 9 is taken out of the back surface of substrate.
• the contact with respect to the semiconductor layer 9 may be taken out of the same surface as the source electrode 5. In this case, no conductive substrate is required.
• the p-type semiconductor layer 9 speedily discharges holes generated in the channel layer 1; therefore, it is desirable that the semiconductor layer 9 has a band gap same as or narrower than the channel layer 1. For this reason, it is desirable that a composition ratio W of the semiconductor layer 9 is the same as or smaller than a composition ratio X of the channel layer 1.
• FIG. 11 is a cross-sectional view schematically showing the structure of a lateral type GaN-MISFET according to a fifth embodiment of the present invention.
• a gate insulating film 11 is added to the HEMT shown in FIG. 5. More specifically, the gate insulating film 11 is formed so as to continuously cover the semiconductor layer 3 and the surrounding barrier layer 2.
• the gate electrode 6 is formed on the gate insulating film 11 positioned above the semiconductor layer 3. In this case, the gate insulating film 11 is partially formed with an opening portion so that the semiconductor layer 3 can be electrically connected with the gate electrode 6 via the opening portion.
• the surface of the channel layer 1 is formed with an inverted channel in accordance with a voltage applied to the gate electrode 6. A current flowing between the source electrode 5 and the drain electrode 4 is controlled in accordance with the forming state of the inverted channel.
• nitride semiconductors such as Al ⁇ Ga]__ ⁇ N, Al ⁇ Ga ⁇ _ ⁇ N and AlgGai-gN having wide band gap are used as device material.
• the field plate electrode 8 is formed between gate and drain determining the breakdown voltage. This serves to relieve the electric field applied between the gate electrode 6 and the drain electrode 4 when voltage is applied; therefore, it is possible to prevent the reduction of the breakdown voltage.
• Two-dimensional electron gas having high mobility is generated in the hetero-interface between the barrier layer 2 and the channel layer; therefore, low ON resistance is realized.
• the p-type semiconductor layer 3 is formed on the n-type barrier layer 2.
• the p-type semiconductor layer 3 is formed on the barrier layer 2; therefore, the following effect can be obtained such that a gate leak current is reduced.
• the electric field in the p-n junction between the p-type semiconductor layer 3 and the n-type barrier layer 2 determines the breakdown voltage. Since the breakdown point exists in the semiconductor layer, the following effect can be obtained such that non-uniformity of breakdown voltage is prevented.
• the breakdown point exists in the p-n junction of the semiconductor layer. Therefore, avalanche breakdown stably increases, and a device having high reliability can be realized.
• the field plate electrode 8 Since the field plate electrode 8 is connected with the source electrode 5, the capacitance between gate and drain becomes small; therefore, high-speed switching operation can be realized.
• the semiconductor layer 3 is electrically connected with the gate electrode 6; therefore, the following effect can be obtained, that is, it is possible to make small a gate leak current.
• FIG. 12 shows a MISFET according to a first modification example of the fifth embodiment.
• the gate insulating film 11 may be formed with no opening portion so that the semiconductor layer 3 can be isolated from the gate electrode 6.
• the MISFET has the above-mentioned structure, and thereby, it is possible to extremely reduce a gate leak current.
• the semiconductor layer 3 is not electrically connected with the gate electrode so that it becomes a potentially floating state, and thereby, holes are not discharged into the semiconductor layer 3.
• the source electrode 5 is formed so that it can be partially extended to the upper portion of the semiconductor layer 3.
• the semiconductor layer 3 is electrically connected with the source electrode 5. Therefore, avalanche current flows into the source electrode 5 via the semiconductor layer 3; however, it does not flow into the gate electrode 6. This serves to reduce a load to a gate drive circuit for driving the gate electrode 6.
• the following films are preferably used as the gate insulating film 11.
• the films include oxide films such as l ⁇ Ga2- ⁇ 3 film oxidizing an AlGaN layer, insulating films such as AI2O 3 , SiN deposited by CVD process, etc. If impurity concentration of the semiconductor layer 3 is too high, this is a factor of deteriorating the control characteristic of inverted channel generated by the voltage applied to the gate electrode. In other words, mutual conductance of the gate electrode 6 becomes small. Conversely, if the impurity concentration of the semiconductor layer 3 is too low, discharge resistance becomes large when discharging hole. Therefore, considering both viewpoints described above, it is desirable that the impurity concentration of the semiconductor layer 3 is set to the same as that of the barrier layer 2.
• FIG. 13A and FIG. 13B are a cross-sectional view and a top plan view schematically showing the structure according to a second modification example of the power MISFET shown in FIG. 12.
• the semiconductor layer 3 has been formed over the entire surface in the gate widthwise direction.
• the semiconductor layer 3 is formed like a shape of rectangle in the gate widthwise direction.
• the semiconductor layer 3 has the above shape, and thereby, control of gate threshold voltage and ON resistance is possible.
• the semiconductor layer 3 is formed into a shape of rectangle, and thereby, there are formed both portions where the semiconductor layer 3 is formed and is not formed under the gate.
• the gate threshold voltage is high, and in addition, channel resistance and offset resistance between gate and source are large.
• the gate threshold voltage is low, and in addition, channel resistance and offset resistance between gate and source are small.
• the former and latter portions are operated in parallel; therefore, the threshold voltage or ON resistance is controllable by changing the interval between rectangular-shaped semiconductor layers 3 and the density.
• FIG. 14 is a cross-sectional view schematically showing the structure of a lateral type GaN-Schottky barrier diode (SBD) according to a sixth embodiment of the present invention.
• SBD lateral type GaN-Schottky barrier diode
• the SBD is provided with the channel layer 1 including a non-doped GaN layer, like the FET shown in FIG. 1.
• the barrier layer 2 including the n-type
• An anode electrode (A: second electrode) 12 consisting of Ni/Au is formed so as to continuously cover the above semiconductor layers 3 and the surrounding barrier layer 2.
• the insulating film 7 is formed on the barrier layer 2 so as to contact with the anode electrode 12.
• the field plate electrode 8 consisting of Ni/Au is formed on the insulating film 7.
• the field plate electrode 8 is electrically connected with the anode electrode 12.
• a cathode electrode (K: first electrode) 13 consisting of Ti/Al/Ni/Au is formed on the barrier layer 2 in a state of separating from the above anode electrode 12.
• the n-AlGaN/GaN hetero-structure including the barrier layer 2 and the channel layer 1 is employed like the HEMT described before. By doing so, it is possible to realize high breakdown voltage and ultra-low ON resistance.
• the semiconductor layer 3 including the p-AlGaN layer is formed on the barrier layer 2 including the n-AlGaN layer. By doing so, holes are securely discharged when avalanche breakdown occurs; therefore, high voltage effect can be expected.
• the semiconductor layer 3 is formed in the above manner, and thereby, it is possible to reduce a Schottky junction area directly contacting the anode electrode 12 with barrier layer, and to reduce a reverse leakage current. (Seventh embodiment)
• FIG. 15 is a cross-sectional view schematically showing the structure of a Schottky barrier diode (SBD) according to a seventh embodiment of the present invention.
• the semiconductor layer 3 is formed at the Schottky junction end.
• the end of the semiconductor layer 3 on the side of the cathode electrode 13 is positioned between the end of the field plate electrode 8 on the side of the cathode electrode 13 and the end of the anode electrode 12 on the side of the cathode electrode 13.
• FIG. 16A and are a cross-sectional view enlarging the end of the semiconductor layer 3 shown in FIG. 15, and FIG. 16B is a characteristic diagram showing an electric field distribution in the barrier layer 2 when the SBD of FIG. 15 is operated.
• the semiconductor layer 3 is formed so that the end portion on the side of the cathode electrode 13 can be positioned below the filed plate electrode 8. By doing so, the field concentrated points exists at the end of the semiconductor layer 3 and at the end of the field plate electrode 8, as seen from FIG. 16B.
• the characteristic curve 23 shows the case where the insulating film 7 is formed thick in some degree; on the other hand, the characteristic curve 24 shows the case where the insulating film 7 is formed thin in some degree.
• the thickness t of the insulating film 7 is set so that the above relative equations (5) and (7) can be satisfied, as described in the HEMT of the above second embodiment. By doing so, it is possible to secure avalanche withstand capability, and to avoid the dielectric breakdown.
• the present invention has been described based on the first to seventh embodiments. Incidentally, the present invention is not limited to the above embodiments, and besides, modifications readily imaged by skilled persons in the art are all applicable.
• the semiconductor layer 3 including the p-AlGaN layer used for discharging holes has the band gap narrower than that of the barrier layer 2 including the n-AlGaN layer in the light of holes discharge.
• the composition ratio of Al is small, and p-GaN layer may be used.
• a semiconductor layer such as an InGaN layer having a narrow band gap is used as a contact layer.
• the contact layer may be formed between the gate electrode 6 or anode electrode 12 and the semiconductor layer 3.
• the combination of AlGaN/GaN has been employed as the device material.
• the combination of GaN/ InGaN or AlN/AlGaN may be employed.
• the present invention is not limited to unipolar devices such as junction type FET.
• the present invention is readily applicable to bipolar devices such as pin diodes and IGBTs provided with a p-layer on the drain side of MISFET so long as the device is a lateral type.

Landscapes

• Junction Field-Effect Transistors (AREA)
• Electrodes Of Semiconductors (AREA)
• Insulated Gate Type Field-Effect Transistor (AREA)

Priority Applications (5)

Applications Claiming Priority (1)

Related Child Applications (1)

Publications (1)

Family

ID=32800805

Family Applications (1)

Country Status (4)

Cited By (37)

Families Citing this family (36)

Citations (3)

Family Cites Families (4)

• 2003
  • 2003-01-29 WO PCT/JP2003/000843 patent/WO2004068590A1/en active IP Right Grant
  • 2003-01-29 CN CNB038052059A patent/CN100388509C/zh not_active Expired - Fee Related
  • 2003-01-29 KR KR1020047013050A patent/KR100573720B1/ko not_active Expired - Fee Related
  • 2003-01-29 JP JP2004567520A patent/JP4568118B2/ja not_active Expired - Lifetime

Patent Citations (3)

Non-Patent Citations (3)

Also Published As

Similar Documents

Legal Events