[go: up one dir, main page]

JPH04359518A - 半導体装置の製造方法 - Google Patents

半導体装置の製造方法

Info

Publication number
JPH04359518A
JPH04359518A JP3134544A JP13454491A JPH04359518A JP H04359518 A JPH04359518 A JP H04359518A JP 3134544 A JP3134544 A JP 3134544A JP 13454491 A JP13454491 A JP 13454491A JP H04359518 A JPH04359518 A JP H04359518A
Authority
JP
Japan
Prior art keywords
wiring
layer
silicon oxide
power supply
insulating film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3134544A
Other languages
English (en)
Inventor
Takashi Inaba
稲葉　孝
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP3134544A priority Critical patent/JPH04359518A/ja
Priority to EP92305240A priority patent/EP0517551B1/en
Priority to US07/895,551 priority patent/US5242861A/en
Priority to DE69218664T priority patent/DE69218664T2/de
Publication of JPH04359518A publication Critical patent/JPH04359518A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
    • H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05117—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
    • H01L2224/05124—Aluminium [Al] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/05001—Internal layers
    • H01L2224/05099—Material
    • H01L2224/051—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05163—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
    • H01L2224/05166—Titanium [Ti] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/05599—Material
    • H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/05644—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/03—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/02—Bonding areas ; Manufacturing methods related thereto
    • H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/00013—Fully indexed content
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01005—Boron [B]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01013—Aluminum [Al]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01018—Argon [Ar]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01022—Titanium [Ti]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01029—Copper [Cu]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01078—Platinum [Pt]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】
【０００１】
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特に多層配線の形成方法に関する。
【０００２】
【従来の技術】従来の多層配線を有する半導体装置の製
造方法は、図３（ａ）に示すように、シリコン基板１の
上に設けた酸化シリコン膜２の上にアルミニウム層を堆
積してパターニングし、幅２μｍ，厚さ０．５μｍの下
層の配線３を形成する。次に、配線３を含む表面にシリ
カ粉末を混入させたポリイミド系樹脂膜等の有機膜を塗
布法により形成して表面を平坦化した層間絶縁膜４を形
成し、選択的に開孔して配線３の上にコンタクトホール
を形成する。次に、コンタクトホールを含む表面にＴｉ
−Ｗ層等のバリアメタル層５及び金層６を夫々０．１μ
ｍの厚さに順次スパッタして電気めっき用の給電層を形
成する。
【０００３】次に、図３（ｂ）に示すように、金層６の
上にフォトレジスト膜９を形成してパターニングし、コ
ンタクトホールを含む配線形成用の溝を形成する。次に
、給電層によりフォトレジスト膜９をマスクとして金層
を電気めっきする。
【０００４】次に、図３（ｃ）に示すように、フォトレ
ジスト膜９を除去して上層の配線７を形成した後、配線
７をマスクとしてＡｒなどの不活性ガスを用いてスパッ
タエッチングし、金層６及びバリアメタル層５を順次エ
ッチング除去していた。
【０００５】
【発明が解決しようとする課題】この従来の半導体装置
の製造方法では、金めっきによる上層配線を形成した後
に、不要な部分の給電層を除去するために、Ａｒなどの
不活性ガスを用いたスパッタエッチングをしていたため
、エッチングされた給電層の金属の一部が堆積物となっ
て上層配線の側壁に付着していた。この付着した堆積物
が後工程で上層配線の側壁から一部が剥れて、隣接する
上層配線間を短絡させてしまい歩留りの低下や信頼性を
低下させるという問題点があった。
【０００６】
【課題を解決するための手段】本発明の半導体装置の製
造方法は、半導体基板上に層間絶縁膜を設けて上面を平
坦化する工程と、前記層間絶縁膜に選択的に設けたコン
タクトホールを含む表面に電気めっき用の給電層を形成
する工程と、前記給電層の上にフォトレジスト膜を設け
てパターニングし配線形成用の溝を形成する工程と、前
記フォトレジスト膜をマスクとして電気めっき法により
前記給電層上に金属層を堆積して前記溝内に配線を形成
する工程と、前記フォトレジスト膜を除去した後前記配
線を含む表面にＣＶＤ法により絶縁膜を形成してエッチ
バックし前記配線の側壁にのみ前記絶縁膜を残して前記
給電層の表面を露出させる工程と、前記配線及び絶縁膜
をマスクとして前記給電層をエッチング除去した後前記
絶縁膜をエッチング除去する工程とを含んで構成される
。
【０００７】
【実施例】次に、本発明について図面を参照して説明す
る。
【０００８】図１（ａ）〜（ｃ）は本発明の第１の実施
例を説明するための工程順に示した半導体チップの断面
図である。
【０００９】まず、図１（ａ）に示すように、シリコン
基板１の上に設けた酸化シリコン膜２の上に図３（ａ）
，（ｂ）により説明した従来例と同様の工程で、金属を
めっきし、フォトレジスト膜９を剥離して上層の配線７
を形成した後、配線７を含む表面にプラズマＣＶＤ法に
より酸化シリコン膜８を０．２μｍの厚さに堆積する。
【００１０】次に、図１（ｂ）に示すように、異方性エ
ッチングによりエッチバックして配線７の側壁以外の酸
化シリコン膜８を除去した後、配線７及び酸化シリコン
膜８をマスクとして金層６及びバリアメタル層５を、Ａ
ｒなどの不活性ガスを用いたスパッタエッチングにより
順次エッチングして除去する。この際に、除去した金属
の一部が堆積物となって配線７の側壁の酸化シリコン膜
８の側面に付着してしまうことがある。
【００１１】次に、図１（ｃ）に示すように、堆積物の
付着した酸化シリコン膜８を希釈弗酸液によりエッチン
グして除去する。
【００１２】なお、酸化シリコン膜８の代りに、プラズ
マＣＶＤ法で窒化シリコン膜を堆積しても良く、配線７
の側壁にのみ残した窒化シリコン膜を金属の堆積物と共
にＣＦ４　ガス等の等方性ドライエッチングにより、容
易に除去することができる利点がある。また配線７を金
めっき層の代りに銅めっき層で形成しても良い。
【００１３】図２は本発明の第２の実施例を示す半導体
チップの断面図である。
【００１４】図２に示すように、酸化シリコン膜８をマ
スクとして金層６及びバリアメタル層５を順次スパッタ
エッチングで除去した後、更に金層６を王水で、バリア
メタル層５をＨ２　Ｏ２　溶液でウェットエッチングし
、酸化シリコン膜８に付着した堆積物の大部分をエッチ
ングする。次に、酸化シリコン膜８をウェットエッチン
グ（希釈弗酸など）により付着していた堆積物の残りも
同時に除去する以外は第１の実施例と同様の工程を含ん
で構成され、スパッタエッチングにより発生した堆積物
をさらに完全に除去することができる。
【００１５】
【発明の効果】以上説明したように本発明は、電気めっ
きで形成した上層配線の側壁に絶縁膜を形成した後に、
電気めっきの給電層をスパッタエッチングで除去し、次
に、エッチングの際に発生する堆積物の付着した絶縁膜
をエッチングして除去することにより、堆積物も同時に
除去されるため、後工程で堆積物が剥れて隣接する配線
間を短絡させることを防止でき、歩留り及び信頼性を向
上させるという効果を有する。
【図面の簡単な説明】
【図１】本発明の第１の実施例を説明するための工程順
に示した半導体チップの断面図。
【図２】本発明の第２の実施例を説明するための半導体
チップの断面図。
【図３】従来の半導体装置の製造方法の一例を説明する
ための工程順に示した半導体チップの断面図。
【符号の説明】
１　　　　シリコン基板 ２，８　　　　酸化シリコン膜 ３，７　　　　配線 ４　　　　層間絶縁膜 ５　　　　バリアメタル層 ６　　　　金層 ９　　　　フォトレジスト膜

Claims (1)

    【特許請求の範囲】
  1. 【請求項１】　　半導体基板上に層間絶縁膜を設けて上
    面を平坦化する工程と、前記層間絶縁膜に選択的に設け
    たコンタクトホールを含む表面に電気めっき用の給電層
    を形成する工程と、前記給電層の上にフォトレジスト膜
    を設けてパターニングし配線形成用の溝を形成する工程
    と、前記フォトレジスト膜をマスクとして電気めっき法
    により前記給電層上に金属層を堆積して前記溝内に配線
    を形成する工程と、前記フォトレジスト膜を除去した後
    前記配線を含む表面にＣＶＤ法により絶縁膜を形成して
    エッチバックし前記配線の側壁にのみ前記絶縁膜を残し
    て前記給電層の表面を露出させる工程と、前記配線及び
    絶縁膜をマスクとして前記給電層をエッチング除去した
    後前記絶縁膜をエッチング除去する工程とを含むことを
    特徴とする半導体装置の製造方法。
JP3134544A 1991-06-06 1991-06-06 半導体装置の製造方法 Pending JPH04359518A (ja)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP3134544A JPH04359518A (ja) 1991-06-06 1991-06-06 半導体装置の製造方法
EP92305240A EP0517551B1 (en) 1991-06-06 1992-06-08 Method of forming a multilayer wiring structure on a semiconductor device
US07/895,551 US5242861A (en) 1991-06-06 1992-06-08 Method for manufacturing semiconductor device having a multilayer wiring structure
DE69218664T DE69218664T2 (de) 1991-06-06 1992-06-08 Herstellungsverfahren von einer Mehrschichtleiterbahn-Struktur über einer Halbleiteranordung

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3134544A JPH04359518A (ja) 1991-06-06 1991-06-06 半導体装置の製造方法

Publications (1)

Publication Number Publication Date
JPH04359518A true JPH04359518A (ja) 1992-12-11

Family

ID=15130801

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3134544A Pending JPH04359518A (ja) 1991-06-06 1991-06-06 半導体装置の製造方法

Country Status (4)

Country Link
US (1) US5242861A (ja)
EP (1) EP0517551B1 (ja)
JP (1) JPH04359518A (ja)
DE (1) DE69218664T2 (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014107404A (ja) * 2012-11-27 2014-06-09 Mitsubishi Electric Corp 配線構造の製造方法

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5334804A (en) * 1992-11-17 1994-08-02 Fujitsu Limited Wire interconnect structures for connecting an integrated circuit to a substrate
US5348894A (en) 1993-01-27 1994-09-20 Texas Instruments Incorporated Method of forming electrical connections to high dielectric constant materials
JP2951215B2 (ja) * 1993-09-10 1999-09-20 レイセオン・カンパニー 位相マスクレーザによる微細なパターンの電子相互接続構造の製造方法
DE4331185C1 (de) * 1993-09-14 1994-12-15 Siemens Ag Verfahren zur Kontaktlochauffüllung in einem Halbleiterschichtaufbau
KR0134108B1 (ko) * 1994-06-30 1998-04-20 김주용 반도체 소자의 제조방법
JP3000877B2 (ja) * 1995-02-20 2000-01-17 松下電器産業株式会社 金メッキ電極の形成方法、基板及びワイヤボンディング方法
US20070122997A1 (en) 1998-02-19 2007-05-31 Silicon Genesis Corporation Controlled process and resulting device
US6033974A (en) 1997-05-12 2000-03-07 Silicon Genesis Corporation Method for controlled cleaving process
EP0995227A4 (en) * 1997-05-12 2000-07-05 Silicon Genesis Corp CONTROLLED CLEAVAGE PROCESS
US6291313B1 (en) 1997-05-12 2001-09-18 Silicon Genesis Corporation Method and device for controlled cleaving process
US6146979A (en) 1997-05-12 2000-11-14 Silicon Genesis Corporation Pressurized microbubble thin film separation process using a reusable substrate
US6548382B1 (en) 1997-07-18 2003-04-15 Silicon Genesis Corporation Gettering technique for wafers made using a controlled cleaving process
DE19732250A1 (de) * 1997-07-26 1999-01-28 Bosch Gmbh Robert Verfahren zur Herstellung metallischer Mikrostrukturen
FR2769122B1 (fr) * 1997-09-29 2001-04-13 Commissariat Energie Atomique Procede pour augmenter la frequence de fonctionnement d'un circuit magnetique et circuit magnetique correspondant
US6030877A (en) * 1997-10-06 2000-02-29 Industrial Technology Research Institute Electroless gold plating method for forming inductor structures
US6228757B1 (en) * 1998-03-05 2001-05-08 Philips Semiconductors, Inc. Process for forming metal interconnects with reduced or eliminated metal recess in vias
US6291326B1 (en) 1998-06-23 2001-09-18 Silicon Genesis Corporation Pre-semiconductor process implant and post-process film separation
US6046107A (en) * 1998-12-17 2000-04-04 Industrial Technology Research Institute Electroless copper employing hypophosphite as a reducing agent
US6221740B1 (en) 1999-08-10 2001-04-24 Silicon Genesis Corporation Substrate cleaving tool and method
EP1939932A1 (en) 1999-08-10 2008-07-02 Silicon Genesis Corporation A substrate comprising a stressed silicon germanium cleave layer
US6263941B1 (en) 1999-08-10 2001-07-24 Silicon Genesis Corporation Nozzle for cleaving substrates
US6500732B1 (en) 1999-08-10 2002-12-31 Silicon Genesis Corporation Cleaving process to fabricate multilayered substrates using low implantation doses
US6080656A (en) * 1999-09-01 2000-06-27 Taiwan Semiconductor Manufacturing Company Method for forming a self-aligned copper structure with improved planarity
US6511912B1 (en) * 2000-08-22 2003-01-28 Micron Technology, Inc. Method of forming a non-conformal layer over and exposing a trench
US8187377B2 (en) 2002-10-04 2012-05-29 Silicon Genesis Corporation Non-contact etch annealing of strained layers
US7902062B2 (en) * 2002-11-23 2011-03-08 Infineon Technologies Ag Electrodepositing a metal in integrated circuit applications
WO2004101857A2 (en) * 2003-05-07 2004-11-25 Microfabrica Inc. Methods and apparatus for forming multi-layer structures using adhered masks
US10297421B1 (en) 2003-05-07 2019-05-21 Microfabrica Inc. Plasma etching of dielectric sacrificial material from reentrant multi-layer metal structures
TWI286372B (en) * 2003-08-13 2007-09-01 Phoenix Prec Technology Corp Semiconductor package substrate with protective metal layer on pads formed thereon and method for fabricating the same
JP2005183567A (ja) * 2003-12-18 2005-07-07 Matsushita Electric Ind Co Ltd 半導体集積回路の製造方法、ヴィアホール形成用共用マスクおよび半導体集積回路
KR100661220B1 (ko) * 2004-12-29 2006-12-22 동부일렉트로닉스 주식회사 듀얼 절연막을 이용한 금속 배선 형성 방법
US8993410B2 (en) 2006-09-08 2015-03-31 Silicon Genesis Corporation Substrate cleaving under controlled stress conditions
US7811900B2 (en) 2006-09-08 2010-10-12 Silicon Genesis Corporation Method and structure for fabricating solar cells using a thick layer transfer process
US9362439B2 (en) 2008-05-07 2016-06-07 Silicon Genesis Corporation Layer transfer of films utilizing controlled shear region
US8293619B2 (en) 2008-08-28 2012-10-23 Silicon Genesis Corporation Layer transfer of films utilizing controlled propagation
US20090184425A1 (en) * 2008-01-17 2009-07-23 Advanced Chip Engineering Technology Inc. Conductive line structure and the method of forming the same
US8330126B2 (en) 2008-08-25 2012-12-11 Silicon Genesis Corporation Race track configuration and method for wafering silicon solar substrates
KR101426038B1 (ko) * 2008-11-13 2014-08-01 주식회사 엠디에스 인쇄회로기판 및 그 제조방법
US8329557B2 (en) 2009-05-13 2012-12-11 Silicon Genesis Corporation Techniques for forming thin films by implantation with reduced channeling
KR20160052463A (ko) * 2013-06-28 2016-05-12 인텔 코포레이션 미세 피치 재분배 라인들의 보존

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3997963A (en) * 1973-06-29 1976-12-21 Ibm Corporation Novel beam-lead integrated circuit structure and method for making the same including automatic registration of beam-leads with corresponding dielectric substrate leads
US3993515A (en) * 1975-03-31 1976-11-23 Rca Corporation Method of forming raised electrical contacts on a semiconductor device
JPS60140737A (ja) * 1983-12-27 1985-07-25 Seiko Instr & Electronics Ltd 半導体装置の製造方法
JPS614248A (ja) * 1984-06-19 1986-01-10 Nec Kansai Ltd バンプ電極の形成方法
JPS61183945A (ja) * 1985-02-08 1986-08-16 Nippon Denso Co Ltd 半導体装置
JPS63146451A (ja) * 1986-10-23 1988-06-18 Mitsubishi Electric Corp 配線パタ−ン形成方法
JPH01120848A (ja) * 1987-11-05 1989-05-12 Seiko Epson Corp 半導体装置及びその製造方法
JPH0228932A (ja) * 1988-07-19 1990-01-31 Fujitsu Ltd 半導体装置
JP2610337B2 (ja) * 1989-02-25 1997-05-14 富士通株式会社 パターン形成方法
GB2233820A (en) * 1989-06-26 1991-01-16 Philips Nv Providing an electrode on a semiconductor device
US5098860A (en) * 1990-05-07 1992-03-24 The Boeing Company Method of fabricating high-density interconnect structures having tantalum/tantalum oxide layers
US5130275A (en) * 1990-07-02 1992-07-14 Digital Equipment Corp. Post fabrication processing of semiconductor chips

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2014107404A (ja) * 2012-11-27 2014-06-09 Mitsubishi Electric Corp 配線構造の製造方法

Also Published As

Publication number Publication date
DE69218664T2 (de) 1997-07-10
US5242861A (en) 1993-09-07
DE69218664D1 (de) 1997-05-07
EP0517551A3 (en) 1993-10-13
EP0517551B1 (en) 1997-04-02
EP0517551A2 (en) 1992-12-09

Similar Documents

Publication Publication Date Title
JPH04359518A (ja) 半導体装置の製造方法
JPH05206064A (ja) 半導体装置の製造方法
JPH04290232A (ja) 溝埋込み配線形成方法
JPH0669351A (ja) 多層金属配線構造のコンタクトの製造方法
JP3367490B2 (ja) 半導体装置の製造方法
JPH11251433A (ja) 半導体装置およびその製法
JPH03248429A (ja) 半導体装置の製造方法
KR20030074870A (ko) 반도체 소자의 금속 배선 형성 방법
JP3033171B2 (ja) 半導体装置の製造方法
JPH0570301B2 (ja)
JPH08288385A (ja) 半導体装置の製造方法
JP3166912B2 (ja) 半導体装置の製造方法
JP3036086B2 (ja) 半導体装置の製造方法
JPH04307737A (ja) 半導体装置の製造方法
JPS62249451A (ja) 多層配線構造体の製造法
JP3049872B2 (ja) 半導体装置の製造方法
JP2000277522A (ja) 半導体装置とその製造方法
JPH0684908A (ja) 半導体装置およびその製造方法
JPH09232424A (ja) 半導体装置の製造方法
JPH02152255A (ja) 多層配線の形成方法
KR20040001851A (ko) 반도체소자의 다층 구리 배선 형성 방법
JPS63312658A (ja) 半導体装置の製造方法
JPH03248533A (ja) 半導体集積回路装置
JPH0594985A (ja) 半導体装置の製造方法
JPH07106325A (ja) 半導体装置の製造方法