KR100661220B1 - 듀얼 절연막을 이용한 금속 배선 형성 방법 - Google Patents
듀얼 절연막을 이용한 금속 배선 형성 방법 Download PDFInfo
- Publication number
- KR100661220B1 KR100661220B1 KR1020040115538A KR20040115538A KR100661220B1 KR 100661220 B1 KR100661220 B1 KR 100661220B1 KR 1020040115538 A KR1020040115538 A KR 1020040115538A KR 20040115538 A KR20040115538 A KR 20040115538A KR 100661220 B1 KR100661220 B1 KR 100661220B1
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- Prior art keywords
- metal wiring
- insulating film
- forming
- substrate
- metal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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- 229910052751 metal Inorganic materials 0.000 title claims abstract description 71
- 239000002184 metal Substances 0.000 title claims abstract description 71
- 238000000034 method Methods 0.000 title abstract description 32
- 230000009977 dual effect Effects 0.000 title abstract description 11
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 239000000463 material Substances 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims abstract description 17
- 238000001465 metallisation Methods 0.000 claims abstract description 9
- 238000000059 patterning Methods 0.000 claims description 4
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims 1
- 238000004544 sputter deposition Methods 0.000 abstract description 8
- 238000000151 deposition Methods 0.000 abstract description 3
- 230000008021 deposition Effects 0.000 abstract description 3
- 230000000694 effects Effects 0.000 abstract description 3
- 238000009413 insulation Methods 0.000 abstract 1
- 239000012212 insulator Substances 0.000 abstract 1
- 239000010410 layer Substances 0.000 description 14
- 238000005229 chemical vapour deposition Methods 0.000 description 4
- 238000005530 etching Methods 0.000 description 4
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 229910000881 Cu alloy Inorganic materials 0.000 description 2
- WPPDFTBPZNZZRP-UHFFFAOYSA-N aluminum copper Chemical compound [Al].[Cu] WPPDFTBPZNZZRP-UHFFFAOYSA-N 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 239000002356 single layer Substances 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76885—By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
Description
Claims (7)
- 삭제
- 삭제
- 기판상에 소정 간격을 갖도록 제 1절연막 패턴을 형성하는 단계;상기 제 1절연막 패턴이 형성된 기판상에 금속 배선 물질을 형성하는 단계;상기 금속 배선 물질의 상부면을 평탄화하는 단계;상기 금속 배선 물질을 패터닝하여 상기 제 1절연막보다 소정 높이 돌출되도록 하고, 상기 제 1절연막이 없는 기판상의 영역에 금속 배선을 형성하는 단계;상기 금속 배선이 형성된 패턴 및 제 1절연막 상부에 제 2절연막을 형성하는 단계; 및상기 제 2절연막 상에 소정 두께의 캐핑 레이어를 형성하는 단계;가 포함되고,상기 제1절연막은 금속 배선 높이의 1/3내지 2/3의 높이를 갖는 것을 특징으로 하는 듀얼 절연막을 이용한 금속 배선 형성 방법.
- 삭제
- 기판상에 소정 간격을 갖도록 제 1절연막 패턴을 형성하는 단계;상기 제 1절연막 패턴이 형성된 기판상에 금속 배선 물질을 형성하는 단계;상기 금속 배선 물질의 상부면을 평탄화하는 단계;상기 금속 배선 물질을 패터닝하여 상기 제 1절연막보다 소정 높이 돌출되도록 하고, 상기 제 1절연막이 없는 기판상의 영역에 금속 배선을 형성하는 단계;상기 금속 배선이 형성된 패턴 및 제 1절연막 상부에 제 2절연막을 형성하는 단계; 및상기 제 2절연막 상에 소정 두께의 캐핑 레이어를 형성하는 단계;가 포함되고,상기 제1절연막 패턴간의 간격은 상기 금속 배선의 폭과 같음을 특징으로 하는 듀얼 절연막을 이용한 금속 배선 형성 방법.
- 삭제
- 기판상에 소정 간격을 갖도록 제 1절연막 패턴을 형성하는 단계;상기 제 1절연막 패턴이 형성된 기판상에 금속 배선 물질을 형성하는 단계;상기 금속 배선 물질의 상부면을 평탄화하는 단계;상기 금속 배선 물질을 패터닝하여 상기 제 1절연막보다 소정 높이 돌출되도록 하고, 상기 제 1절연막이 없는 기판상의 영역에 금속 배선을 형성하는 단계;상기 금속 배선이 형성된 패턴 및 제 1절연막 상부에 제 2절연막을 형성하는 단계; 및상기 제 2절연막 상에 소정 두께의 캐핑 레이어를 형성하는 단계;가 포함되고,상기 제2절연막은 고밀도 플라즈마 CVD 방법으로 형성됨을 특징으로 하는 듀얼 절연막을 이용한 금속 배선 형성 방법.
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040115538A KR100661220B1 (ko) | 2004-12-29 | 2004-12-29 | 듀얼 절연막을 이용한 금속 배선 형성 방법 |
US11/320,408 US7517799B2 (en) | 2004-12-29 | 2005-12-29 | Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer |
US12/397,169 US20090165706A1 (en) | 2004-12-29 | 2009-03-03 | Method for forming a plurality of metal lines in a semiconductor device using dual insulating layer |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1020040115538A KR100661220B1 (ko) | 2004-12-29 | 2004-12-29 | 듀얼 절연막을 이용한 금속 배선 형성 방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20060076913A KR20060076913A (ko) | 2006-07-05 |
KR100661220B1 true KR100661220B1 (ko) | 2006-12-22 |
Family
ID=36971587
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
KR1020040115538A Expired - Fee Related KR100661220B1 (ko) | 2004-12-29 | 2004-12-29 | 듀얼 절연막을 이용한 금속 배선 형성 방법 |
Country Status (2)
Country | Link |
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US (2) | US7517799B2 (ko) |
KR (1) | KR100661220B1 (ko) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8030215B1 (en) * | 2008-02-19 | 2011-10-04 | Marvell International Ltd. | Method for creating ultra-high-density holes and metallization |
US12142562B2 (en) | 2021-06-22 | 2024-11-12 | International Business Machines Corporation | Subtractive metal etch with improved isolation for BEOL interconnect and cross point |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0156124B1 (ko) * | 1994-10-20 | 1998-12-01 | 문정환 | 반도체소자의 금속배선 형성방법 |
JPH1131692A (ja) * | 1997-07-10 | 1999-02-02 | Oki Electric Ind Co Ltd | 半導体素子の配線の製造方法 |
Family Cites Families (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4702792A (en) * | 1985-10-28 | 1987-10-27 | International Business Machines Corporation | Method of forming fine conductive lines, patterns and connectors |
JPH04359518A (ja) * | 1991-06-06 | 1992-12-11 | Nec Corp | 半導体装置の製造方法 |
US6284591B1 (en) * | 1995-11-02 | 2001-09-04 | Samsung Electromics Co., Ltd. | Formation method of interconnection in semiconductor device |
US5763010A (en) * | 1996-05-08 | 1998-06-09 | Applied Materials, Inc. | Thermal post-deposition treatment of halogen-doped films to improve film stability and reduce halogen migration to interconnect layers |
JPH10163192A (ja) * | 1996-10-03 | 1998-06-19 | Fujitsu Ltd | 半導体装置およびその製造方法 |
US6740950B2 (en) * | 2001-01-15 | 2004-05-25 | Amkor Technology, Inc. | Optical device packages having improved conductor efficiency, optical coupling and thermal transfer |
US6977435B2 (en) * | 2003-09-09 | 2005-12-20 | Intel Corporation | Thick metal layer integrated process flow to improve power delivery and mechanical buffering |
-
2004
- 2004-12-29 KR KR1020040115538A patent/KR100661220B1/ko not_active Expired - Fee Related
-
2005
- 2005-12-29 US US11/320,408 patent/US7517799B2/en active Active
-
2009
- 2009-03-03 US US12/397,169 patent/US20090165706A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR0156124B1 (ko) * | 1994-10-20 | 1998-12-01 | 문정환 | 반도체소자의 금속배선 형성방법 |
JPH1131692A (ja) * | 1997-07-10 | 1999-02-02 | Oki Electric Ind Co Ltd | 半導体素子の配線の製造方法 |
Non-Patent Citations (2)
Title |
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1001561240000 * |
11031692 * |
Also Published As
Publication number | Publication date |
---|---|
US7517799B2 (en) | 2009-04-14 |
US20060205212A1 (en) | 2006-09-14 |
KR20060076913A (ko) | 2006-07-05 |
US20090165706A1 (en) | 2009-07-02 |
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