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CN2704927Y - 可同时具有部分空乏晶体管与完全空乏晶体管的芯片 - Google Patents

可同时具有部分空乏晶体管与完全空乏晶体管的芯片 Download PDF

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CN2704927Y
CN2704927Y CNU2004200483757U CN200420048375U CN2704927Y CN 2704927 Y CN2704927 Y CN 2704927Y CN U2004200483757 U CNU2004200483757 U CN U2004200483757U CN 200420048375 U CN200420048375 U CN 200420048375U CN 2704927 Y CN2704927 Y CN 2704927Y
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transistor
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杨育佳
陈豪育
黄健朝
李文钦
杨富量
胡正明
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Taiwan Semiconductor Manufacturing Co TSMC Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/024—Manufacture or treatment of FETs having insulated gates [IGFET] of fin field-effect transistors [FinFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/62—Fin field-effect transistors [FinFET]
    • H10D30/6212—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections
    • H10D30/6213—Fin field-effect transistors [FinFET] having fin-shaped semiconductor bodies having non-rectangular cross-sections having rounded corners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/791—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions
    • H10D30/792—Arrangements for exerting mechanical stress on the crystal lattice of the channel regions comprising applied insulating layers, e.g. stress liners
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
    • H10D86/201—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates the substrates comprising an insulating layer on a semiconductor body, e.g. SOI

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Abstract

本实用新型主要提出两种不同型态的完全空乏晶体管，并且将完全空乏晶体管与部分空乏晶体管整合于单一芯片上。可透过调整栅极层的长度，以决定平面晶体管是完全空乏或是部分空乏。完全空乏晶体管的栅极层长度较部分空乏晶体管的栅极层长度为长。或是透过调整晶体管主动区的宽度，以决定晶体管是完全空乏或是部分空乏。完全空乏晶体管的主动区宽度较部分空乏晶体管的主动区宽度为窄。不断地减少主动区的宽度，可以形成一多重栅极晶体管，当该多重栅极晶体管的主动区宽度减少至小于空乏区宽度的两倍时，该多重栅极晶体管便是完全空乏。如此一来，在单一芯片上就可同时制备完全空乏晶体管与部分空乏晶体管。

Description

可同时具有部分空乏晶体管与完全空乏晶体管的芯片
技术领域
本实用新型是有关于一种半导体集成电路，且特别是有关于一种可同时具有部分空乏晶体管与完全空乏晶体管的芯片。
背景技术
随着半导体集积度的增加，半导体组件的尺寸必须随的缩小。而为了提供更良好的组件性能，绝缘层上覆硅(silicon on insulator；SOI)的半导体基底被提出来，绝缘层上覆硅(semiconductor on insulator；SOI)的集成电路组件是将传统的组件(active devices)设置于一绝缘层上有半导体层的晶圆(silicon on insulator wafer)上，上述晶圆例如为一绝缘层上有硅的晶圆(silicon on insulator wafer)。绝缘层上覆硅(SOI)具有以下优点(1)降低短通道效应(Short Channel Effect)(2)消除闭锁现象(Latch up Effect)(3)降低寄生汲极/源极电容(ParasiticSource/Drain Capacitance)(4)减少软错效应(Soft Error Effect)(5)降低基材漏电流(Substrate Leakage Current)(6)制程简化容易与硅晶制程兼容等等。因此，借由SOI技术可形成具有较佳速度表现、较高积集度以及较低消耗功率的集成电路组件。
绝缘层上覆硅(SOI)又可分为部分空乏绝缘层上覆硅(partially-depleted SOI)与完全空乏绝缘层上覆硅(fully-depletedSOI)两种。部分空乏金氧半导体场效应晶体管(metal-oxide-semiconductor field effect transistors；MOSFET)的通道区厚度大于最大空乏层宽度，而部分空乏金氧半导体场效应晶体管(metal-oxide-semiconductor field effect transistors；MOSFET)的通道区厚度小于最大空乏层宽度。部分空乏金氧半导体场效应晶体管(PDMOSFET)的电荷载子会累积在汲极/源极附近的通道区下方硅层基底内，造成通道区电位改变，而产生浮体效应(floating body effect)，进而造成电流的突变(kink)，导致组件功能退化。
改善浮体效应的方法的一为将通道区下方的硅层基底外接一电性导体，以搜集冲击离子化(impact ionization)所产生的电流，针对这方面技术已有许多方法被提出来，但仍有许多缺点有待改进。美国专利第4946799号与第6387739号都是揭示有关改善浮体效应的方法。
克服浮体效应的另一种有效方法，便是采用完全空乏金氧半导体场效应晶体管(FD MOSFET)。
美国专利第6222234号提供一种于单一基底上制作完全空乏金氧半导体场效应晶体管(FD MOSFET)与部分空乏金氧半导体场效应晶体管(PDMOSFET)的方法。
美国专利第6414355号与第6448114号都揭示有关于厚度不均匀的绝缘层上覆硅基底的半导体技术。
美国专利第6448114号更是揭示将完全空乏金氧半导体场效应晶体管(FD MOSFET)制作于一厚度较薄的硅层基底，而部分空乏金氧半导体场效应晶体管(PD MOSFET)则制作于一厚度较厚的硅层基底。
然而，完全空乏金氧半导体场效应晶体管的硅层基底厚度较薄或被施以离子掺杂。制作完全空乏金氧半导体场效应晶体管(FD MOSFET)需要选择性磊晶(selective epitaxy)，技术尚未发展成熟，不仅良率不佳，并且价格昂贵，急需发展更佳的制造技术。
有鉴于此，为了解决上述问题，本实用新型主要目的在于提供一种可同时具有部分空乏晶体管与完全空乏晶体管的芯片，可适用于绝缘层上覆硅基底的单一芯片。
发明内容
本实用新型的目的之一在于提供一种可同时具有部分空乏晶体管与完全空乏晶体管的芯片，具有新的完全空乏晶体管结构，以提供良好的组件功能。
本实用新型主要提出两种不同型态的完全空乏晶体管，并且将完全空乏晶体管与部分空乏晶体管整合于单一芯片上。
本实用新型的第一主要特征在于透过调整栅极层的长度，以决定平面晶体管是完全空乏或是部分空乏。完全空乏晶体管的栅极层长度较部分空乏晶体管的栅极层长度为长。如此一来，在单一芯片上就可同时制备完全空乏晶体管与部分空乏晶体管。
为获致上述的目的，本实用新型提出一种可同时具有部分空乏晶体管与完全空乏晶体管的芯片，主要是包括：
一半导体基底；一完全空乏平面晶体管，具有一长栅极层，且设置于上述半导体基底上；以及一部分空乏平面晶体管，具有一短栅极层，且设置于上述半导体基底上；其中上述长栅极层的长度大于上述短栅极层。
如前所述，上述半导体基底可由一依序堆栈的一第一硅层、一绝缘层与一第二硅层所构成。
如前所述，上述完全空乏平面晶体管下方的上述第二硅层具有浓度大体为1016～1018cm-3的掺杂物，而上述部分空乏平面晶体管下方的上述第二硅层具有浓度大体为1018～2*1019cm-3的掺杂物。
如前所述，上述完全空乏平面晶体管的上述长栅极层的长度大于宽度，而上述部分空乏平面晶体管的上述短栅极层的宽度大于长度。
如前所述，上述第二硅层的厚度大体为10～2000。
如前所述，上述完全空乏平面晶体管的上述长栅极层的长度大体为120～1000nm，而上述部分空乏平面晶体管的上述短栅极层的长度大体为9～100nm。
如前所述，本实用新型的芯片更包括：一多重栅极晶体管，设置于上述半导体基底上方。上述多重栅极晶体管可以为完全空乏，上述多重栅极晶体管的宽度小于70nm。
本实用新型的第二主要特征在于透过调整晶体管主动区的宽度，以决定晶体管是完全空乏或是部分空乏。完全空乏晶体管的主动区宽度较部分空乏晶体管的主动区宽度为窄。不断地减少主动区的宽度，可以形成一多重栅极晶体管，当该多重栅极晶体管的主动区宽度减少至小于空乏区宽度的两倍时，该多重栅极晶体管便是完全空乏。如此一来，在单一芯片上就可同时制备完全空乏晶体管与部分空乏晶体管。
为获致上述的目的，本实用新型提出一种可同时具有部分空乏晶体管与完全空乏晶体管的芯片，主要包括：
一半导体基底；以及一多重栅极晶体管，设置于上述半导体基底上。上述多重栅极晶体管，包括：
一鳍形半导体层，位于上述半导体基底上，其中上述鳍形半导体层具有一源极、一汲极以及位于上述源极和上述汲极之间的一通道区，且上述鳍形半导体层中具有一应变；
一栅极介电层，位于上述鳍形半导体层的上述通道区表面；以及
一栅极电极，位于上述栅极介电层上，并包覆对应于上述通道区的上述鳍形半导体层的两侧壁和一顶面；其中，上述鳍形半导体层的宽度小于空乏区最大宽度的两倍。
如前所述，本实用新型的芯片包括：一平面晶体管，设置于上述半导体基底上。上述平面晶体管可以为完全空乏，也可以为部分空乏。当上述平面晶体管为完全空乏，则具有一长栅极层，且上述长栅极层的长度大于宽度，上述长栅极层的长度大体为120～1000nm。当上述平面晶体管为部分空乏，则具有一短栅极层，且上述短栅极层的长度小于宽度，上述短栅极层的长度大体为9～100nm。
根据本实用新型，上述多重栅极晶体管为完全空乏，上述鳍形半导体层的宽度小于70nm。上述鳍形半导体层的厚度大体为20～1000。
如前所述，上述多重栅极晶体管更可包括：一应力膜层，位于上述源极和上述汲极上。上述应力膜层的材质可包括氮化硅。
如前所述，上述鳍形半导体层可具有圆滑化的上部边角(roundedcorner)，上述圆滑化的上部边角的半径大体为200。
如前所述，上述鳍形半导体层中的上述应变为沿上述源极至上述汲极方向的拉伸应变。上述鳍形半导体层中的上述拉伸应变量为0.1％至2％。
如前所述，上述栅极介电层的材质例如为氧化硅、氮氧化硅、或相对电容率(relative permittivity)大于5的介电材质。上述相对电容率大于5的介电材质可以为氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化硅铪(HfSiNxOy)、硅化铪(HfSi4)、氧化锆(ZrO2)、硅化锆(ZrSi4)或氧化镧(La2O3)。
如前所述，上述栅极介电层的等效氧化层厚度例如为3～100。上述鳍形半导体层的侧壁的上述栅极介电层的厚度可以不同于顶部的厚度，例如：上述鳍形半导体层的侧壁的上述栅极介电层的厚度小于顶部的厚度，则上述鳍形半导体层的顶部的上述栅极介电层的等效氧化层厚度约小于20。
如前所述，上述栅极电极为一金属、一金属硅化物或一金属氮化物，其材质包括一多晶硅或一多晶锗。
如前所述，上述多重栅极晶体管更包括：一间隔物，设置于上述栅极电极沿上述汲极与上述源极方向的两侧壁上。上述间隔物沿着上述汲极与上述源极的延伸宽度大体为500。
如前所述，上述栅极电极的栅极长度小于65nm。
如前所述，本实用新型的芯片更包括：一隔离区，包围于上述多重栅极晶体管周围，以提供电性隔离。上述隔离区是可以由一绝缘物所构成，则上述鳍形半导体层表面与上述隔离区表面的高度差大体为200～400。上述隔离区也可以借由一平台式隔离达成电性隔离，则上述鳍形半导体层表面与上述平台式隔离表面的高度差大体为200～400。
合并前述第一主要特征与第二主要特征，本实用新型又提出一种可同时具有部分空乏晶体管与完全空乏晶体管的芯片，主要包括：
一半导体基底；一平面晶体管，设置于上述半导体基底上；以及一多重栅极晶体管，设置于上述半导体基底上。上述多重栅极晶体管包括：
一鳍形半导体层，位于上述半导体基底上，其中上述鳍形半导体层具有一源极、一汲极以及位于上述源极和上述汲极之间的一通道区，且上述鳍形半导体层中具有一应变；
一栅极介电层，位于上述鳍形半导体层的上述通道区表面；以及
一栅极电极，位于上述栅极介电层上，并包覆对应于上述通道区的上述鳍形半导体层的两侧壁和一顶面。
附图说明
图1是显示本实用新型的可同时具有部分空乏晶体管与完全空乏晶体管的芯片的立体图；
图2A与图2B是显示不同主动区宽度的晶体管的电性分析结果；
图3A与图3B是显示不同主动区宽度与不同通道长度之下，部分空乏晶体管与完全空乏晶体管之间的关系示意图。
符号说明：
108～半导体基底
120～部分空乏平面晶体管
130～完全空乏平面晶体管
140～多重栅极晶体管
122a、122b、122c～栅极层
124a、124b、124c～栅极介电层
126a、126b、126c～间隔物
S/D～汲极/源极
102～第一硅层
104～绝缘层
106～第二硅层
106a～鳍形半导体层
150～应力膜层
STI～隔离区
106b、106c～图案化第二硅层
具体实施方式
为使本实用新型的上述目的、特征和优点能更明显易懂，下文特举较佳实施例，并配合附图，作详细说明如下：
本实用新型将一部分空乏绝缘层上覆硅与一完全空乏绝缘层上覆硅晶体管同时整合于一芯片上，并且增大应变效应，以改善超大(ultra-scaled)集成电路的载子迁移率(carrier mobility)与组件功能。
本实用新型提供两种不同结构的完全空乏晶体管，利用两种手段1.调整信道的长度并且配合调整通道掺杂的浓度，2.调整主动区的宽度，来达成备制部分空乏(PD)晶体管与完全空乏(FD)晶体管于单一芯片上，如此一来，就可以在一厚度薄的硅层上，制备出部分空乏晶体管与完全空乏晶体管。
以下将配合图1的立体图，详细说明本实用新型的可同时具有部分空乏晶体管与完全空乏晶体管的芯片的结构。
根据本实用新型的芯片主要包括：一半导体基底102、设置于半导体基底102上的至少一平面晶体管120、130、设置于半导体基底102上的一多重栅极晶体管140。其中，平面晶体管120、130可以为部分空乏晶体管120，也可以为完全空乏晶体管130。多重栅极晶体管140是为完全空乏晶体管。
部分空乏平面晶体管120如同一般习知平面晶体管，包括：设置于半导体基底102上的一栅极层122b、设置于栅极层122b与半导体基底102之间的一栅极介电层124b、设置于栅极层122b侧壁的一间隔物(spacer)126b以及形成于栅极层122b外侧的半导体基底102表面的汲极与源极S/D。栅极层122b的长度小于宽度。栅极层122b的长度大体为40～60nm。
根据本实用新型的第一主要技术特征，即延长栅极层122b的长度，可使平面晶体管由部分空乏转变成完全空乏。便获得完全空乏平面晶体管130，包括：设置于半导体基底102上的一栅极层122c、设置于栅极层122c与半导体基底102之间的一栅极介电层124c、设置于栅极层122c侧壁的一间隔物126b以及形成于栅极层122c外侧的半导体基底102表面的汲极与源极S/D。完全空乏平面晶体管130的栅极层120c长度较部分空乏平面晶体管120的栅极层122b长度为长。栅极层120c的长度大于宽度。栅极层120c的长度大体为120～1000nm。值得注意的是，这里所指的栅极层长度，是指与沿着汲极经由信道(channel)至源极的方向相互平行的方向的尺寸，即为图1中的LL’方向的尺寸，也就是熟知此技艺人士所指的通道长度。
另外，半导体基底102是由一依序堆栈的一第一硅层102、一绝缘层104与一第二硅层106所构成。绝缘层104例如为埋入式氧化硅层，第二硅层106的厚度大体为10～2000。完全空乏平面晶体管130下方的第二硅层106具有浓度大体为1016～1018cm-3的掺杂物，而部分空乏平面晶体管120下方的第二硅层106具有浓度大体为1018～2*1019cm-3的掺杂物。
根据本实用新型的第二主要特征，缩窄晶体管主动区的宽度，可使平面晶体管由部分空乏转变成完全空乏。便获得完全空乏平面晶体管140，包括：一鳍形半导体层106a、一栅极介电层124a、一栅极电极122a、一汲极与源极S/D以及一间隔物126a。其中，鳍形半导体层106a，位于半导体基底102上，其中鳍形半导体层106a具有一源极/汲极S/D以及位于源极/汲极S/D之间的一通道区。另外，栅极介电层124a，位于鳍形半导体层122a的通道区表面。并且，栅极电极122a，位于栅极介电层124a上，并包覆对应于通道区的鳍形半导体层122a的两侧壁和一顶面。完全空乏多重栅极晶体管140的宽度(也就是其主动区宽度)较部分空乏平面晶体管120的宽度为窄。值得注意的是，这里所指的晶体管宽度，是指与前述栅极层长度同一平面且垂直于栅极层长度方向的空间尺寸，即为图1中的WW’方向的尺寸。当多重栅极晶体管140的主动区宽度减少至小于其空乏区最大宽度的两倍时，则多重栅极晶体管140便是完全空乏。
根据本实用新型的完全空乏多重栅极晶体管140，鳍形半导体层106a的宽度小于70nm。并且，多重栅极晶体管140更包括：一应力膜层150，位于源极和汲极S/D上，使源极和汲极S/D具有一应变，其中应力膜层150的材质包括氮化硅，此应变可为沿上述源极至上述汲极方向的拉伸应变，拉伸应变量约为0.1％至2％。鳍形半导体层106a具有圆滑化的上部边角(rounded corner)，其厚度大体为20～1000，圆滑化的上部边角的半径大约为200。再者，栅极介电层124a的材质例如为氧化硅、氮氧化硅、或相对电容率(relative permittivity)大于5的介电材质，其中相对电容率大于5的介电材质包括氧化铝(Al2O3)、氧化铪(HfO2)、氮氧化硅铪(HfSiNxOy)、硅化铪(HfSi4)、氧化锆(ZrO2)、硅化锆(ZrSi4)或氧化镧(La2O3)。栅极介电层124a的等效氧化层厚度可为3～100。并且，鳍形半导体层106a的侧壁的栅极介电层124a的厚度可以不同于顶部的厚度，鳍形半导体层106a的侧壁的栅极介电层124a的厚度最好小于顶部的厚度，顶部的栅极介电层124a的等效氧化层厚度例如小于20。再者，栅极电极122a可为一金属、一金属硅化物或一金属氮化物，其材质包括一多晶硅或一多晶锗，其长度约小于65nm。另外，多重栅极晶体管140更包括：一间隔物126a，设置于栅极电极140沿汲极与源极S/D方向的两侧壁上，其宽度大约为500。
根据本实用新型的芯片上更包括：材质例如为绝缘物的一隔离区(STI)，包围各晶体管120、130、140周围，以提供电性隔离，而隔离区(STI)可以由一绝缘物所构成，本实用新型的多重栅极晶体管140周围的隔离区(STI)绝缘层厚度可以较其它区域隔离区绝缘物为薄，使得鳍形半导体层106a表面与隔离区(STI)表面的高度差大约为200～400，甚至多重栅极晶体管140隔离区的绝缘物可以完全去除，再此定义为一平台式隔离(mesa isolation)，而在后段制程制作内联机线时，会填入内层介电层，以达成电性隔离，如此鳍形半导体层106a表面与平台式隔离表面的高度差大体为200～400。
如此一来，在单一芯片上就可同时制备完全空乏晶体管130、140与部分空乏晶体管120，而完全空乏晶体管可以由具有长栅极层的平面晶体管130所构成，也可以由具有窄主动区宽度的多重栅极晶体管140所构成。为了清楚起见，本实施例的芯片共包括了3种型态晶体管，并非一芯片必须同时皆包括此3种型态晶体管，熟知此技艺人士可视实际需求调整芯片上前述晶体管的种类数及其组合，例如：单一芯片包括一部分空乏平面晶体管与一完全空乏平面晶体管、单一芯片包括一部分空乏平面晶体管与一完全空乏多重栅极晶体管或单一芯片包括一部分空乏平面晶体管、完全空乏平面晶体管与一完全空乏多重栅极晶体管等，在此并不加以设限。
以下请参照图1，说明本实用新型的可同时具有部分空乏晶体管与完全空乏晶体管的芯片的一较佳实施例。
首先提供一半导体基底102，可以为一半导体层/绝缘层迭置型基底，例如为一硅层/氧化硅层迭置型基底(silicon on insulator substrate；SOI substrate)108，其包括一第一硅层102、一绝缘层104和一第二硅层106，其中绝缘层104例如为埋入式氧化硅层。在此实施例中是以该种型式的基底为例，当然半导体层的材质和绝缘层的材质并不限定于此，例如硅锗亦可做为半导体层。
接着，于第二硅层106中预计形成平面晶体管120、130的区域定义出主动区硅层106b、106c，且在预计形成多重栅极晶体管140的区域定义出鳍形硅层(silicon fins)106a，以做为通道层之用。其中鳍形硅层106a的宽度小于70nm，高度约为20～1000。完全空乏平面晶体管130的栅极层长度约为120～1000nm。并且第二硅层106被施以掺杂物。预计形成完全空乏平面晶体管130的第二硅层106c具有浓度大体为1016～1018cm-3的掺杂物，而预计形成部分空乏平面晶体管120的第二硅层106b具有浓度大体为1018～2*1019cm-3的掺杂物。部分空乏平面晶体管120的栅极层122b的长度大约为9～100nm。完全空乏平面晶体管130的栅极层120c的长度大体为120～1000nm，定义主动区时需做应对调整。
定义第二硅层106的方法例如是于第二硅层106上形成一罩幕层，并以该罩幕层为蚀刻罩幕，以将该罩幕层的图案转移至其下方的第二硅层106中。此罩幕层可为光阻层(photoresist layer)、能量敏感层(energysensitive layer)、氧化硅层、氮化硅层、或其它材质的罩幕层。
接着，可对鳍形硅层106a进行侧表面平滑化处理，以降低鳍形硅层106a侧表面的粗糙度。侧表面平滑化处理的方法为牺牲性氧化处理和侧壁处理，其中侧壁处理的方法例如是在1000℃含氢(H2)的环境下进行高温回火。当鳍形硅层106a的侧表面经牺牲性氧化处理时，会于表面氧化生成一层氧化硅，借此修复表面于蚀刻过程中所受到的伤害，并将上部边角圆滑化，再将氧化硅移除。表面平滑化的目的在于使组件具有好的载子迁移率，以及利于后续形成可靠度佳的栅极介电层。将鳍形半导体层106a上部边角圆滑化I，可以避免因为应力集中于角落所导致缺陷传播和延伸的问题，可以使栅极电流稳定。缺陷可能是由于制程不良率或组件退化所产生的。
接着，将具有干净且平整表面的图案化第二硅层106a、106b、106c上方的罩幕层移除。移除的方法可为电浆蚀刻或湿蚀刻，湿蚀刻所使用的蚀刻剂可为稀释的氢氟酸(DHF)。在此蚀刻过程中，图案化第二硅层106a、106b、106c底部可能发生底切(undercut)或凹槽(notch)。
接着，形成一浅沟槽隔离物(shallow trench isolation；STI)于图案化硅层106a、106b、106c周围的半导体基底102表面。例如先全面性以适当沉积法，例如化学气相沉积(chemical vapor deposition；CVD)形成一材质例如为氧化物的隔离物于半导体基底102表面，然后经过化学机械研磨与选择性蚀刻，将部分隔离物去除，仅留下平面晶体管120、130、140的图案化硅层106a、106b、106c周围隔离物，以做为晶体管之间的浅沟槽隔离物(STI)，其中多重栅极晶体管140周围的隔离物STI厚度较其它区域隔离区绝缘物为薄，使得鳍形半导体层106a表面与隔离区(STI)表面的高度差大约为200～400，甚至多重栅极晶体管140隔离区的绝缘物可以完全去除，以平台式隔离(mesa isolation)做电性隔离。
接着，分别于图案化第二硅层106a、106b、106c表面形成一层栅极介电层124a、124b、124c，平面晶体管120、130的栅极介电层124b、124c是形成于图案化第二硅层106b、106c顶部，而多重栅极介电层140的栅极介电层124a形成于鳍形硅层106a的顶部与侧壁，其形成方法例如是热氧化法、化学气相沉积法、溅镀等，其材质可为氧化硅、或氮氧化硅。通常，鳍形硅层106a的侧壁和顶部的栅极介电层124a具有不同的厚度，通常是顶部的栅极介电层124a的厚度较侧壁为厚，其厚度约为3埃至100埃，较佳的是10埃以下，顶部部分的厚度较佳的是20埃以下；或者为高介电常数的材质，例如氧化铝(Al2O5)、氧化铪(HfO2)、氧化锆(ZrO2)、或其它类似此性质者，其等效氧化层厚度(equivalent oxidethickness)约为3至100埃。
接着，形成一层导电层于栅极介电层124a、124b、124c上，其材质可为多晶硅、多晶硅锗、耐火金属(refractory metal)、类金属化合物、或其它导电材质，其中耐火金属可为钼(Mo)、钨(W)等，类金属化合物可为氮化钛。
接着，于导电层上覆盖一图案化罩幕层，并借由蚀刻，将图案化罩幕层的图案转移至导电层中，以形成栅极电极122a、122b、122c，平面晶体管120、130的栅极层122b、122c形成于栅极介电层124b、124c上方，而多重栅极晶体管140的栅极层122a则形成于栅极介电层124a上，并包覆对应于通道区的鳍形半导体层106a的两侧壁和一顶面。以材质为多晶硅的导电层以及材质为氮氧化硅的栅极介电层124a、124b、124c为例，其蚀刻条件例如是含氯和溴的蚀刻气体进行电浆蚀刻，其多晶硅对氮氧化硅的蚀刻选择比超过2000。
在完成栅极电极122a、122b、122c的定义后，则移除其上方的图案化罩幕层。
接着，进行源极/汲极的淡掺杂制程，其形成方法例是以离子植入、电浆侵入式离子植入(plasma immersion ion implantation，PIII)、或是其它的技术来进行。
接着，借由沉积以及选择性非等向性地蚀刻介电材质，以于栅极电极122a、122b、122c的侧壁形成间隙壁126a、126b、126c，间隙壁126的材质可为氮化硅或氧化硅。之后进行源极/汲极的浓掺杂制程，其形成方法例是以离子植入、电浆侵入式离子植入、固体源扩散(solid sourcediffusion)、或是其它的技术。在此步骤中，亦可以根据需要，同时将离子掺杂入栅极电极122a、122b、122c，借此提高其导电性。任何植入的伤害或非晶化可借由后续高温回火制程而获得改善。经过上述的源极/汲极的淡掺杂制程和浓掺杂制程后，于栅极电极122a、122b、122c两侧的图案化第二硅层106a、106b、106c中形成具有浅掺杂汲极结构(lightlydoped drain)LDD的源极/汲极S/D。并且，平面晶体管120、130的图案化硅层106b、106c的通道区可以施以一super halo布植，由于部分空乏晶体管120的信道长度短，所以信道两侧的super halo布植区域会在信道中间区域重达。
接着，为了降低源极/汲极S/D的片电阻，可以在源极/汲极S/D表面形成一层导电层，意即，此导电层形成于鳍形硅层106a的顶部和侧壁以及图案化硅层106b、106c的汲极/源极S/D表面。导电层的材质例如是以自动对准金属硅化物制程(self-aligned silicide process，salicideprocess)形成的金属硅化物，例如硅化钴。该材质亦可为金属、多晶硅、或是磊晶硅。
之后，沉积一层高应力膜层150覆盖于多重栅极晶体管140的栅极电极122a上，其厚度约为50～1000埃。由于鳍形硅层106a和高应力膜层150两者之间的热膨胀系数(thermal expansion coefficient)及杨氏系数(Young’s modulus)有很大的差异，使得在经过半导体制程中所需的高温沉积或热回火制程后，高应力膜层150自高温降温时的收缩速度和鳍形硅层106a的收缩速度会有很大的差异，因此会将应力导入鳍形硅层106a的通道区中，产生的应力可能是数百MPa甚至超过1GPa。
如果高应力膜层150的热膨胀系数小于鳍形硅层106a，则鳍形硅层106a会感受到压缩应变(compressive strain)。若高应力膜层150施与通道区的应变为压缩应变，则电洞载子的迁移率可获得提升。因此，覆盖于高应力膜层150下方的栅极电极122a和源极/汲极S/D构成的晶体管为PMOS晶体管。上述的应变是指沿源极至汲极方向的压缩应变，鳍形硅层106a中的压缩应变强度为0.1％至2％，较佳的是1％至2％，应力约为-500～1500MPa，，其中负值代表是一压缩应力，则正值代表是一拉伸应力。
如果高应力膜层150的热膨胀系数大于鳍形硅层26a，则鳍形硅层106a会感受到拉伸应变(tensile strain)。若高应力膜层150施与通道区的应变为拉伸应变，则电子和电洞载子两者的迁移率均可获得提升。因此，覆盖于高应力膜层150下方的栅极电极122a和源极/汲极S/D构成的晶体管可为PMOS晶体管和NMOS晶体管。上述的应变是指沿源极至汲极方向的拉伸应变，鳍形硅层106a中的拉伸应变强度为0.1％至2％，较佳的是1％至2％。
就高应力膜层150而言，借由控制形成的条件，可以调整所形成的膜层的应力大小，根据研究，可控制应力的因素有温度、压力或制程气体的流速比。举例而言，利用电浆增强型化学气相沉积的氮化硅(plasma-enhanced chemical vapor deposited silicon nitride)可以导入至通道区中的应力可为拉伸应力或压缩应力，端视沉积的条件而定。此外，若选择氧化硅制备高应力膜层150，还可以借由改变掺杂的物质及掺杂的浓度来改变其热膨胀系数及杨氏系数，可以掺杂的物质例如是锗(Ga)、氮(N)或耐火的金属(refractory metal)。
发明功效：
当主动区的宽度W越小，则应力膜层与鳍状半导体基底接触的面积则越大，因此，应力效应会随着主动区宽度W的减少而增强。如图2A与图2B所示，当主动区宽度W由1200nm(图2A)减少至110nm(图2B)，在晶体管关闭状态(off-state)下，漏电流(leakage)约为300nA/mm，应变感应驱动电流由10％增加到17％。
关于通道长度、主动区宽度与完全空乏晶体管、部分空乏晶体管之间的关系，经由实验，得到以下结果。图3A与图3B是显示部分空乏晶体管与完全空乏晶体管的主动区宽度W与通道长度Lg的关系示意图。图3A是一N型晶体管的实验结果，平面部分空乏晶体管与平面完全空乏晶体管的主动区大于50nm，而非平面式多重栅极完全空乏晶体管的主动区宽度小于50nm。图3B是一P型晶体管的实验结果。在主动区宽度固定的情况下，欲将部分空乏晶体管转变成完全空乏晶体管的方法为增加栅极长度。另外，当主动区宽度小于50nm以下，便会形成多重栅极晶体管。第3B图中P型晶体管可形成部分空乏的范围较第3A图中N型晶体管可形成部分空乏的范围为小。这是因为P形晶体管中的冲击离子化引发寄生双极化反应(impact ionization induced parasitic bipolar action)较弱。
发明优点：
1.根据本实用新型的具有长通道的完全空乏平面晶体管或多重栅极完全空乏晶体管皆可有效克服浮体效应(floating body effect)的问题。
2.根据本实用新型的多重栅极晶体管，可视为三个并联的晶体管，分别位于鳍形硅层两侧及顶面。该结构可有效提高组件的电流量，并且无须缩短通道长度，可以有效控制短通道效应(short-channel effect)。
3.根据本实用新型的应力膜层，可使应力导入通道区中，以提高载子的迁移率，进而提升组件的操作效能。
4.本实用新型的具有多重栅极及应变的通道层的晶体管，借由其垂直型的结构，使晶体管的积集度可以有效地提升。

Claims (15)

1.一种可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于所述芯片包括：
一半导体基底；
一完全空乏平面晶体管，具有一长栅极层，且设置于上述半导体基底上；以及
一部分空乏平面晶体管，具有一短栅极层，且设置于上述半导体基底上；
其中上述长栅极层的长度大于上述短栅极层。
2.根据权利要求1所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于：上述完全空乏平面晶体管的上述长栅极层的长度大于宽度。
3.根据权利要求1所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于：上述部分空乏平面晶体管的上述短栅极层的宽度大于长度。
4.根据权利要求1所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于：上述完全空乏平面晶体管的上述长栅极层的长度为120～1000nm。
5.根据权利要求1所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于：上述部分空乏平面晶体管的上述短栅极层的长度为9～100nm。
6.根据权利要求1所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于所述芯片更包括：一多重栅极晶体管，设置于上述半导体基底上方。
7.根据权利要求6所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于上述多重栅极晶体管包括：
一鳍形半导体层，位于上述半导体基底上，其中上述鳍形半导体层具有一源极、一汲极以及位于上述源极和上述汲极之间的一通道区，且上述鳍形半导体层中具有一应变；
一栅极介电层，位于上述鳍形半导体层的上述通道区表面；以及
一栅极电极，位于上述栅极介电层上，并包覆对应于上述通道区的上述鳍形半导体层的两侧壁和一顶面。
8.根据权利要求7所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于所述芯片更包括：一应力膜层，位于上述源极和上述汲极上。
9.根据权利要求7所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于：上述鳍形半导体层具有圆滑化的上部边角。
10.根据权利要求7所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于：上述鳍形半导体层中的上述应变为沿上述源极至上述汲极方向的拉伸应变。
11.根据权利要求7所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于：上述鳍形半导体层的侧壁的上述栅极介电层的厚度不同于顶部的厚度。
12.根据权利要求7所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于：上述鳍形半导体层的侧壁的上述栅极介电层的厚度小于顶部的厚度。
13.根据权利要求7所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于所述芯片更包括：一间隔物，设置于上述栅极电极沿上述汲极与上述源极方向的两侧壁上。
14.根据权利要求7所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于所述芯片更包括：一隔离区，包围于上述多重栅极晶体管周围，以提供电性隔离。
15.根据权利要求14所述的可同时具有部分空乏晶体管与完全空乏晶体管的芯片，其特征在于：上述隔离区是借由一平台式隔离达成电性隔离。
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US7268024B2 (en) 2007-09-11
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US6867433B2 (en) 2005-03-15

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