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FR2812764B1 - Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu - Google Patents

Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu

Info

Publication number
FR2812764B1
FR2812764B1 FR0010176A FR0010176A FR2812764B1 FR 2812764 B1 FR2812764 B1 FR 2812764B1 FR 0010176 A FR0010176 A FR 0010176A FR 0010176 A FR0010176 A FR 0010176A FR 2812764 B1 FR2812764 B1 FR 2812764B1
Authority
FR
France
Prior art keywords
substrate
insulation
vacuum
self
device obtained
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0010176A
Other languages
English (en)
Other versions
FR2812764A1 (fr
Inventor
Thomas Skotnicki
Michel Haond
Didier Dutartre
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SA
Original Assignee
STMicroelectronics SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics SA filed Critical STMicroelectronics SA
Priority to FR0010176A priority Critical patent/FR2812764B1/fr
Priority to US09/920,315 priority patent/US6537894B2/en
Publication of FR2812764A1 publication Critical patent/FR2812764A1/fr
Application granted granted Critical
Publication of FR2812764B1 publication Critical patent/FR2812764B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Thin Film Transistor (AREA)
  • Element Separation (AREA)
  • Semiconductor Memories (AREA)
FR0010176A 2000-08-02 2000-08-02 Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu Expired - Fee Related FR2812764B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR0010176A FR2812764B1 (fr) 2000-08-02 2000-08-02 Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu
US09/920,315 US6537894B2 (en) 2000-08-02 2001-08-01 Process for fabricating a substrate of the silicon-on-insulator or silicon-on-nothing type and resulting device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0010176A FR2812764B1 (fr) 2000-08-02 2000-08-02 Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu

Publications (2)

Publication Number Publication Date
FR2812764A1 FR2812764A1 (fr) 2002-02-08
FR2812764B1 true FR2812764B1 (fr) 2003-01-24

Family

ID=8853216

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0010176A Expired - Fee Related FR2812764B1 (fr) 2000-08-02 2000-08-02 Procede de fabrication d'un substrat de type substrat-sur- isolant ou substrat-sur-vide et dispositif obtenu

Country Status (2)

Country Link
US (1) US6537894B2 (fr)
FR (1) FR2812764B1 (fr)

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FR2838237B1 (fr) * 2002-04-03 2005-02-25 St Microelectronics Sa Procede de fabrication d'un transistor a effet de champ a grille isolee a canal contraint et circuit integre comprenant un tel transistor
US6887773B2 (en) * 2002-06-19 2005-05-03 Luxtera, Inc. Methods of incorporating germanium within CMOS process
JP4750342B2 (ja) * 2002-07-03 2011-08-17 ルネサスエレクトロニクス株式会社 Ｍｏｓ−ｆｅｔおよびその製造方法、並びに半導体装置
KR100511656B1 (ko) * 2002-08-10 2005-09-07 주식회사 실트론 나노 에스오아이 웨이퍼의 제조방법 및 그에 따라 제조된나노 에스오아이 웨이퍼
JP2004103612A (ja) * 2002-09-04 2004-04-02 Toshiba Corp 半導体装置とその製造方法
US6900502B2 (en) * 2003-04-03 2005-05-31 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel on insulator device
US6882025B2 (en) * 2003-04-25 2005-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Strained-channel transistor and methods of manufacture
US6867433B2 (en) 2003-04-30 2005-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors
US7262117B1 (en) * 2003-06-10 2007-08-28 Luxtera, Inc. Germanium integrated CMOS wafer and method for manufacturing the same
US20050012087A1 (en) * 2003-07-15 2005-01-20 Yi-Ming Sheu Self-aligned MOSFET having an oxide region below the channel
US7015147B2 (en) * 2003-07-22 2006-03-21 Sharp Laboratories Of America, Inc. Fabrication of silicon-on-nothing (SON) MOSFET fabrication using selective etching of Si1-xGex layer
US6936881B2 (en) * 2003-07-25 2005-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor that includes high permittivity capacitor dielectric
US7078742B2 (en) * 2003-07-25 2006-07-18 Taiwan Semiconductor Manufacturing Co., Ltd. Strained-channel semiconductor structure and method of fabricating the same
US6940705B2 (en) * 2003-07-25 2005-09-06 Taiwan Semiconductor Manufacturing Company, Ltd. Capacitor with enhanced performance and method of manufacture
US7301206B2 (en) * 2003-08-01 2007-11-27 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US7101742B2 (en) * 2003-08-12 2006-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Strained channel complementary field-effect transistors and methods of manufacture
US7112495B2 (en) * 2003-08-15 2006-09-26 Taiwan Semiconductor Manufacturing Company, Ltd. Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit
US6974755B2 (en) * 2003-08-15 2005-12-13 Taiwan Semiconductor Manufacturing Company, Ltd. Isolation structure with nitrogen-containing liner and methods of manufacture
US20050035369A1 (en) * 2003-08-15 2005-02-17 Chun-Chieh Lin Structure and method of forming integrated circuits utilizing strained channel transistors
US7071052B2 (en) 2003-08-18 2006-07-04 Taiwan Semiconductor Manufacturing Company, Ltd. Resistor with reduced leakage
US6964911B2 (en) * 2003-09-23 2005-11-15 Freescale Semiconductor, Inc. Method for forming a semiconductor device having isolation regions
US20070126034A1 (en) * 2003-10-10 2007-06-07 Tokyo Institute Of Technology Semiconductor substrate, semiconductor device and process for producing semiconductor substrate
US6902965B2 (en) * 2003-10-31 2005-06-07 Taiwan Semiconductor Manufacturing Company, Ltd. Strained silicon structure
US7888201B2 (en) * 2003-11-04 2011-02-15 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors
US20050186722A1 (en) * 2004-02-25 2005-08-25 Kuan-Lun Cheng Method and structure for CMOS device with stress relaxed by ion implantation of carbon or oxygen containing ions
KR100560815B1 (ko) * 2004-03-16 2006-03-13 삼성전자주식회사 이형 반도체 기판 및 그 형성 방법
US7018882B2 (en) * 2004-03-23 2006-03-28 Sharp Laboratories Of America, Inc. Method to form local “silicon-on-nothing” or “silicon-on-insulator” wafers with tensile-strained silicon
US7078723B2 (en) * 2004-04-06 2006-07-18 Taiwan Semiconductor Manufacturing Company, Ltd. Microelectronic device with depth adjustable sill
US20050266632A1 (en) * 2004-05-26 2005-12-01 Yun-Hsiu Chen Integrated circuit with strained and non-strained transistors, and method of forming thereof
JP2006041422A (ja) * 2004-07-30 2006-02-09 Seiko Epson Corp 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法
JP4862253B2 (ja) * 2004-09-28 2012-01-25 セイコーエプソン株式会社 半導体基板の製造方法及び半導体装置の製造方法
JP4759967B2 (ja) * 2004-10-01 2011-08-31 セイコーエプソン株式会社 半導体装置の製造方法
JP2006128428A (ja) * 2004-10-29 2006-05-18 Seiko Epson Corp 半導体基板、半導体装置、半導体基板の製造方法および半導体装置の製造方法
FR2879820B1 (fr) * 2004-12-16 2009-01-16 Commissariat Energie Atomique Modulateur a jonction capacitive, jonction capacitive et son procede de realisation
US7465972B2 (en) 2005-01-21 2008-12-16 Taiwan Semiconductor Manufacturing Company, Ltd. High performance CMOS device design
US7354831B2 (en) * 2005-08-08 2008-04-08 Freescale Semiconductor, Inc. Multi-channel transistor structure and method of making thereof
JP4792875B2 (ja) * 2005-08-26 2011-10-12 セイコーエプソン株式会社 半導体基板の製造方法及び半導体装置の製造方法
JP2007059804A (ja) * 2005-08-26 2007-03-08 Seiko Epson Corp 半導体装置の製造方法
JP2009507389A (ja) * 2005-09-06 2009-02-19 エヌエックスピー ビー ヴィ 分離領域を有する半導体装置の製造方法およびその方法によって製造された装置
JP4894245B2 (ja) * 2005-11-29 2012-03-14 セイコーエプソン株式会社 半導体装置の製造方法
JP2007207815A (ja) * 2006-01-31 2007-08-16 Seiko Epson Corp 半導体装置、及び半導体装置の製造方法
JP2007251005A (ja) * 2006-03-17 2007-09-27 Toshiba Corp 半導体装置及びその製造方法
US7323392B2 (en) * 2006-03-28 2008-01-29 Taiwan Semiconductor Manufacturing Company, Ltd. High performance transistor with a highly stressed channel
US20070257322A1 (en) * 2006-05-08 2007-11-08 Freescale Semiconductor, Inc. Hybrid Transistor Structure and a Method for Making the Same
US7452784B2 (en) * 2006-05-25 2008-11-18 International Business Machines Corporation Formation of improved SOI substrates using bulk semiconductor wafers
WO2008087576A1 (fr) * 2007-01-16 2008-07-24 Nxp B.V. Traitement d'un substrat semi-conducteur
US8558278B2 (en) * 2007-01-16 2013-10-15 Taiwan Semiconductor Manufacturing Company, Ltd. Strained transistor with optimized drive current and method of forming
JP4455618B2 (ja) * 2007-06-26 2010-04-21 株式会社東芝 半導体装置の製造方法
US7906381B2 (en) 2007-07-05 2011-03-15 Stmicroelectronics S.A. Method for integrating silicon-on-nothing devices with standard CMOS devices
US7943961B2 (en) * 2008-03-13 2011-05-17 Taiwan Semiconductor Manufacturing Company, Ltd. Strain bars in stressed layers of MOS devices
US7808051B2 (en) * 2008-09-29 2010-10-05 Taiwan Semiconductor Manufacturing Company, Ltd. Standard cell without OD space effect in Y-direction
US8610211B2 (en) 2010-07-23 2013-12-17 International Business Machines Corporation Semiconductor-on-insulator (SOI) structure with selectively placed sub-insulator layer void(s) and method of forming the SOI structure
US8455308B2 (en) 2011-03-16 2013-06-04 International Business Machines Corporation Fully-depleted SON
US20130137238A1 (en) * 2011-11-30 2013-05-30 Taiwan Semiconductor Manufacturing Company, Ltd. Method for forming high mobility channels in iii-v family channel devices
US9136328B2 (en) 2012-10-09 2015-09-15 Infineon Technologies Dresden Gmbh Silicon on nothing devices and methods of formation thereof
FR3005309B1 (fr) 2013-05-02 2016-03-11 Commissariat Energie Atomique Transistors a nanofils et planaires cointegres sur substrat soi utbox
US11515158B2 (en) 2020-03-11 2022-11-29 Globalfoundries U.S. Inc. Semiconductor structure with semiconductor-on-insulator region and method

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US4849370A (en) * 1987-12-21 1989-07-18 Texas Instruments Incorporated Anodizable strain layer for SOI semiconductor structures
EP0957515A1 (fr) * 1998-05-15 1999-11-17 STMicroelectronics S.r.l. Procédé de fabrication pour une plaquette de silicium à silicium sur isolant (SOI)
FR2795554B1 (fr) * 1999-06-28 2003-08-22 France Telecom Procede de gravure laterale par trous pour fabriquer des dis positifs semi-conducteurs
US6677209B2 (en) * 2000-02-14 2004-01-13 Micron Technology, Inc. Low dielectric constant STI with SOI devices
US6383924B1 (en) * 2000-12-13 2002-05-07 Micron Technology, Inc. Method of forming buried conductor patterns by surface transformation of empty spaces in solid state materials

Also Published As

Publication number Publication date
US6537894B2 (en) 2003-03-25
US20020076899A1 (en) 2002-06-20
FR2812764A1 (fr) 2002-02-08

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Effective date: 20090430