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KR850005169A - 우물영역을 갖는 반도체기판상에 형성되는 mis형 반도체장치 - Google Patents

우물영역을 갖는 반도체기판상에 형성되는 mis형 반도체장치 Download PDF

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Publication number
KR850005169A
KR850005169A KR1019840007019A KR840007019A KR850005169A KR 850005169 A KR850005169 A KR 850005169A KR 1019840007019 A KR1019840007019 A KR 1019840007019A KR 840007019 A KR840007019 A KR 840007019A KR 850005169 A KR850005169 A KR 850005169A
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region
well region
semiconductor device
mis
type semiconductor
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KR1019840007019A
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KR890004797B1 (ko
Inventor
다께히데 시라도
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야마모도 다꾸마
후지쓰 가부시끼가이샤
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Publication of KR890004797B1 publication Critical patent/KR890004797B1/ko

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    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/17Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
    • H10D62/351Substrate regions of field-effect devices
    • H10D62/357Substrate regions of field-effect devices of FETs
    • H10D62/364Substrate regions of field-effect devices of FETs of IGFETs
    • H10D62/371Inactive supplementary semiconductor regions, e.g. for preventing punch-through, improving capacity effect or leakage current
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/0123Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0191Manufacturing their doped wells
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01Manufacture or treatment
    • H10D84/02Manufacture or treatment characterised by using material-based technologies
    • H10D84/03Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85Complementary IGFETs, e.g. CMOS
    • H10D84/854Complementary IGFETs, e.g. CMOS comprising arrangements for preventing bipolar actions between the different IGFET regions, e.g. arrangements for latchup prevention

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음

Description

우물영역을 갖는 반도체기판상에 형성되는 MIS형 반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제2도는 본 발명의 제1실시예의 개략 횡단면도.
제3도는 우물(well)형태가 어닐링 공정에 의해 변형된 제2도의 축소된 구조의 개략횡단면도.
제4도는 본 발명의 제3실시예의 개략횡단면도.
제5도는 우물의 형태가 어닐링 공정에 의해 변형된 제4도의 축소된 구조의 개략횡단면도.

Claims (5)

  1. 일도전형을 갖는 반도체기판과, 상기 일도전형으로서 동일도전형을 갖는 상기 기판내에 형성되는 우물영역과, 상기 가판에 형성되는 전계절연층과, 그리고 상기 우물영역상에 형성되며 상기 전계절연층에 의해 분리되는 MIS형 전계효과 트랜지스터와를 포함하되, 상기 트랜지스터는 게이트와 드레인 영역을 갖고 있으며, 상기 우물영역은 상기 게이트와 상기 전계절연층 밑 부분들에 선택적으로 형성되며 상기 드레인영역밑의 적어도 일부분에 형성되지 않는 것이 특징인 우물영역을 갖는 반도체 기판상에 형성되는 MIS형 반도체장치.
  2. 제1항에서, 상기 드레인영역밑의 상기부분은 상기 기판과 접촉상태에 있는 MIS형 반도체장치.
  3. 제1항에서, 드레인영역밑의 상기 부분에 형성되는 측방확산영역을 더 포함하되, 그 측방확산영역은 우물 영역보다 저불순물 농도를 갖는 MIS형 반도체장치.
  4. 제1항에 있어서, 상기 트랜지스터는 소오스영역을 더 포함하며, 상기 우물영역은 상기 소오스영역 둘레에 형성되며 상기 소오스영역 밑부분에는 형성되지 않는 MIS형 반도체장치.
  5. 제1항에서, 상기 우물영역은 상기 드레인영역보다 더 큰 깊이를 갖는 MIS형 반도체장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019840007019A 1983-12-07 1984-11-09 우물영역을 갖는 반도체기판상에 형성되는 mis형 반도체장치 KR890004797B1 (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP58230862A JPS60123055A (ja) 1983-12-07 1983-12-07 半導体装置及びその製造方法
JP58-230862 1983-12-07
JP?58-230862 1983-12-07

Publications (2)

Publication Number Publication Date
KR850005169A true KR850005169A (ko) 1985-08-21
KR890004797B1 KR890004797B1 (ko) 1989-11-27

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KR1019840007019A KR890004797B1 (ko) 1983-12-07 1984-11-09 우물영역을 갖는 반도체기판상에 형성되는 mis형 반도체장치

Country Status (5)

Country Link
US (1) US5128739A (ko)
EP (1) EP0144248B1 (ko)
JP (1) JPS60123055A (ko)
KR (1) KR890004797B1 (ko)
DE (1) DE3476944D1 (ko)

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EP0304541A1 (de) * 1987-08-18 1989-03-01 Deutsche ITT Industries GmbH Verfahren zum Herstellen implantierter Wannen und Inseln von integrierten CMOS-Schaltungen
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Also Published As

Publication number Publication date
EP0144248A2 (en) 1985-06-12
EP0144248A3 (en) 1985-12-18
KR890004797B1 (ko) 1989-11-27
DE3476944D1 (en) 1989-04-06
JPS60123055A (ja) 1985-07-01
US5128739A (en) 1992-07-07
EP0144248B1 (en) 1989-03-01

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