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KR840006872A - 반도체 집적회로장치 및 그 제조방법 - Google Patents

반도체 집적회로장치 및 그 제조방법 Download PDF

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KR840006872A
KR840006872A KR1019830005524A KR830005524A KR840006872A KR 840006872 A KR840006872 A KR 840006872A KR 1019830005524 A KR1019830005524 A KR 1019830005524A KR 830005524 A KR830005524 A KR 830005524A KR 840006872 A KR840006872 A KR 840006872A
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well region
semiconductor
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semiconductor layer
conductive
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KR900000817B1 (en
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아쓰오 와다나베 (외 5)
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미다 가쓰시게
가부시기가이샤 히다찌세이사꾸쇼
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/996—Masterslice integrated circuits using combined field effect technology and bipolar technology
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00—Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30—Devices controlled by electric currents or voltages
    • H10D48/32—Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0107—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs
    • H10D84/0109—Integrating at least one component covered by H10D12/00 or H10D30/00 with at least one component covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating IGFETs with BJTs the at least one component covered by H10D12/00 or H10D30/00 being a MOS device
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/40—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00 with at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of IGFETs with BJTs
    • H10D84/401—Combinations of FETs or IGBTs with BJTs

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  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)

Abstract

내용 없음

Description

반도체 집적회로장치 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제9도는 본원 발명의 제1의 실시예인 BiCMOS LSI의 개략평면도.
제10도는 본원 발명 제1의 실시예에 있어서의 불순물농도 분포를 나타낸 도면.
제11도는 본원 발명의 제1의 실시예의 개략평면도.

Claims (10)

  1. 제1도전형의 반도체기판상에 형성되는 소정의 도전형의 반도체층과, 상기 반도체층 표면의 소정 개소에 형성되며 상기 표면에서 상기 반도체기판방향을 향해 불순물농도가 작아지는 제2도전형의 제1웰영역과, 상기 반도체층 표면의 상기 제1웰영역과 접하며, 또한 상기 제1웰영역을 둘러싸서 형성되며, 상기 표면에서 상기 반도체기판방향을 향해 불순물농도가 작아지는 제1도전형의 제2웰영역과, 상기 제1웰영역과 상기 반도 체기판과의 사이에 각기 인접해서 설치되며, 또한 인접하는 상기 제1웰영역의 인접부보다 높은 불순물농도의 제2도전형의 제1매입영역과, 상기 제2웰영역과 상기 반도체기판과의 사이에 각기 실질적으로 인접해서 설치되며, 또한 입접하는 상기 제2웰영역의 인접부보다 높은 불순물농도의 제1도전형의 제2매입영역과, 상기 제1웰영역 및 제2웰영역에 각기 형성되는 반도체소자를 구비하는 것을 특징으로 하는 반도체 집적회로장치.
  2. 상기 제1웰영역에 형성되는 반도체소자는 종형바이폴라트랜지스터 및/또는 제1도전형 MOS 트랜지스터이며, 상기 제2웰영역에 형성되는 반도체소자는 제2도전형 MOS 트랜지스터임을 특징으로 하는 특허청구의 범위 1기재의 반도체 집적회로장치.
  3. 상기 소정의 도전형의 반도체층은 제2도전형의 반도체층임을 특징으로 하는 특허청구의 범위 1기재의 반도체 집적회로장치.
  4. 상기 소정의 도전형의 반도체층은 불순물농도분포가 대충 균일한반도체층임을 특징으로 하는 특허청구의 범위 1기재의 반도체 집적회로장치.
  5. 제1도전형의 반도체기판상에 형성되는 소정의 도전형의 반도체층과, 상기 반도체층의 표면의 소정개소에 형성되며, 상기 표면에서 상기 반도체기판방향을 향해서 불순물농도가 작아지는 제2도전형의 제1웰영역과, 상기 반도체층 표면의 상기 제1웰영역과는 다른 개소에 형성되며, 상기 표면에서 상기 반도체기판 방향을 향해서 불순물농도가 작아지는 제1도전형의 제2웰영역과, 상기 제1웰영역과 상기 반도체기판과의 사이에 각기 인접해서 설치되며, 또한 인접하는 상기 제1웰영역의 인접부보다 높은 불순물농도의 제2도전형의 제매입영역과, 상기 제2웰영역과 상기 반도체기판과의 사이에 각기 실질적으로 인접하며, 상기 제1매입영역과 실질적으로 접하고 또한 형기 제1매입영역을 둘러싸고 형성되며, 인접하는 형기 제2웰영역의 인접부보다 높은 불순물농도의 제1도전형의 제2매입영역과, 상기 제1웰영역 및 상기 제2웰영역에 각기 형성되는 반도체소자를 구비하는 것을 특징으로 하는 반도체 집적회로장치.
  6. 상기 제1웰영역에 형성되는 반도체소자는 종형바이폴라트랜지스터 및/또는 제1도전형 MOS 트랜지스터이며, 상기 제2웰영역에 형성되는 반도체소자는 제2도전형 MOS 트랜지스터임을 특징으로 하는 특허청구의 범위 5기재의 반도체 집적회로장치.
  7. 상기 소정의 도전형의 반도체층은 제2도전형의 반도체층임을 특징으로 하는 특허청구의 범위 5기재의 반도체 집적회로장치.
  8. 상기 소정의 도전형의 반도체층은 불순물농도분포가 대충 균일한 반도체층임을 특징으로 하는 특허청구의 범위 5기재의 반도체 집적회로장치.
  9. 상기 제1웰영역과 상기 제2웰영역과의 경계면과, 상기 제1메입영역과 상기 제2매입영역과의 경계면이 대충 동일 평면상에 있는 것을 특징으로 하는 특허청구의 범위 5기재의 반도체 집적회로장치.
  10. 제1도전형의 반도체기판 표면의 소정 개소에 제2도전형의 제1매입영역을 형성하는 공정과, 상기 반도체기판 표면에 상기 제1매입영역과 실질적으로 접하며, 또한 상기 제1매입영역을 둘러싸도록 제1도전형의 제2매입영역을 형성하는 공정과, 상기 반도체기판상에 소정의 도전형의 반도체층을 적층하는 공정과, 상기 반도체층표면의 상기 제1매입영역에 대응하는 개소에, 제2도전형의 제1웰영역을 형성하는 공정과, 상기 반도체층 표면의 상기 제1매입영역에 대응하는 개소에, 상기 제1웰영역과 접하며, 또한 상기 제1웰영역을 둘러싸도록 제1도전형의 제2웰영역을 형성하는 공정과, 상기 제1웰영역 및 상기 제2웰영역에 반도체소자를 형성하는 공정을 최소한 갖는 것을 특징으로 하는 반도체 집적회로장치의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR8305524A 1982-11-24 1983-11-22 Semiconductor ic device manufacturing method Expired KR900000817B1 (en)

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Application Number Priority Date Filing Date Title
JP204671 1982-11-24
JP57204671A JPS5994861A (ja) 1982-11-24 1982-11-24 半導体集積回路装置及びその製造方法

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KR840006872A true KR840006872A (ko) 1984-12-03
KR900000817B1 KR900000817B1 (en) 1990-02-17

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US (5) US4980744A (ko)
EP (1) EP0110313B1 (ko)
JP (1) JPS5994861A (ko)
KR (1) KR900000817B1 (ko)
DE (1) DE3379621D1 (ko)

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US4921811A (en) 1990-05-01
US4980744A (en) 1990-12-25
DE3379621D1 (en) 1989-05-18
JPS5994861A (ja) 1984-05-31
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US5672897A (en) 1997-09-30
EP0110313B1 (en) 1989-04-12
JPH058583B2 (ko) 1993-02-02
EP0110313A2 (en) 1984-06-13
US5049967A (en) 1991-09-17
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US5508549A (en) 1996-04-16

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