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KR870005464A - 반도체장치 - Google Patents

반도체장치 Download PDF

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Publication number
KR870005464A
KR870005464A KR860009872A KR860009872A KR870005464A KR 870005464 A KR870005464 A KR 870005464A KR 860009872 A KR860009872 A KR 860009872A KR 860009872 A KR860009872 A KR 860009872A KR 870005464 A KR870005464 A KR 870005464A
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South Korea
Prior art keywords
semiconductor layer
source
drain regions
conductive semiconductor
semiconductor device
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KR860009872A
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English (en)
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KR930001899B1 (ko
Inventor
요시아키 야자와
유타카 고바야시
아키라 후카미
다카히로 나가노
Original Assignee
미타 가쓰시게
가부시키가이샤 히타치세이사쿠쇼
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Publication of KR870005464A publication Critical patent/KR870005464A/ko
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Publication of KR930001899B1 publication Critical patent/KR930001899B1/ko
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6757—Thin-film transistors [TFT] characterised by the structure of the channel, e.g. transverse or longitudinal shape or doping profile
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/637—Lateral IGFETs having no inversion channels, e.g. buried channel lateral IGFETs, normally-on lateral IGFETs or depletion-mode lateral IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/67—Thin-film transistors [TFT]
    • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
    • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
    • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0167—Manufacturing their channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/90—MOSFET type gate sidewall insulating spacer

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  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

내용 없음

Description

반도체장치
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본원 발명의 일실시예를 나타낸 MOSFET의 단면도.
제8도는 제1도에 나타낸 본원 발명 MOSFET에 있어서의 공핍층과 전기력선의 발생상황을 나타낸 도면.
제12도는 본원 발명의 다른 실시예에 의한 P채널 MOSFET는 나타낸 단면도.
*도면의 주요 부분에 대한 부호의 설명
(1) : 반도체기판 (2) : 게이트절연막
(3) : 게이트 (4) : 소스영역
(5) : 드레인영역 (6) : N층
(7) : P층

Claims (5)

  1. 소스, 드레인 양 영역간에 게이트절연막을 통해 게이트가 설치되며, 게이트 바로 밑에 있어서의 소스, 드레인 양 영역간의 반도체층이 게이트절연막에서 떨어짐에 따라서, 소스, 드레인 양영역과는 반대도전형의 반도체층 및 동 도전형의 반도체층으로 되어 있는 반도체장치에 있어서, 반대도전형 반도체층의 소스, 드레인 양영역간 치수보다 그 밑의 동 도전형 반도체층의 소스, 드레인 양영역간 치수를 길게 한 것을 특징으로 하는 반도체장치.
  2. 제1항에 있어서, 소스, 드레인 양영역, 반대 및 동 도전형의 각 반도체층은 소스, 드레인 양 영역과는 반대도전형의 반도체기판상에 설치되며, 반대도전형 반도체층 및 반도체기판이 동 도전형 반도체층과 형성하는 공핍층이 연결되어 있는 것을 특징으로 하는 반도체장치.
  3. 제1항에 있어서, 소스, 드레인 양 영역, 반대 및 동 도전형의 각 반도체층은 절연체상에 설치되며, 반대도전형 반반체층이 동 도전형 반도체층과 형성하는 공핍층은 절연체에 접하고 있는 것을 특징으로 하는 반도체장치.
  4. 제1항에 있어서, 소스, 드레인 양 영역과 반대도전형 및 동 도전형 반도체층과의 사이에 소스, 드레인 양 영역과 동 도전형 반도체층간의 중간 불순물 농도로 소스, 드레인 양 영역과 동 도전형의 반도체층이 설치되며, 중간 불순물농도의 반도체층을 반대도전형 반도체층 밑의 동 도전형 반도체층의 일부로 하고 있는 것을 특징으로 하는 반도체장치.
  5. 제1항에 있어서, 소스, 드레인 양 영역과 반대도전형 반도체층간에 소스, 드레인 양 영역과 동 도전형 반도체층간의 중간 불순물 농도를 소스, 드레인 양 영역과 동 도전형의 반도체층의 설치되어 있는 것을 특징으로 하는 반도체 장치.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019860009872A 1985-11-29 1986-11-22 반도체 장치 Expired - Fee Related KR930001899B1 (ko)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP60267152A JPS62128175A (ja) 1985-11-29 1985-11-29 半導体装置
JP60-267152 1985-11-29

Publications (2)

Publication Number Publication Date
KR870005464A true KR870005464A (ko) 1987-06-09
KR930001899B1 KR930001899B1 (ko) 1993-03-19

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US (1) US4819043A (ko)
JP (1) JPS62128175A (ko)
KR (1) KR930001899B1 (ko)

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KR930001899B1 (ko) 1993-03-19
JPS62128175A (ja) 1987-06-10
US4819043A (en) 1989-04-04

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