JP2013149779A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2013149779A JP2013149779A JP2012008952A JP2012008952A JP2013149779A JP 2013149779 A JP2013149779 A JP 2013149779A JP 2012008952 A JP2012008952 A JP 2012008952A JP 2012008952 A JP2012008952 A JP 2012008952A JP 2013149779 A JP2013149779 A JP 2013149779A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 170
- 230000001070 adhesive effect Effects 0.000 claims abstract description 37
- 239000000463 material Substances 0.000 claims abstract description 37
- 239000000853 adhesive Substances 0.000 claims abstract description 36
- 239000011347 resin Substances 0.000 claims description 21
- 229920005989 resin Polymers 0.000 claims description 21
- 239000004642 Polyimide Substances 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 3
- 229910052710 silicon Inorganic materials 0.000 claims description 3
- 239000010703 silicon Substances 0.000 claims description 3
- 239000008393 encapsulating agent Substances 0.000 claims 1
- 238000007789 sealing Methods 0.000 claims 1
- 238000001514 detection method Methods 0.000 abstract description 6
- 239000003990 capacitor Substances 0.000 description 7
- 238000012545 processing Methods 0.000 description 5
- 238000000926 separation method Methods 0.000 description 4
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 3
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 238000007747 plating Methods 0.000 description 3
- 229910000679 solder Inorganic materials 0.000 description 3
- 238000010304 firing Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 238000013459 approach Methods 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000012447 hatching Effects 0.000 description 1
- 230000020169 heat generation Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 230000000630 rising effect Effects 0.000 description 1
- 230000035945 sensitivity Effects 0.000 description 1
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- H01L23/495—Lead-frames or other flat leads
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- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2924/13—Discrete devices, e.g. 3 terminal devices
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- Die Bonding (AREA)
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Abstract
【解決手段】本発明の半導体装置では、駆動用の半導体チップ14を固着する第1の搭載領域8と制御用の半導体チップ15を固着する第2の搭載領域9とが、分離して形成される。そして、第1の搭載領域8に突出領域8aが形成され、その突出領域8aが、第2の搭載領域9側へと延在し、第2の半導体チップ15は、絶縁性の接着シート材16を介して突出領域8a及び第2の搭載領域9上面に固着される。この構造により、両チップ間のショートが防止され、制御用の半導体チップでの温度検知の精度が向上される。
【選択図】図2
Description
2 樹脂パッケージ
4a リード
7 フレーム
8 第1の搭載領域
8a 突出領域
9 第2の搭載領域
14 半導体チップ
15 半導体チップ
16 接着シート材
33 第1の搭載領域
36 開口部
37 接着シート材
Claims (8)
- 第1の搭載領域と、
前記第1の搭載領域の近傍に配置され、前記第1の搭載領域と分離して形成される第2の搭載領域と、
前記第1及び第2の搭載領域の近傍に配置されるリードと、
前記第1の搭載領域上に固着された第1の半導体チップと、
前記第1及び第2の搭載領域上に固着され、前記第1の半導体チップを制御する第2の半導体チップと、
前記第1及び第2の搭載領域、前記リード及び前記第1及び第2の半導体チップを被覆する樹脂封止体とを有し、
前記第1の搭載領域には、前記第2の搭載領域側へと突出する突出領域が形成され、
前記第2の半導体チップ下方には少なくとも前記突出領域の一部が配置されるように、前記第2の半導体チップは、絶縁性の接着シート材を介して前記第1及び第2の搭載領域上に固着されることを特徴とする半導体装置。 - 前記第2の搭載領域には、少なくとも前記突出領域の一部を囲むように窪み領域が形成され、
前記第2の半導体チップは、前記突出領域及び前記窪み領域周辺の前記第2の搭載領域上に固着されることを特徴とする請求項1に記載の半導体装置。 - 前記第2の半導体チップは、前記第1の半導体チップの温度を検知し、制御するサーマルシャットダウン回路を有することを特徴とする請求項2に記載の半導体装置。
- 前記接着シート材は、ポリイミドテープ、シリコンテープまたはDAF材から形成されることを特徴とする請求項2または請求項3に記載の半導体装置。
- 前記接着シート材は、前記第2の搭載領域と対向し、前記突出領域が形成される前記第1の搭載領域の側辺を越えて、前記第1の搭載領域側まで配置されることを特徴とする請求項4に記載の半導体装置。
- 少なくとも搭載領域と、
前記搭載領域の近傍に配置されるリードと、
前記搭載領域の表面側に固着された第1の半導体チップと、
前記搭載領域に形成された開口部を塞ぐように、前記搭載領域の裏面側に貼り合わされた絶縁性の接着シート材と、
前記開口部内の前記接着シート上に固着され、前記第1の半導体チップを制御する第2の半導体チップと、
前記搭載領域、前記リード及び前記第1及び第2の半導体チップを被覆する樹脂封止体とを有することを特徴とする半導体装置。 - 前記第2の半導体チップは、前記第1の半導体チップの温度を検知し、制御するサーマルシャットダウン回路を有することを特徴とする請求項6に記載の半導体装置。
- 前記接着シート材は、ポリイミドテープ、シリコンテープまたはDAF材から形成されることを特徴とする請求項7に記載の半導体装置。
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2012008952A JP2013149779A (ja) | 2012-01-19 | 2012-01-19 | 半導体装置 |
CN201610075119.4A CN105529314B (zh) | 2012-01-19 | 2013-01-16 | 半导体装置 |
CN201310014810.8A CN103219313B (zh) | 2012-01-19 | 2013-01-16 | 半导体装置 |
DE202013012738.4U DE202013012738U1 (de) | 2012-01-19 | 2013-01-18 | Halbleitervorrichtung |
US13/745,330 US8759955B2 (en) | 2012-01-19 | 2013-01-18 | Semiconductor device with chips on isolated mount regions |
EP13151939.9A EP2618371B1 (en) | 2012-01-19 | 2013-01-18 | Semiconductor device |
US14/291,159 US20140264807A1 (en) | 2012-01-19 | 2014-05-30 | Semiconductor device |
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JP2012008952A JP2013149779A (ja) | 2012-01-19 | 2012-01-19 | 半導体装置 |
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JP2012008952A Pending JP2013149779A (ja) | 2012-01-19 | 2012-01-19 | 半導体装置 |
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US (2) | US8759955B2 (ja) |
EP (1) | EP2618371B1 (ja) |
JP (1) | JP2013149779A (ja) |
CN (2) | CN103219313B (ja) |
DE (1) | DE202013012738U1 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
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JPWO2016157394A1 (ja) * | 2015-03-30 | 2017-06-08 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2018056358A (ja) * | 2016-09-29 | 2018-04-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
CN110660786A (zh) * | 2019-08-21 | 2020-01-07 | 深圳市晶导电子有限公司 | Led驱动电源的集成电路及其制造方法及led驱动电源 |
US12080692B2 (en) | 2021-04-19 | 2024-09-03 | Mitsubishi Electric Corporation | Semiconductor device and method for manufacturing semiconductor device |
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CN107275394B (zh) * | 2016-04-08 | 2020-08-14 | 株洲中车时代电气股份有限公司 | 一种功率半导体模块及其自保护方法 |
JP7131903B2 (ja) * | 2017-12-08 | 2022-09-06 | ローム株式会社 | 半導体パッケージ |
CN112928091A (zh) * | 2019-12-05 | 2021-06-08 | 深圳晶鼎科实业有限公司 | 一种驱动芯片封装结构 |
JP7603400B2 (ja) | 2020-09-10 | 2024-12-20 | ローム株式会社 | 半導体装置 |
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JPH02148758A (ja) * | 1988-11-29 | 1990-06-07 | Matsushita Electron Corp | 半導体装置用リードフレーム |
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JPWO2016157394A1 (ja) * | 2015-03-30 | 2017-06-08 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
JP2018056358A (ja) * | 2016-09-29 | 2018-04-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法および半導体装置 |
CN110660786A (zh) * | 2019-08-21 | 2020-01-07 | 深圳市晶导电子有限公司 | Led驱动电源的集成电路及其制造方法及led驱动电源 |
CN110660786B (zh) * | 2019-08-21 | 2024-02-27 | 深圳市晶导电子有限公司 | Led驱动电源的集成电路及其制造方法及led驱动电源 |
US12080692B2 (en) | 2021-04-19 | 2024-09-03 | Mitsubishi Electric Corporation | Semiconductor device and method for manufacturing semiconductor device |
Also Published As
Publication number | Publication date |
---|---|
EP2618371B1 (en) | 2018-12-12 |
CN103219313A (zh) | 2013-07-24 |
US20130187261A1 (en) | 2013-07-25 |
EP2618371A3 (en) | 2017-02-22 |
CN103219313B (zh) | 2016-01-06 |
US20140264807A1 (en) | 2014-09-18 |
CN105529314A (zh) | 2016-04-27 |
CN105529314B (zh) | 2020-10-13 |
EP2618371A2 (en) | 2013-07-24 |
DE202013012738U1 (de) | 2019-01-08 |
US8759955B2 (en) | 2014-06-24 |
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