CN105529314B - 半导体装置 - Google Patents
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Abstract
本发明提供一种半导体装置。在现有的半导体装置中,存在难以防止芯片之间发生短路且难以提高控制用半导体芯片的温度检测精度的问题。在本发明的半导体装置中,分开形成固定安装驱动用半导体芯片(14)的第一搭载区域(8)与固定安装控制用半导体芯片(15)的第二搭载区域(9),而且在第一搭载区域(8)形成突出区域(8a),该突出区域(8a)向第二搭载区域(9)侧延伸,第二半导体芯片(15)经由绝缘性粘接片材(16)固定安装在突出区域(8a)及第二搭载区域(9)的上表面。通过该结构,能够防止两芯片之间发生短路,能够提高控制用半导体芯片的温度检测精度。
Description
本分案申请是基于申请号为201310014810.8,申请日为2013年1月16日,发明名称为“半导体装置”的中国专利申请的分案申请。
技术领域
本发明涉及例如在应用于车载用点火装置(点火器)的半导体封装中内置有驱动用半导体芯片及控制驱动用半导体芯片的控制用半导体芯片的半导体装置。
背景技术
作为现有半导体装置的一个实施例,已知如下的结构。
如图7所示,在半导体装置61的由引线框形成的载置台62上,固定有半导体元件63与片状电容64。载置台62形成得大于半导体元件63,片状电容64搭载在半导体元件63周围的载置台62上。而且,在片状电容64的搭载区域,载置台62通过其表面侧被半蚀刻而形成有凹部65。如图7所示,在凹部65内配置有聚酰亚胺胶带等绝缘胶带66,在该绝缘胶带66上固定安装有片状电容64。通过该结构,能够防止片状电容64经由载置台62与半导体63发生短路(例如参照专利文献1)。
另外,作为现有半导体装置的另一个实施例,已知如下的结构。
如图8所示,在一分为二的其中一个接头片(タブ)71的主表面上固定有IC芯片72,在另一个接头片73的主表面上固定有电子部件74,至少通过被分割的接头片71,73的结构,能够防止电子部件74经由接头片71,73与IC芯片72发生短路。而且,如砂状的阴影所示,也可以在另一个接头片73的主表面上形成绝缘膜75(例如参照专利文献2)。
专利文献1:(日本)特开2006-245618号公报(第4-5页、第5-8图)
专利文献2:(日本)实开昭63-187353号的微型薄膜(第4-5页、第1-2图)
在车载用点火装置的树脂封装内,内置有例如作为开关元件内置了IGBT等大电流元件的驱动用半导体芯片及控制该驱动用半导体芯片的控制用半导体芯片。控制用半导体芯片具有温度检测元件与过热保护电路,被配置在驱动用半导体芯片的附近。而且,控制用半导体芯片检测驱动用半导体芯片的温度,当检测出设定值以上的温度时,强制关断驱动用半导体芯片,防止驱动用半导体芯片的温度异常升高,防止驱动用半导体芯片着火。
此时,如图7所示,通过将驱动用半导体芯片与控制用半导体芯片配置在同一岛部上,能够精确地检测驱动用半导体芯片温度升高的状况。而且,通过使用绝缘胶带来防止两个半导体芯片发生短路,但在两个半导体芯片被配置在同一岛部上的结构中,由于绝缘胶带的粘贴工序及贴片接合工序中的位置确认误差等制造上的误差,存在易于使两个半导体芯片发生短路的问题。
而且,在同一岛部上配置两个半导体芯片的结构中,该岛部电位成为向驱动用半导体芯片施加的电位。因此,在向控制用半导体芯片施加不同的电位时,需要对引线进行构图直至该岛部附近,从而存在限制图案设计自由度的问题。
另一方面,如图8所示,在分割接头片的结构中,驱动用半导体芯片与控制用半导体芯片的间隔距离由于引线框的加工条件而存在难以缩小一定幅度以上的问题。进而,通过该结构,在控制用半导体芯片检测驱动用半导体芯片温度升高的状况时,因为主要经由树脂封装的树脂进行检测,所以,由于材料的导热率的关系,存在难以精确地进行检测的问题。
发明内容
本发明是鉴于上述问题而提出的,本发明的半导体装置的特征在于,具有:第一搭载区域;配置在所述第一搭载区域的附近且与所述第一搭载区域分开形成的第二搭载区域;配置在所述第一搭载区域及所述第二搭载区域的附近的引线;固定安装在所述第一搭载区域上的第一半导体芯片;固定安装在所述第一搭载区域及所述第二搭载区域上并控制所述第一半导体芯片的第二半导体芯片;覆盖所述第一搭载区域及所述第二搭载区域、所述引线、所述第一半导体芯片及所述第二半导体芯片的树脂密封体;在所述第一搭载区域形成有向所述第二搭载区域侧突出的突出区域;所述第二半导体芯片经由绝缘性粘接片材固定安装在所述第一搭载区域及所述第二搭载区域上,以使在所述第二半导体芯片下方至少配置有所述突出区域的一部分。
在本发明中,驱动用半导体芯片与控制用半导体芯片固定安装在不同的搭载区域上,但是固定安装驱动用半导体芯片的搭载区域的一部分配置至控制用半导体芯片的下方。通过该结构,控制用半导体芯片经由搭载区域也能够进行温度检测。
而且,在本发明中,通过将控制用半导体芯片端部的大部分配置在第二搭载区域上,能够构成使驱动用半导体芯片与控制用半导体芯片难以发生短路的结构。
而且,在本发明中,控制用半导体芯片对驱动用半导体芯片精度地进行温度检测,通过适当地关断驱动用半导体芯片,使驱动用半导体芯片难以因发热而遭到破坏。
而且,在本发明中,通过分开配置固定安装驱动用半导体芯片的搭载区域与固定安装控制用半导体芯片的搭载区域,能够分别施加不同的电位。
而且,在本发明中,通过使用绝缘性粘接片材,在搭载区域上固定安装控制用半导体芯片,能够维持控制用半导体芯片的温度检测功能,并且能够防止两芯片之间发生短路。
另外,在本发明中,在固定安装驱动用半导体芯片的搭载区域形成开口部,经由该开口部,使用绝缘性粘接片材固定安装控制用半导体芯片,由此,能够防止两芯片之间发生短路。
附图说明
图1是用来说明本发明实施方式的半导体装置的立体图;
图2是用来说明本发明实施方式的半导体装置的(A)俯视图、(B)俯视图;
图3是用来说明本发明实施方式的半导体装置的(A)剖面图、(B)剖面图;
图4是用来说明本发明实施方式的半导体装置的(A)俯视图、(B)俯视图;
图5是用来说明本发明实施方式的半导体装置的(A)剖面图、(B)剖面图;
图6是用来说明本发明实施方式的半导体装置的(A)俯视图、(B)俯视图;
图7是用来说明现有实施方式的半导体装置的剖面图;
图8是用来说明现有实施方式的半导体装置的立体图。
附图标记说明
1 半导体装置;2 树脂封装;4a 引线;7 框架;8 第一搭载区域;8a 突出区域;9第二搭载区域;14 半导体芯片;15 半导体芯片;16 粘接片材;33 第一搭载区域;36 开口部;37 粘接片材。
具体实施方式
下面,对本发明第一实施方式的半导体装置进行说明。图1是半导体装置表面侧的立体图,图2(A)是说明图1所示的半导体装置所使用的框架结构的俯视图,图2(B)是说明图1所示的半导体装置内的结构的俯视图,图3(A)是说明图2(B)所示的A-A线方向的剖面图,图3(B)是说明图2(B)所示的B-B线方向的剖面图。
如图1所示,半导体装置1的树脂封装2为长方体形状,从树脂封装2的长度方向的侧面3导出多条引线4a~4f。另一方面,在树脂封装2的宽度方向的侧面5配置有用于拧紧螺钉的U形孔6。虽然未图示,但是引线4例如被弯曲加工成直角形状,通过焊料固定在安装基板的贯通孔内。
图2(A)表示在树脂封装2内配置的框架7,框架7通常以铜为主材料,但也可以以Fe为主材料。而且,框架7的厚度例如为200μm。另外,框架7通过蚀刻加工或冲压加工等,例如被区划为第一至第四搭载区域8,9,10,11和多条引线区域4a~4f。单点划线12表示树脂封装2的外形线。
如图2A所示,第一搭载区域8在纸面Y轴方向上与引线4a一体形成。而且,第一搭载区域8在纸面X方向上具有向第二搭载区域9侧突出的凸形状突出区域8a,但该突出区域8a通过分离沟13与第二搭载区域9分离。而且,突出区域8a构成为延伸至固定安装于第二搭载区域9的半导体芯片15(参照图2(B))下方,突出区域8a优选为突出至第二搭载区域9的一半宽度(X轴方向的宽度)以上。
另一方面,第二搭载区域9在纸面X轴方向上具有围绕突出区域8a的凹形状的凹陷区域9a。而且,固定安装在第二搭载区域9的半导体芯片15配置在该凹陷区域9a,所以凹陷区域9a的宽度(Y轴方向的宽度)窄于半导体芯片15的宽度。需要说明的是,只要将凹陷区域9a配置为通过调节分离沟13的宽度能够至少围绕突出区域8a的一部分即可。
多条引线4a~4f被配置为从树脂封装2的侧面3侧导出。而且,引线4b~4d被配置在第一及第二搭载区域8,9的附近。引线4e与第三搭载区域10一体形成,引线4f与第四搭载区域11一体形成。
另外,在框架7上施行Pd电镀、Ag电镀、Ni/Pd/Ag电镀等电镀。
图2(B)表示固定安装了半导体芯片等的框架,在第一搭载区域8上,通过Ag膏、焊料等粘接材料20(参照图3(A))固定安装有作为开关元件(驱动用元件)内置有例如IGBT的分立型半导体芯片14。
在第二搭载区域9上,通过绝缘性粘接片材16固定安装有内置了用来控制半导体芯片14的LSI元件的半导体芯片15。在半导体芯片15上,例如在其表面侧配置温度检测元件而形成过热保护电路。由此,在半导体芯片15中检测半导体芯片14温度升高的状况,当半导体芯片14的温度升高为设定温度以上时强制关断半导体芯片14。
需要说明的是,粘接片材16覆盖在分离沟13上,也可以配置至第一搭载区域8侧。在该情况下,容易通过粘接片材16维持第一搭载区域8与第二搭载区域9的平坦性,也能够以稳定的状态固定安装第二半导体芯片15。因此,在引线焊接工序中,也能够减少与金属线的连接不良的问题,从而提高成品率。
在第三搭载区域10上,通过导电性粘接材料固定安装有半导体芯片17,在第三及第四搭载区域10,11上,通过Ag膏、焊料等粘接材料21(参照图3(A))固定安装有片状电容18。如图所示,形成有由金属线19电连接半导体芯片14,15之间等而具有过热保护电路的例如车载用点火器的树脂封装2。
图3(A)是表示树脂封装2的A-A线方向(参照图2(B))的剖面,半导体芯片14通过粘接材料20固定安装在第一搭载区域8上,半导体芯片15通过粘接片材16固定安装在第一搭载区域8的突出区域8a及第二搭载区域9上。粘接片材16由例如聚酰亚胺胶带、硅胶带及DAF(Die Attach Film:芯片粘接膜)材料等具有粘接性的绝缘性材料形成。作为粘接片材16使用聚酰亚胺胶带,从而能够减薄其厚度,能够提高温度检测的灵敏度。另外,片状电容18通过粘接材料21固定安装在第三及第四搭载区域10,11上。
如图所示,半导体芯片14所产生的热量向第一搭载区域8传递,经由突出区域8a再向半导体芯片15的下方传递。由于框架7以铜为主材料,所以其导热率比构成树脂封装2的树脂材料良好。通过该结构,半导体芯片15即使经由框架7也能够检测到半导体芯片14的温度升高的状况,能够精确地检测半导体芯片14的温度状况。当半导体芯片14的温度异常升高时,通过直接关断半导体芯片14,就能够防止半导体芯片14着火。
而且,通过使突出区域8a突出至半导体芯片15的一半宽度(X轴方向的宽度)以上,能够使导热率良好的框架7的区域增大,半导体芯片15能够精确地检测半导体芯片14的温度状况。而且,在突出区域8a,至少在固定安装有半导体芯片15的区域配置有粘接片材16,从而能够防止半导体芯片15经由突出区域8a与半导体芯片14发生短路。
图3(B)表示树脂封装2的B-B线方向(参照图2(B))的剖面,半导体芯片15通过粘接片材16固定安装在第一搭载区域8的突出区域8a及第二搭载区域9。如圆形标识22所示,粘接片材16被配置至半导体芯片15端部的外侧,因此不会发生上述的短路问题。
而且,在固定安装半导体芯片15时,在第一及第二搭载区域8,9的上表面配置粘接片材16后,在粘接片材16上配置半导体芯片15。即使在该制造工序时的位置确认误差等导致半导体芯片15的端部向第二搭载区域9靠近或者与第二搭载区域9接触的情况下,第一及第二搭载区域8,9被分离沟13分离,所以不会发生上述的短路问题。
需要说明的是,在本实施方式中,以在第二搭载区域9上未特别施加电位的状态的情况为例进行了说明,但不限于该情况。例如第二搭载区域9也可以施加有半导体芯片15的GND电位。在该情况下,通过减少向第二搭载区域9的附近配置的引线数量,能够提高框架构图的设计自由度。
接着,对本发明第二实施方式的半导体装置进行说明。图4(A)是说明图1所示的半导体装置所使用的框架结构的俯视图,图4(B)是说明图1所示的半导体装置内的结构的俯视图,图5(A)是说明图4(B)所示的C-C线方向的剖面图,图5(B)是说明图4(B)所示的D-D线方向的剖面图。需要说明的是,在第二实施方式中,对于与第一实施方式相同的结构部件,使用与第一实施方式相同的附图标记,并参照其说明,在此省略该说明。
图4(A)表示在单点划线32所示的树脂封装2内配置的框架31,框架31与框架7同样,通常以铜为主材料,但也可以以Fe为主材料。而且,如图所示,通过对框架31进行蚀刻加工或冲压加工等,能够将框架31区划为例如第一~第三搭载区域33~35与多条引线区域4a~4f。
需要说明的是,在本实施方式中,第一搭载区域33为第一实施方式的第一及第二搭载区域8,9一体形成的形状,第二搭载区域34对应于第一实施方式的第三搭载区域10,第三搭载区域35对应于第一实施方式的第四搭载区域。
如图所示,第一搭载区域33在纸面Y轴方向上与引线4a一体形成。而且,第一搭载区域33在纸面X轴方向的左侧形成开口部36,该开口部36具有大于半导体芯片15的开口形状。
图4(B)表示固定安装了半导体芯片等的框架,半导体芯片14经由粘接材料20固定安装在第一搭载区域33的上表面。而且,如图5(A)所示,粘接片材37为了堵塞开口部36而与第一搭载区域33的背面侧贴合。另外,如图5(B)的圆形标识38所示,半导体芯片15在开口部36内固定安装在粘接片材37的上表面,半导体芯片15的端部与第一搭载区域33分开而配置。需要说明的是,粘接片材37由与第一实施方式的粘接片材16相同的材料形成。
通过该结构,能够防止半导体芯片14,15彼此发生短路。而且,半导体芯片14,15与分别固定在不同的搭载区域的结构相比,能够缩短半导体芯片14,15之间的间隔距离,所以半导体芯片15能够精确地检测半导体芯片14的温度状况。
在上述第一及第二实施方式中,对在树脂封装2内配置一个驱动用半导体芯片14且通过一个控制用半导体芯片控制该半导体芯片14的情况进行了说明,但本发明不限于该情况。
例如,如图6(A)所示,也可以在单点划线39所示的树脂封装内配置四个驱动用半导体芯片40,通过一个控制用半导体芯片41控制该四个半导体芯片40。如图所示,四个半导体芯片40分别固定安装在不同的搭载区域42~45上,半导体芯片41固定安装在上述粘接片材46上。如上所述,通过粘接片材46,也能够维持各搭载区域42~45的平坦性。
而且,如图6(B)所示,也可以在单点划线47所示的树脂封装内配置六个驱动用半导体芯片48,通过一个控制用半导体芯片49控制该六个半导体芯片48。与图6(A)同样,六个半导体芯片48分别固定安装在不同的搭载区域50~55上,半导体芯片49固定安装在上述粘接片材56上。如上所述,通过粘接片材56,也能够维持各个搭载区域50~55的平坦性。
另外,在不脱离本发明要旨的范围内能够进行各种变更。
Claims (5)
1.一种半导体装置,包括:
具有顶面和底面的引线框;
所述引线框中的开口部,从所述引线框的背面延伸至所述引线框的顶面;
从所述引线框延伸的多条引线;
有顶面和底面的绝缘性的粘接片材,其中所述绝缘性的粘接片材的顶面粘接到所述引线框的背面,其中所述绝缘性的粘接片材的顶面的至少一部分在所述引线框中的开口部下方以堵塞开口部的方式延伸;
第一半导体芯片,固定到所述引线框的顶面;
第二半导体芯片,安装到所述引线框的开口部内,并附接到在所述引线框中的开口部下方延伸的所述绝缘性的粘接片材的顶面的所述部分,其中第二半导体芯片的覆盖区小于所述引线框中的开口部的覆盖区;以及
树脂密封体,至少部分地包封第二半导体芯片、所述绝缘性的粘接片材和所述引线框,其中所述绝缘性的粘接片材的顶面和背面都接触所述树脂密封体。
2.根据权利要求1所述的半导体装置,其中所述绝缘性的粘接片材由聚酰亚胺胶带、硅胶带和芯片粘接膜DAF材料中的任何一种形成。
3.根据权利要求1所述的半导体装置,其中所述第二半导体芯片与所述引线框中的所述开口部分开。
4.根据权利要求1所述的半导体装置,其中所述第二半导体芯片被配置为控制所述第一半导体芯片。
5.根据权利要求4所述的半导体装置,其中所述第二半导体芯片包括过热保护电路,所述过热保护电路被配置为检测和控制所述第一半导体芯片的温度。
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5373188A (en) * | 1992-11-04 | 1994-12-13 | Mitsubishi Denki Kabushiki Kaisha | Packaged semiconductor device including multiple semiconductor chips and cross-over lead |
CN102201402A (zh) * | 2010-03-23 | 2011-09-28 | 三垦电气株式会社 | 半导体装置 |
Family Cites Families (42)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6114731A (ja) * | 1984-06-29 | 1986-01-22 | Nec Kansai Ltd | 半導体装置 |
EP0276450A1 (de) | 1987-01-23 | 1988-08-03 | Xmit Ag | Datenschutzschaltung zur Sperrung der Uebertragung von Signalen über einen Bus |
JPH02133986A (ja) * | 1988-11-15 | 1990-05-23 | Shinko Electric Ind Co Ltd | 樹脂封止モジュールとその製造方法 |
JPH02148758A (ja) * | 1988-11-29 | 1990-06-07 | Matsushita Electron Corp | 半導体装置用リードフレーム |
US5291060A (en) * | 1989-10-16 | 1994-03-01 | Shinko Electric Industries Co., Ltd. | Lead frame and semiconductor device using same |
JPH04162556A (ja) * | 1990-10-25 | 1992-06-08 | Mitsubishi Electric Corp | リードフレーム及びその製造方法 |
US5455454A (en) * | 1992-03-28 | 1995-10-03 | Samsung Electronics Co., Ltd. | Semiconductor lead frame having a down set support member formed by inwardly extending leads within a central aperture |
EP0595021A1 (en) * | 1992-10-28 | 1994-05-04 | International Business Machines Corporation | Improved lead frame package for electronic devices |
JP3299421B2 (ja) * | 1995-10-03 | 2002-07-08 | 三菱電機株式会社 | 電力用半導体装置の製造方法およびリードフレーム |
US5894108A (en) * | 1997-02-11 | 1999-04-13 | National Semiconductor Corporation | Plastic package with exposed die |
JP2891692B1 (ja) * | 1997-08-25 | 1999-05-17 | 株式会社日立製作所 | 半導体装置 |
US6114756A (en) * | 1998-04-01 | 2000-09-05 | Micron Technology, Inc. | Interdigitated capacitor design for integrated circuit leadframes |
JP2000049184A (ja) * | 1998-05-27 | 2000-02-18 | Hitachi Ltd | 半導体装置およびその製造方法 |
JP2930079B1 (ja) * | 1998-08-06 | 1999-08-03 | サンケン電気株式会社 | 半導体装置 |
JP2000058735A (ja) * | 1998-08-07 | 2000-02-25 | Hitachi Ltd | リードフレーム、半導体装置及び半導体装置の製造方法 |
JP3871486B2 (ja) * | 1999-02-17 | 2007-01-24 | 株式会社ルネサステクノロジ | 半導体装置 |
US6256200B1 (en) * | 1999-05-27 | 2001-07-03 | Allen K. Lam | Symmetrical package for semiconductor die |
US7138708B2 (en) * | 1999-09-24 | 2006-11-21 | Robert Bosch Gmbh | Electronic system for fixing power and signal semiconductor chips |
JP3491744B2 (ja) * | 1999-10-22 | 2004-01-26 | シャープ株式会社 | 半導体装置 |
JP4651153B2 (ja) * | 1999-10-28 | 2011-03-16 | ローム株式会社 | 半導体装置 |
JP2002134674A (ja) * | 2000-10-20 | 2002-05-10 | Hitachi Ltd | 半導体装置およびその製造方法 |
US6716836B2 (en) * | 2001-03-22 | 2004-04-06 | Boehringer Ingelheim (Canada) Ltd. | Non-nucleoside reverse transcriptase inhibitors |
US6608375B2 (en) * | 2001-04-06 | 2003-08-19 | Oki Electric Industry Co., Ltd. | Semiconductor apparatus with decoupling capacitor |
TW488054B (en) * | 2001-06-22 | 2002-05-21 | Advanced Semiconductor Eng | Semiconductor package for integrating surface mount devices |
US7167377B2 (en) * | 2001-11-26 | 2007-01-23 | Sumitoo Wiring Systems, Ltd. | Circuit-constituting unit and method of producing the same |
US7482699B2 (en) * | 2002-06-05 | 2009-01-27 | Renesas Technology Corp. | Semiconductor device |
JP4248953B2 (ja) * | 2003-06-30 | 2009-04-02 | 株式会社ルネサステクノロジ | 半導体装置およびその製造方法 |
JP4461476B2 (ja) * | 2003-08-25 | 2010-05-12 | Tdkラムダ株式会社 | 混成集積回路の製造方法 |
AU2003261857A1 (en) * | 2003-08-29 | 2005-03-29 | Renesas Technology Corp. | Semiconductor device manufacturing method |
US7208818B2 (en) * | 2004-07-20 | 2007-04-24 | Alpha And Omega Semiconductor Ltd. | Power semiconductor package |
WO2006044804A2 (en) * | 2004-10-18 | 2006-04-27 | Chippac, Inc. | Multi chip leadframe package |
CN101283449B (zh) * | 2005-07-01 | 2014-08-20 | 维税-希力康克斯公司 | 以单个贴装封装实现的完整功率管理系统 |
WO2007102042A1 (en) * | 2006-03-09 | 2007-09-13 | Infineon Technologies Ag | A multi-chip electronic package with reduced stress |
JP2006245618A (ja) | 2006-06-14 | 2006-09-14 | Fujitsu Ltd | 受動素子内蔵半導体装置 |
JP2008078445A (ja) * | 2006-09-22 | 2008-04-03 | Yamaha Corp | リードフレーム |
JP5157247B2 (ja) * | 2006-10-30 | 2013-03-06 | 三菱電機株式会社 | 電力半導体装置 |
JP2008140936A (ja) * | 2006-11-30 | 2008-06-19 | Toshiba Corp | プリント基板 |
MY154596A (en) * | 2007-07-25 | 2015-06-30 | Carsem M Sdn Bhd | Thin plastic leadless package with exposed metal die paddle |
JP5634033B2 (ja) * | 2008-08-29 | 2014-12-03 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 樹脂封止型半導体装置とその製造方法 |
US20100164078A1 (en) * | 2008-12-31 | 2010-07-01 | Ruben Madrid | Package assembly for semiconductor devices |
JP4947135B2 (ja) * | 2009-12-04 | 2012-06-06 | 株式会社デンソー | 半導体パッケージおよびその製造方法 |
JP2012008952A (ja) | 2010-06-28 | 2012-01-12 | Fuji Xerox Co Ltd | 情報処理装置、情報処理システム及びプログラム |
-
2012
- 2012-01-19 JP JP2012008952A patent/JP2013149779A/ja active Pending
-
2013
- 2013-01-16 CN CN201310014810.8A patent/CN103219313B/zh active Active
- 2013-01-16 CN CN201610075119.4A patent/CN105529314B/zh active Active
- 2013-01-18 DE DE202013012738.4U patent/DE202013012738U1/de not_active Expired - Lifetime
- 2013-01-18 EP EP13151939.9A patent/EP2618371B1/en active Active
- 2013-01-18 US US13/745,330 patent/US8759955B2/en active Active
-
2014
- 2014-05-30 US US14/291,159 patent/US20140264807A1/en not_active Abandoned
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5373188A (en) * | 1992-11-04 | 1994-12-13 | Mitsubishi Denki Kabushiki Kaisha | Packaged semiconductor device including multiple semiconductor chips and cross-over lead |
CN102201402A (zh) * | 2010-03-23 | 2011-09-28 | 三垦电气株式会社 | 半导体装置 |
Also Published As
Publication number | Publication date |
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CN105529314A (zh) | 2016-04-27 |
EP2618371A3 (en) | 2017-02-22 |
CN103219313B (zh) | 2016-01-06 |
US20130187261A1 (en) | 2013-07-25 |
EP2618371B1 (en) | 2018-12-12 |
JP2013149779A (ja) | 2013-08-01 |
US20140264807A1 (en) | 2014-09-18 |
EP2618371A2 (en) | 2013-07-24 |
US8759955B2 (en) | 2014-06-24 |
DE202013012738U1 (de) | 2019-01-08 |
CN103219313A (zh) | 2013-07-24 |
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