EP1267415A3 - Leistungshalbleiterbauelement mit RESURF-Schicht - Google Patents
Leistungshalbleiterbauelement mit RESURF-Schicht Download PDFInfo
- Publication number
- EP1267415A3 EP1267415A3 EP02012374A EP02012374A EP1267415A3 EP 1267415 A3 EP1267415 A3 EP 1267415A3 EP 02012374 A EP02012374 A EP 02012374A EP 02012374 A EP02012374 A EP 02012374A EP 1267415 A3 EP1267415 A3 EP 1267415A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- layer
- drift
- resurf
- drain
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/01—Manufacture or treatment
- H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
- H10D30/028—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs
- H10D30/0291—Manufacture or treatment of FETs having insulated gates [IGFET] of double-diffused metal oxide semiconductor [DMOS] FETs of vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/65—Lateral DMOS [LDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/109—Reduced surface field [RESURF] PN junction structures
- H10D62/111—Multiple RESURF structures, e.g. double RESURF or 3D-RESURF structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/13—Semiconductor regions connected to electrodes carrying current to be rectified, amplified or switched, e.g. source or drain regions
- H10D62/149—Source or drain regions of field-effect devices
- H10D62/151—Source or drain regions of field-effect devices of IGFETs
- H10D62/156—Drain regions of DMOS transistors
- H10D62/157—Impurity concentrations or distributions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26586—Bombardment with radiation with high-energy radiation producing ion implantation characterised by the angle between the ion beam and the crystal planes or the main crystal surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/65—Lateral DMOS [LDMOS] FETs
- H10D30/657—Lateral DMOS [LDMOS] FETs having substrates comprising insulating layers, e.g. SOI-LDMOS transistors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
- H10D62/103—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices
- H10D62/105—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE]
- H10D62/106—Constructional design considerations for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse-biased devices by having particular doping profiles, shapes or arrangements of PN junctions; by having supplementary regions, e.g. junction termination extension [JTE] having supplementary regions doped oppositely to or in rectifying contact with regions of the semiconductor bodies, e.g. guard rings with PN or Schottky junctions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/113—Isolations within a component, i.e. internal isolations
- H10D62/115—Dielectric isolations, e.g. air gaps
- H10D62/116—Dielectric isolations, e.g. air gaps adjoining the input or output regions of field-effect devices, e.g. adjoining source or drain regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/124—Shapes, relative sizes or dispositions of the regions of semiconductor bodies or of junctions between the regions
- H10D62/126—Top-view geometrical layouts of the regions or the junctions
- H10D62/127—Top-view geometrical layouts of the regions or the junctions of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
- H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
- H10D62/17—Semiconductor regions connected to electrodes not carrying current to be rectified, amplified or switched, e.g. channel regions
- H10D62/393—Body regions of DMOS transistors or IGBTs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
Applications Claiming Priority (6)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001175041 | 2001-06-11 | ||
JP2001175041A JP4728508B2 (ja) | 2001-06-11 | 2001-06-11 | 縦型電力用半導体素子の製造方法 |
JP2001276801 | 2001-09-12 | ||
JP2001276801A JP2003086800A (ja) | 2001-09-12 | 2001-09-12 | 半導体装置及びその製造方法 |
JP2001298311A JP2003101022A (ja) | 2001-09-27 | 2001-09-27 | 電力用半導体素子 |
JP2001298311 | 2001-09-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
EP1267415A2 EP1267415A2 (de) | 2002-12-18 |
EP1267415A3 true EP1267415A3 (de) | 2009-04-15 |
Family
ID=27346905
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP02012374A Withdrawn EP1267415A3 (de) | 2001-06-11 | 2002-06-06 | Leistungshalbleiterbauelement mit RESURF-Schicht |
Country Status (4)
Country | Link |
---|---|
US (2) | US6693338B2 (de) |
EP (1) | EP1267415A3 (de) |
KR (1) | KR100491989B1 (de) |
CN (1) | CN1329999C (de) |
Families Citing this family (154)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6344213B1 (en) * | 1996-03-29 | 2002-02-05 | Emisphere Technologies, Inc. | Compounds and compositions for delivering active agents |
US6995426B2 (en) * | 2001-12-27 | 2006-02-07 | Kabushiki Kaisha Toshiba | Semiconductor device having vertical metal insulator semiconductor transistors having plural spatially overlapping regions of different conductivity type |
JP3908572B2 (ja) | 2002-03-18 | 2007-04-25 | 株式会社東芝 | 半導体素子 |
US6686244B2 (en) * | 2002-03-21 | 2004-02-03 | General Semiconductor, Inc. | Power semiconductor device having a voltage sustaining region that includes doped columns formed with a single ion implantation step |
GB0214618D0 (en) * | 2002-06-25 | 2002-08-07 | Koninkl Philips Electronics Nv | Semiconductor device with edge structure |
KR100473476B1 (ko) * | 2002-07-04 | 2005-03-10 | 삼성전자주식회사 | 반도체 장치 및 그 제조방법 |
US8080459B2 (en) * | 2002-09-24 | 2011-12-20 | Vishay-Siliconix | Self aligned contact in a semiconductor device and method of fabricating the same |
JP3634830B2 (ja) * | 2002-09-25 | 2005-03-30 | 株式会社東芝 | 電力用半導体素子 |
DE10354249A1 (de) * | 2002-11-22 | 2004-06-03 | Fuji Electric Device Technology Co. Ltd. | Halbleitervorrichtung und Verfahren zu deren Herstellung |
JP3634848B2 (ja) * | 2003-01-07 | 2005-03-30 | 株式会社東芝 | 電力用半導体素子 |
JP2004335990A (ja) * | 2003-03-10 | 2004-11-25 | Fuji Electric Device Technology Co Ltd | Mis型半導体装置 |
JP4292964B2 (ja) | 2003-08-08 | 2009-07-08 | 三菱電機株式会社 | 縦型半導体装置 |
DE112004001163B4 (de) * | 2003-08-20 | 2017-12-28 | Denso Corporation | Halbleiteranordnung eines vertikalen Typs |
JP4253558B2 (ja) * | 2003-10-10 | 2009-04-15 | 株式会社豊田中央研究所 | 半導体装置 |
EP1701686A4 (de) * | 2003-12-19 | 2009-07-01 | Third Dimension 3D Sc Inc | Verfahren zur herstellung einer superverbindungsvorrichtung mit herkömmlichen enden |
KR20070029655A (ko) * | 2003-12-19 | 2007-03-14 | 써드 디멘존 세미컨덕터, 인코포레이티드 | 넓은 메사를 갖는 수퍼 접합 장치의 제조 방법 |
JP4699692B2 (ja) * | 2003-12-26 | 2011-06-15 | ローム株式会社 | 半導体装置の製造方法および半導体装置 |
US7126166B2 (en) * | 2004-03-11 | 2006-10-24 | Semiconductor Components Industries, L.L.C. | High voltage lateral FET structure with improved on resistance performance |
JP4865194B2 (ja) | 2004-03-29 | 2012-02-01 | ルネサスエレクトロニクス株式会社 | 超接合半導体素子 |
DE102004015921B4 (de) * | 2004-03-31 | 2006-06-14 | Infineon Technologies Ag | Rückwärts sperrendes Halbleiterbauelement mit Ladungskompensation |
DE102004029435B4 (de) * | 2004-06-18 | 2017-02-16 | Infineon Technologies Ag | Feldplattentrenchtransistor |
JP3875245B2 (ja) | 2004-07-26 | 2007-01-31 | 株式会社東芝 | 半導体装置 |
JP2006140372A (ja) * | 2004-11-15 | 2006-06-01 | Sanyo Electric Co Ltd | 半導体装置およびその製造方法 |
JP4940546B2 (ja) * | 2004-12-13 | 2012-05-30 | 株式会社デンソー | 半導体装置 |
JP4768259B2 (ja) * | 2004-12-21 | 2011-09-07 | 株式会社東芝 | 電力用半導体装置 |
US7598586B2 (en) * | 2004-12-24 | 2009-10-06 | Rohm Co., Ltd. | Semiconductor device and production method therefor |
JP2006186145A (ja) | 2004-12-28 | 2006-07-13 | Toshiba Corp | 半導体装置及びその製造方法 |
JP4825424B2 (ja) * | 2005-01-18 | 2011-11-30 | 株式会社東芝 | 電力用半導体装置 |
US7176524B2 (en) * | 2005-02-15 | 2007-02-13 | Semiconductor Components Industries, Llc | Semiconductor device having deep trench charge compensation regions and method |
US7482220B2 (en) | 2005-02-15 | 2009-01-27 | Semiconductor Components Industries, L.L.C. | Semiconductor device having deep trench charge compensation regions and method |
DE102005009000B4 (de) | 2005-02-28 | 2009-04-02 | Infineon Technologies Austria Ag | Vertikales Halbleiterbauelement vom Grabenstrukturtyp und Herstellungsverfahren |
US9685524B2 (en) | 2005-03-11 | 2017-06-20 | Vishay-Siliconix | Narrow semiconductor trench structure |
JP2006269720A (ja) * | 2005-03-24 | 2006-10-05 | Toshiba Corp | 半導体素子及びその製造方法 |
JP2006278826A (ja) * | 2005-03-30 | 2006-10-12 | Toshiba Corp | 半導体素子及びその製造方法 |
US7541643B2 (en) * | 2005-04-07 | 2009-06-02 | Kabushiki Kaisha Toshiba | Semiconductor device |
EP1872396A4 (de) * | 2005-04-22 | 2009-09-23 | Icemos Technology Corp | Superübergangsbauelement mit oxidausgekleideten gräben und verfahren zur herstellung eines superübergangsbauelements mit oxidausgekleideten gräben |
US20060255401A1 (en) * | 2005-05-11 | 2006-11-16 | Yang Robert K | Increasing breakdown voltage in semiconductor devices with vertical series capacitive structures |
JP4843253B2 (ja) * | 2005-05-23 | 2011-12-21 | 株式会社東芝 | 電力用半導体装置 |
US7462909B2 (en) * | 2005-06-20 | 2008-12-09 | Kabushiki Kaisha Toshiba | Semiconductor device and method of fabricating the same |
JP2007012858A (ja) * | 2005-06-30 | 2007-01-18 | Toshiba Corp | 半導体素子及びその製造方法 |
US20070012983A1 (en) * | 2005-07-15 | 2007-01-18 | Yang Robert K | Terminations for semiconductor devices with floating vertical series capacitive structures |
JP5002148B2 (ja) * | 2005-11-24 | 2012-08-15 | 株式会社東芝 | 半導体装置 |
JP4996848B2 (ja) * | 2005-11-30 | 2012-08-08 | 株式会社東芝 | 半導体装置 |
TWI489557B (zh) * | 2005-12-22 | 2015-06-21 | Vishay Siliconix | 高移動率p-通道溝槽及平面型空乏模式的功率型金屬氧化物半導體場效電晶體 |
JP4989085B2 (ja) * | 2006-02-24 | 2012-08-01 | オンセミコンダクター・トレーディング・リミテッド | 半導体装置及びその製造方法 |
JP5307973B2 (ja) * | 2006-02-24 | 2013-10-02 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 半導体装置 |
US8409954B2 (en) * | 2006-03-21 | 2013-04-02 | Vishay-Silconix | Ultra-low drain-source resistance power MOSFET |
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JP2007281034A (ja) * | 2006-04-03 | 2007-10-25 | Toshiba Corp | 電力用半導体素子 |
WO2007122646A1 (en) * | 2006-04-21 | 2007-11-01 | Stmicroelectronics S.R.L. | Process for manufacturing a power semiconductor device and corresponding power semiconductor device |
DE102006025218B4 (de) | 2006-05-29 | 2009-02-19 | Infineon Technologies Austria Ag | Leistungshalbleiterbauelement mit Ladungskompensationsstruktur und Verfahren zur Herstellung desselben |
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US7799640B2 (en) * | 2006-09-28 | 2010-09-21 | Semiconductor Components Industries, Llc | Method of forming a semiconductor device having trench charge compensation regions |
JP5128100B2 (ja) * | 2006-09-29 | 2013-01-23 | 三菱電機株式会社 | 電力用半導体装置 |
JP2008091450A (ja) * | 2006-09-29 | 2008-04-17 | Toshiba Corp | 半導体素子 |
JP5196766B2 (ja) * | 2006-11-20 | 2013-05-15 | 株式会社東芝 | 半導体装置 |
EP2089907A4 (de) * | 2006-12-07 | 2011-05-25 | Shindengen Electric Mfg | Halbleiterbauelement und herstellungsverfahren dafür |
US9437729B2 (en) | 2007-01-08 | 2016-09-06 | Vishay-Siliconix | High-density power MOSFET with planarized metalization |
JP2008182054A (ja) * | 2007-01-25 | 2008-08-07 | Toshiba Corp | 半導体装置 |
DE102007004320A1 (de) * | 2007-01-29 | 2008-07-31 | Infineon Technologies Ag | Halbleiterbauelement mit vertikalen Strukturen von hohem Aspektverhältnis und Verfahren zur Herstellung einer kapazitiven Struktur in einem Halbleiterkörper |
US9947770B2 (en) | 2007-04-03 | 2018-04-17 | Vishay-Siliconix | Self-aligned trench MOSFET and method of manufacture |
JP4564509B2 (ja) * | 2007-04-05 | 2010-10-20 | 株式会社東芝 | 電力用半導体素子 |
JP4564510B2 (ja) * | 2007-04-05 | 2010-10-20 | 株式会社東芝 | 電力用半導体素子 |
US8581345B2 (en) * | 2007-06-05 | 2013-11-12 | Stmicroelectronics S.R.L. | Charge-balance power device comprising columnar structures and having reduced resistance, and method and system of same |
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Also Published As
Publication number | Publication date |
---|---|
EP1267415A2 (de) | 2002-12-18 |
CN1405897A (zh) | 2003-03-26 |
KR100491989B1 (ko) | 2005-05-30 |
US6693338B2 (en) | 2004-02-17 |
KR20020095110A (ko) | 2002-12-20 |
CN1329999C (zh) | 2007-08-01 |
US6919610B2 (en) | 2005-07-19 |
US20020185705A1 (en) | 2002-12-12 |
US20040094819A1 (en) | 2004-05-20 |
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