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CN107968272A - 端子 - Google Patents

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Publication number
CN107968272A
CN107968272A CN201710984491.1A CN201710984491A CN107968272A CN 107968272 A CN107968272 A CN 107968272A CN 201710984491 A CN201710984491 A CN 201710984491A CN 107968272 A CN107968272 A CN 107968272A
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CN
China
Prior art keywords
arm
abutted position
elastic arm
terminal
chip module
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
CN201710984491.1A
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English (en)
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CN107968272B (zh
Inventor
黄常伟
朱德祥
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Lotes Guangzhou Co Ltd
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Lotes Guangzhou Co Ltd
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Publication of CN107968272A publication Critical patent/CN107968272A/zh
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Publication of CN107968272B publication Critical patent/CN107968272B/zh
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01R—ELECTRICALLY-CONDUCTIVE CONNECTIONS; STRUCTURAL ASSOCIATIONS OF A PLURALITY OF MUTUALLY-INSULATED ELECTRICAL CONNECTING ELEMENTS; COUPLING DEVICES; CURRENT COLLECTORS
    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
    • H01R12/70—Coupling devices
    • H01R12/71—Coupling devices for rigid printing circuits or like structures
    • H01R12/712—Coupling devices for rigid printing circuits or like structures co-operating with the surface of the printed circuit or with a coupling device exclusively provided on the surface of the printed circuit
    • H01R12/716—Coupling device provided on the PCB
    • H01R12/718—Contact members provided on the PCB without an insulating housing
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    • H01R12/00—Structural associations of a plurality of mutually-insulated electrical connecting elements, specially adapted for printed circuits, e.g. printed circuit boards [PCB], flat or ribbon cables, or like generally planar structures, e.g. terminal strips, terminal blocks; Coupling devices specially adapted for printed circuits, flat or ribbon cables, or like generally planar structures; Terminals specially adapted for contact with, or insertion into, printed circuits, flat or ribbon cables, or like generally planar structures
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  • Details Of Connecting Devices For Male And Female Coupling (AREA)

Abstract

本发明公开了一种端子，用以电性连接一芯片模块至一电路板，包括：一连接部；一上弹性臂自连接部一端向前延伸形成，用于向上抵接芯片模块；一下弹性臂自连接部相对另一端向前延伸形成，用于向下导接电路板；当芯片模块下压上弹性臂时，使得上弹性臂抵接下弹性臂从而形成一第一抵接位置和一第二抵接位置，且第一抵接位置与第二抵接位置沿前后方向间隔排列。首先，端子通过形成第一抵接位置和第二抵接位置，可在芯片模块与电路板之间形成三条并联导电路径，减小了芯片模块与电路板间电讯传输时的电阻抗。其次，第一抵接位置和第二抵接位置沿前后方向间隔排列，减小了端子的体积，可有效降低第一抵接位置和第二抵接位置之间的信号干扰。

Description

端子
技术领域
本发明涉及一种端子，尤其是指一种电性连接芯片模块至电路板的端子。
背景技术
导电端子被广泛地应用于各种电子设备的电连接器中，用以电性连接芯片模块和印刷电路板。所述导电端子包括基部、以及自基部上下两端分别倾斜延伸的一对弹性臂，当所述芯片模块压缩所述导电端子时，所述导电端子的一对所述弹性臂开始自初始状态开始倾斜，以在芯片模块和印刷电路板之间提供信号传输路径。
然而，该种导电端子至少存在以下缺点：该导电端子的电性导通路径是这样实现的：芯片模块通过与导电端子弹性臂自由末端的接触点接触，从而将电性传到导电端子上，导电端子再将电性经由与芯片模块接触的弹性臂、基部、与印刷电路板接触的另一个弹性臂而将电性传至印刷电路板，故，该种导电端子的电性传输路径较远，使得芯片模块与印刷电路板间电讯传输时仍存在较强的电阻抗。
因此，有必要设计一种新的导电端子，以克服上述问题。
发明内容
本发明的创作目的在于提供一种稳定形成三条并联导电路径，以减小芯片模块与电路板间电讯传输时的电阻抗的端子。
为了达到上述目的，本发明采用如下技术方案：
一种端子，用以电性连接一芯片模块至一电路板，其特征在于，包括：一连接部；一上弹性臂自所述连接部一端向前延伸形成，用于向上抵接所述芯片模块；一下弹性臂自所述连接部相对另一端向前延伸形成，用于向下导接所述电路板；当所述芯片模块下压所述上弹性臂时，使得所述上弹性臂抵接所述下弹性臂从而形成一第一抵接位置和一第二抵接位置，且所述第一抵接位置与所述第二抵接位置沿前后方向间隔排列。
进一步，所述第一抵接位置和所述第二抵接位置沿上下方向间隔排列。
进一步，所述上弹性臂具有一上接触部用于向上抵接所述芯片模块，所述第一抵接位置和所述第二抵接位置沿前后方向位于所述上接触部的相对两侧。
进一步，所述上弹性臂包括一第一臂，及自第一臂中部朝所述下弹性臂撕裂形成的一第二臂，当所述芯片模块下压所述第一臂时，使得所述第一臂抵接所述下弹性臂从而形成所述第一抵接位置，所述第二臂抵接所述下弹性臂从而形成所述第二抵接位置。
进一步，所述第二抵接位置相对于所述第一抵接位置更靠近所述连接部。
进一步，所述第一臂与所述下弹性臂的抵接方式和所述第二臂与所述下弹性臂的抵接方式不同。
进一步，所述下弹性臂包括一第三臂，及自第三臂中部朝所述上弹性臂撕裂形成的一第四臂，当所述芯片模块下压所述上弹性臂时，使得所述第三臂抵接所述上弹性臂从而形成所述第一抵接位置，所述第四臂抵接所述上弹性臂从而形成所述第二抵接位置。
进一步，所述第二抵接位置相对于所述第一抵接位置更靠近所述连接部。
进一步，所述第三臂与所述上弹性臂的抵接方式和所述第四臂与所述上弹性臂的抵接方式不同。
进一步，所述上弹性臂包括一第一臂，及自第一臂朝所述下弹性臂撕裂形成的一第二臂，所述下弹性臂包括一第三臂，及自第三臂朝所述上弹性臂撕裂形成的一第四臂，当所述芯片模块下压所述第一臂时，使得所述第一臂抵接所述第三臂从而形成所述第一抵接位置，所述第二臂抵接所述第四臂从而形成所述第二抵接位置。
进一步，所述第二臂的末端设有一第一斜面，所述第四臂的末端设有一第二斜面，当所述芯片模块下压所述第一臂时，使得所述第一斜面的侧缘抵接所述第二斜面的侧缘从而形成所述第二抵接位置。
进一步，所述第二臂的末端设有一第一缺口，所述第四臂的末端设有一第二缺口，当所述芯片模块下压所述第一臂时，使得所述第一缺口的侧缘抵接所述第二缺口的侧缘从而形成所述第二抵接位置。
与现有技术相比，本发明端子具有以下有益效果：
当所述芯片模块下压所述上弹性臂时，使得所述上弹性臂抵接所述下弹性臂从而形成一第一抵接位置和一第二抵接位置，从而在芯片模块与电路板之间形成依次经由芯片模块、上弹性臂、连接部、下弹性臂、电路板；以及依次经由芯片模块、上弹性臂、第一抵接位置、下弹性臂、电路板；以及依次芯片模块、上弹性臂、第二抵接位置、下弹性臂、电路板的三条相互并联的导电路径，减小了所述芯片模块与电路板间电讯传输时的电阻抗；并且所述第一抵接位置与所述第二抵接位置沿前后方向间隔排列，不仅减小了所述端子的体积，而且可有效降低所述第一抵接位置和第二抵接位置之间的信号干扰，增强所述端子的信号传输品质，使得所述端子能够适应更高速率信号的传输。
【附图说明】
图1为本发明第一实施例端子在芯片模块下压前的立体图；
图2为图1中的端子在芯片模块下压后的立体图；
图3为图2的侧视图；
图4为本发明第二实施例端子在芯片模块下压前的立体图；
图5为图4中的端子在芯片模块下压后的立体图；
图6为图5的侧视图；
图7为本发明第三实施例端子在芯片模块下压前的立体图；
图8为图7中的端子在芯片模块下压后的立体图；
图9为本发明第四实施例端子在芯片模块下压后的立体图。
具体实施方式的附图标号说明：
端子1 连接部11 上弹性臂12 第一臂121
上延伸部1211 上接触部1212 上抵接部1213 第二臂122
第一斜面1221 第一缺口1222 下弹性臂13 第三臂131
下延伸部1311 下接触部1312 下抵接部1313 第四臂132
第二斜面1321 第二缺口1322 第一抵接位置P1 第二抵接位置P2
芯片模块2 电路板3
【具体实施方式】
为便于更好的理解本发明的目的、结构、特征以及功效等，现结合附图和具体实施方式对本发明作进一步说明。
如图1至图3所示，为本发明第一实施例的端子1，用以电性连接一芯片模块2至一电路板3，其包括一连接部11，一上弹性臂12及一下弹性臂13。
如图1和图3所示，所述连接部11呈圆弧状。所述上弹性臂12自所述连接部11顶端向前弯折延伸形成，用于向上抵接所述芯片模块2。所述下弹性臂13自所述连接部11底端向前弯折延伸形成，用于向下导接所述电路板3。
沿其延伸方向，所述连接部11、所述上弹性臂12和所述下弹性臂13的宽度相等。
所述上弹性臂12包括一第一臂121和一第二臂122。
所述第一臂121包括一上延伸部1211自所述连接部11朝前上方倾斜延伸形成、一上接触部1212自所述上延伸部1211朝前上方弯折延伸形成、及一上抵接部1213自所述上接触部1212朝前下方倾斜延伸形成。
所述上接触部1212呈圆弧状且用于向上抵接所述芯片模块2，所述上抵接部1213与所述上接触部1212相切。
所述第二臂122自所述上延伸部1211中间朝所述下弹性臂13撕裂形成（在其它实施例中，所述第二臂122也可自所述上延伸部1211一侧朝所述下弹性臂13撕裂形成），所述第二臂122与所述上接触部1212相切，且沿其延伸方向，所述第二臂122的宽度相等。
所述上抵接部1213和所述第二臂122之间的距离沿其延伸方向逐渐增大。
所述下弹性臂13包括一第三臂131和一第四臂132。
所述第三臂131包括一下延伸部1311自所述连接部11朝前下方倾斜延伸形成、一下接触部1312自所述下延伸部1311朝前下方弯折延伸形成、及一下抵接部1313自所述下接触部1312朝前上方倾斜延伸形成。
所述下接触部1312呈圆弧状且用于向下导接所述电路板3，所述下抵接部1313与所述下接触部1312相切，所述下抵接部1313的顶端用于连接一料带（未图示）。
所述第四臂132自所述下延伸部1311中间朝所述上弹性臂12撕裂形成（在其它实施例中，所述第四臂132也可自所述下延伸部1311一侧朝所述上弹性臂12撕裂形成），所述第四臂132与所述下接触部1312相切，且沿其延伸方向，所述第四臂132的宽度相等。
所述下抵接部1313和所述第四臂132之间的距离沿其延伸方向逐渐增大。
所述下抵接部1313末端和所述第四臂132末端之间的距离大于所述上抵接部1213末端和所述第二臂122末端之间的距离。
如图2和图3所示，当所述芯片模块2下压所述第一臂121时，使得所述第一臂121抵接所述第三臂131从而形成一第一抵接位置P1，所述第二臂122抵接所述第四臂132从而形成一第二抵接位置P2，且所述第一臂121与所述第三臂131的抵接方式和所述第二臂122与所述第四臂132的抵接方式不同。
在本实施例中，所述上抵接部1213的前表面抵接所述下抵接部1313的后表面从而形成所述第一抵接位置P1，所述第二臂122的末端后边缘抵接所述第四臂132的前表面从而形成所述第二抵接位置P2，从而在芯片模块2与电路板3之间形成依次经由芯片模块2、上接触部1212、上延伸部1211、连接部11、下延伸部1311、下接触部1312、电路板3；以及依次经由芯片模块2、上接触部1212、上抵接部1213、第一抵接位置P1、下抵接部1313、下接触部1312、电路板3；以及依次芯片模块2、上接触部1212、第二臂122、第二抵接位置P2、第四臂132、下接触部1312、电路板3的三条相互并联的导电路径，减小了所述芯片模块2与电路板3间电讯传输时的电阻抗。
所述第一抵接位置P1与所述第二抵接位置P2沿前后方向间隔排列，所述第一抵接位置P1和所述第二抵接位置P2沿前后方向位于所述上接触部1212和下接触部1312的相对两侧，所述第二抵接位置P2相对于所述第一抵接位置P1更靠近所述连接部11。
所述第一抵接位置P1和所述第二抵接位置P2沿上下方向间隔排列。
在其它实施例中，所述端子1也可仅设有所述第二臂122而不设有第四臂132，且适当延长所述第二臂122的长度，使得当所述芯片模块2下压所述第一臂121时，所述第二臂122的末端抵接所述下延伸部1311的上表面从而形成所述第二抵接位置P2；或者所述端子1也可仅设有所述第四臂132而不设有第二臂122，且适当延长所述第四臂132的长度，使得当所述芯片模块2下压所述第一臂121时，所述第四臂132的末端抵接所述上延伸部1211的下表面从而形成所述第二抵接位置P2。
如图4至图6所示，为本发明第二实施例的端子1，其与第一实施例的不同之处主要在于，本实施例中：
所述第二臂122的末端设有一第一斜面1221，所述第四臂132的末端设有一第二斜面1321，当所述芯片模块2下压所述第一臂121时，使得所述第一斜面1221的侧缘抵接所述第二斜面1321的侧缘从而形成所述第二抵接位置P2，通过所述第一斜面1221和所述第二斜面1321的导向作用，有利于所述芯片模块2下压所述端子1，保证了所述第二臂122与所述第四臂132之间的稳定抵接。
如图7至图8所示，为本发明第三实施例的端子1，其与第一实施例的不同之处主要在于，本实施例中：
所述第二臂122的末端设有一第一缺口1222，所述第四臂132的末端设有一第二缺口1322，当所述芯片模块2下压所述第一臂121时，使得所述第一缺口1222的侧缘抵接所述第二缺口1322的侧缘从而形成所述第二抵接位置P2，可以刮擦去除形成在所述第一缺口1222的侧缘和所述第二缺口1322的侧缘的氧化层，增强了所述第二臂122与所述第四臂132之间的抵接效果。
如图9所示，为本发明第四实施例的端子1，其与第三实施例的不同之处主要在于，本实施例中：
所述第一缺口1222自所述第二臂122末端的中部凹设形成，所述第二缺口1322有两个且自所述第四臂132末端相对的两板缘分别凹设形成，当所述芯片模块2下压所述第一臂121时，使得所述第一缺口1222相对的两侧缘抵接两所述第二缺口1322的侧缘从而形成所述第二抵接位置P2，起限位作用，增强了所述第一缺口1222和所述第二缺口1322的配合，保证了所述第一缺口1222与所述第二缺口1322之间的稳定抵接。
综上所述，本发明端子有下列有益效果：
（1）当所述芯片模块2下压所述上弹性臂12时，使得所述上弹性臂12抵接所述下弹性臂13从而形成一第一抵接位置P1和一第二抵接位置P2，从而在芯片模块2与电路板3之间形成依次经由芯片模块2、上弹性臂12、连接部11、下弹性臂13、电路板3；以及依次经由芯片模块2、上弹性臂12、第一抵接位置P1、下弹性臂13、电路板3；以及依次芯片模块2、上弹性臂12、第二抵接位置P2、下弹性臂13、电路板3的三条相互并联的导电路径，减小了所述芯片模块2与电路板3间电讯传输时的电阻抗；并且所述第一抵接位置P1与所述第二抵接位置P2沿前后方向间隔排列，不仅减小了所述端子1的体积，而且可有效降低所述第一抵接位置P1和第二抵接位置P2之间的信号干扰，增强所述端子1的信号传输品质，使得所述端子1能够适应更高速率信号的传输。
（2）所述第一抵接位置P1和所述第二抵接位置P2沿上下方向间隔排列，可进一步降低所述第一抵接位置P1和第二抵接位置P2之间的信号干扰。
（3）所述第一抵接位置P1和所述第二抵接位置P2沿前后方向位于所述上接触部1212的相对两侧，可以均分所述芯片模块2下压所述端子1的压力，避免了由于所述端子1受力不均而不能与所述芯片模块2之间形成稳定的抵接。
（4）所述第二臂122自所述第一臂121撕裂形成，所述第四臂132自所述第三臂131撕裂形成，可以在不改变原先所述端子1整体体积的前提下，增加了所述第二臂122和所述第四臂132，节省了所述端子1的材料，当所述芯片模块2下压所述端子1时，使得所述第二臂122抵接所述第四臂132从而形成所述第二抵接位置P2，增加了依次芯片模块2、上接触部1212、第二臂122、第二抵接位置P2、第四臂132、下接触部1312、电路板3的第三条导电路径，减小了所述芯片模块2与电路板3间电讯传输时的电阻抗。
以上详细说明仅为本发明之较佳实施例的说明，非因此局限本发明之专利范围，所以，凡运用本创作说明书及图示内容所为之等效技术变化，均包含于本创作之专利范围内。

Claims (12)

1.一种端子，用以电性连接一芯片模块至一电路板，其特征在于，包括：
一连接部；
一上弹性臂自所述连接部一端向前延伸形成，用于向上抵接所述芯片模块；
一下弹性臂自所述连接部相对另一端向前延伸形成，用于向下导接所述电路板；
当所述芯片模块下压所述上弹性臂时，使得所述上弹性臂抵接所述下弹性臂从而形成一第一抵接位置和一第二抵接位置，且所述第一抵接位置与所述第二抵接位置沿前后方向间隔排列。
2.如权利要求1所述的端子，其特征在于：所述第一抵接位置和所述第二抵接位置沿上下方向间隔排列。
3.如权利要求1所述的端子，其特征在于：所述上弹性臂具有一上接触部用于向上抵接所述芯片模块，所述第一抵接位置和所述第二抵接位置沿前后方向位于所述上接触部的相对两侧。
4.如权利要求1所述的端子，其特征在于：所述上弹性臂包括一第一臂，及自第一臂中部朝所述下弹性臂撕裂形成的一第二臂，当所述芯片模块下压所述第一臂时，使得所述第一臂抵接所述下弹性臂从而形成所述第一抵接位置，所述第二臂抵接所述下弹性臂从而形成所述第二抵接位置。
5.如权利要求4所述的端子，其特征在于：所述第二抵接位置相对于所述第一抵接位置更靠近所述连接部。
6.如权利要求4所述的端子，其特征在于：所述第一臂与所述下弹性臂的抵接方式和所述第二臂与所述下弹性臂的抵接方式不同。
7.如权利要求1所述的端子，其特征在于：所述下弹性臂包括一第三臂，及自第三臂中部朝所述上弹性臂撕裂形成的一第四臂，当所述芯片模块下压所述上弹性臂时，使得所述第三臂抵接所述上弹性臂从而形成所述第一抵接位置，所述第四臂抵接所述上弹性臂从而形成所述第二抵接位置。
8.如权利要求7所述的端子，其特征在于：所述第二抵接位置相对于所述第一抵接位置更靠近所述连接部。
9.如权利要求7所述的端子，其特征在于：所述第三臂与所述上弹性臂的抵接方式和所述第四臂与所述上弹性臂的抵接方式不同。
10.如权利要求1所述的端子，其特征在于：所述上弹性臂包括一第一臂，及自第一臂朝所述下弹性臂撕裂形成的一第二臂，所述下弹性臂包括一第三臂，及自第三臂朝所述上弹性臂撕裂形成的一第四臂，当所述芯片模块下压所述第一臂时，使得所述第一臂抵接所述第三臂从而形成所述第一抵接位置，所述第二臂抵接所述第四臂从而形成所述第二抵接位置。
11.如权利要求10所述的端子，其特征在于：所述第二臂的末端设有一第一斜面，所述第四臂的末端设有一第二斜面，当所述芯片模块下压所述第一臂时，使得所述第一斜面的侧缘抵接所述第二斜面的侧缘从而形成所述第二抵接位置。
12.如权利要求10所述的端子，其特征在于：所述第二臂的末端设有一第一缺口，所述第四臂的末端设有一第二缺口，当所述芯片模块下压所述第一臂时，使得所述第一缺口的侧缘抵接所述第二缺口的侧缘从而形成所述第二抵接位置。
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CN108092023B (zh) 2020-08-28
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US10199756B2 (en) 2019-02-05
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CN107492728A (zh) 2017-12-19
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