CN102970013A - Resetting method and resetting control device of register inside chip based on scanning chain - Google Patents
Resetting method and resetting control device of register inside chip based on scanning chain Download PDFInfo
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Abstract
本发明公开了一种基于扫描链的芯片内部寄存器复位方法及复位控制装置，复位方法包括：1）在芯片设计阶段将寄存器根据复位值为0或1分别构建至少一条扫描链；2）在芯片使用阶段将各个寄存器的扫描使能信号置为有效并将复位值写入扫描链链头；复位控制装置包括扫描链使能控制单元、扫描链时钟控制模块和分别向扫描链链头输出测试数据或复位值的输入数据选择器，复位控制装置的输入端口包括测试使能端、复位信号输入端、测试扫描使能信号/工作时钟/复位时钟/测试时钟输入端及多个测试数据输入端。本发明能够高效实现芯片内部寄存器的复位，对数字集成电路芯片性能影响低，具有稳定性高、功耗开销小，结构简单、实现方便的优点。
The invention discloses a chip internal register reset method and a reset control device based on scan chains. The reset method includes: 1) constructing at least one scan chain at the register according to the reset value of 0 or 1 in the chip design stage; 2) in the chip In the use stage, the scan enable signal of each register is made valid and the reset value is written into the scan chain head; the reset control device includes a scan chain enable control unit, a scan chain clock control module and output test data to the scan chain head respectively Or the input data selector of the reset value, the input port of the reset control device includes a test enable terminal, a reset signal input terminal, a test scan enable signal/working clock/reset clock/test clock input terminal and a plurality of test data input terminals. The invention can efficiently realize the reset of the internal register of the chip, has little influence on the performance of the digital integrated circuit chip, has the advantages of high stability, low power consumption, simple structure and convenient realization.
Description
Technical field
The present invention relates to the digital integrated circuit field, be specifically related to a kind of chip internal register repositioning method and repositioning control device based on scan chain.
Background technology
In digital integrated circuit, need to register be resetted by certain method, so that it has a definite initial condition (0 or 1), thereby guarantee that digital integrated circuit can work.Register repositioning method commonly used in the prior art comprises synchronous reset and asynchronous reset.
When synchronous reset, when reset signal was effective, register did not reset immediately, but when effective saltus step occurs the clock of register, just register was reset to fixing initial value.In the synchronous reset structure, reset signal is used as data-signal, participates in the combinational logic operation of register data input, and this has increased the combinational logic progression between the register, and the performance of chip is had certain impact; When asynchronous reset, when reset signal is effective, whether no matter effective clock saltus step arranged, register will be reset to fixing initial value at once.Asynchronous reset register is the independent input of reset signal as register, so reset signal do not participate in the combinational logic operation of register data input as data-signal, but the circuit stability of asynchronous reset structure is not as the synchronous reset circuit.When normal operation, any burr in the asynchronous reset circuit on the reset signal all will cause register to be resetted mistakenly, unless and the burr on the reset signal occurs in effective hopping edge of clock just in the synchronous reset circuit, otherwise can not cause register to be resetted mistakenly.But synchronous reset and asynchronous reset all need the reseting signal line of an overall situation.In the situation that the digital integrated circuit scale constantly enlarges, no matter be synchronous reset or asynchronous reset, all face the wiring problem of overall signal's line.Along with improving constantly of integrated circuit technology, the scale of digital integrated circuit constantly enlarges, and register number integrated in the one single chip is more and more.No matter be to adopt synchronous reset or asynchronous reset, all need to give the register that each need to reset with global reset signal that this will cause the load of global reset signal line very large.And register spreads all over each corner of chip, and reset signal need to be walked very long path could arrive register, and this causes very large holding wire to postpone.General way is to adopt the tree structure that resets at present, by multi-buffer, single global reset signal is done tree-like scattering, and guarantees that the holding wire from root node to all leaf nodes postpones identical.This has not only expended a large amount of hardware resources, has brought certain tree power consumption expense that resets, and along with the continuous expansion of digital integrated circuit scale, the tree that resets will constantly promote chip physical Design complexity, and the design of chip is realized causing great difficulty.
In sum, the synchronous reset method of the digital integrated circuit of prior art has certain impact to the performance of digital integrated circuit chip, but and the asynchronous reset method of the digital integrated circuit of prior art has potential stability problem.And, no matter be synchronous reset structure or asynchronous reset structure, all need to design the tree structure that resets of realizing the overall situation, not only bring extra power consumption expense, also physics realization brings great difficulty to chip.Therefore, along with the continuous increase with integrated level of improving constantly of integrated circuit technology, the variety of problems when being badly in need of technical scheme that a kind of effective digital integrated circuit register resets and solving present general synchronous and asynchronous repositioning method and realize that register resets.
Summary of the invention
The technical problem to be solved in the present invention provide a kind of low to the digital integrated circuit chip performance impact, stability is high, the power consumption expense is little, simple in structure, realize easily chip internal register repositioning method and repositioning control device based on scan chain.
In order to solve the problems of the technologies described above, the technical solution used in the present invention is:
A kind of chip internal register repositioning method based on scan chain, implementation step is as follows:
1) in chip design stage, at chip internal needs are reset to 0 register and make up at least one scan chain, needs are reset to 1 register make up at least one scan chain, and the scanning output end of previous register links to each other with the scan input end of a rear register in the same scan chain;
2) in the chip operational phase, the scan enable signals of each register of chip internal is set to effectively, be reset to the scan chain begin chain input reset values 0 that 0 register forms at needs, be reset to the scan chain begin chain input reset values 1 that 1 register forms at needs, and provide reset clock, control each scan chain and enter the scanning mode that resets, under the control of input reset clock, reset values write successively each register in the scan chain, after scanning last-of-chain register is written into reset values, it is invalid that scan enable signals is set to, withdraw from the scanning mode that resets, finish chip reset.
A kind of chip internal register repositioning control device based on scan chain, it is characterized in that: comprise that scan chain enables control unit, scan chain clock control module and outputing test data or the input data selector of reset values to the scan chain begin chain respectively, the input port of described repositioning control device comprises the test enable end, the reset signal input, test scan enable signal input, the work clock input, the reset clock input, test clock input and a plurality of test data input, described scan chain enables control unit by state controller and is used for selecting the enable signal selector of output scanning chain enable signal to form, described state controller links to each other with the reset signal input, and according to the value of reseting input signal control reset mode, an input of described enable signal selector links to each other with state controller, and another input of described scan chain enable signal selector links to each other with test scan enable signal input; Described scan chain clock control module forms by the one-level clock selector of cascade with for the secondary clock selector to integrated circuit output clock signal, the input of described one-level clock selector links to each other with work clock input, reset clock input respectively, the control end of described one-level clock selector links to each other with the output of state controller, an input of described secondary clock selector links to each other with the test clock input, and another input of described secondary clock selector links to each other with the output of one-level clock selector; Described input data selector is corresponding one by one with the test data input, and an input of described input data selector is continuous with corresponding test data input, and another input of described input data selector is prefabricated reset values 0 or 1; The selection control end of described enable signal selector, secondary clock selector and each input data selector all links to each other with the test enable end.
The chip internal register repositioning method that the present invention is based on scan chain has following advantage:
1, the chip internal register repositioning method that the present invention is based on scan chain takes full advantage of digital integrated circuit and tests necessary scan chain architecture, make up respectively scan chain by digital integrated circuit inside being reset to 0 or 1 register, to be reset to the constructed scan chain begin chain input reset values 0 of 0 register by needs, to be reset to the constructed scan chain begin chain input reset values 1 of 1 register by needs, under the control of input clock signal, scan chain begin chain input signal write successively each register in the scan chain, can realize simply and easily resetting of register, having does not affect the data path performance, stability is high, the simple advantage of physics realization, solved the performance that affects of synchronously existing or the existence of asynchronous reset technology, poor stability, have extra reset tree power consumption expense and physics realization hard problem, have performance impact low, stability is high, the effect expense is little, and is simple in structure, realize easily advantage.
2, by based on the catena method of reset values, realize resetting flexibly of register on the chain, register can be reset to 0 or 1 flexibly, have the high advantage of flexibility ratio.
3, the chip internal register repositioning control device that the present invention is based on scan chain can be tested or register resets according to the signal controlling digital integrated circuit of each input port input, utilize digital integrated circuit to test necessary scan chain architecture, except test controller is improved, do not increase extra logic, have simple in structure, realize easily advantage.
Description of drawings
Fig. 1 is the basic implementing procedure schematic diagram of the method for the embodiment of the invention.
Fig. 2 is for using register block diagram and the input and output truth table thereof of the embodiment of the invention.
Fig. 3 is for using the frame structure schematic diagram of embodiment of the invention register repositioning control device.
Fig. 4 is the frame structure schematic diagram of embodiment of the invention register repositioning control device.
Marginal data: 101, test enable end; 102, reset signal input; 103, test scan enable signal input; 104, work clock input; 105, reset clock input; 106, test clock input; 107, test data input; 1, scan chain enables control unit; 11, state controller; 12, enable signal selector; 2, scan chain clock control module; 21, one-level clock selector; 22, secondary clock selector; 3, input data selector.
Embodiment
As shown in Figure 1, the embodiment of the invention is as follows based on the implementation step of the chip internal register repositioning method of scan chain:
1) in chip design stage, at chip internal needs are reset to 0 register and make up at least one scan chain, needs are reset to 1 register make up at least one scan chain, and the scanning output end of previous register links to each other with the scan input end of a rear register in the same scan chain;
2) in the chip operational phase, the scan enable signals of each register of chip internal is set to effectively, be reset to the scan chain begin chain input reset values 0 that 0 register forms at needs, be reset to the scan chain begin chain input reset values 1 that 1 register forms at needs, and provide reset clock, control each scan chain and enter the scanning mode that resets, under the control of input reset clock, reset values write successively each register in the scan chain, after scanning last-of-chain register is written into reset values, it is invalid that scan enable signals is set to, withdraw from the scanning mode that resets, finish chip reset.
Present embodiment utilizes existing scan chain architecture for test in the digital integrated circuit chip, needs are reset to 0 and be reset to 1 register and be organized in respectively on one or more scan chain, when resetting, enter scanning mode by the control unit gated sweep chain that resets, and the input of the begin chain of scan chain fixing 0 or 1, thereby realize resetting of register, solved the existing register tree that to reset that resets, realize difficulty and have the problem of certain performance cost, the embodiment of the invention can be cancelled existing synchronous reset or the needed tree structure that resets of asynchronous reset method, be easy to realize, and without extra performance cost.
As shown in Figure 2, the embodiment of the invention comprises that based on the chip internal register repositioning control device of scan chain scan chain enables control unit 1, scan chain clock control module 2 and outputing test data or the input data selector 3 of reset values to the scan chain begin chain respectively, the input port of described repositioning control device comprises test enable end 101, reset signal input 102, test scan enable signal input 103, work clock input 104, reset clock input 105, test clock input 106 and a plurality of test data input 107, described scan chain enables control unit 1 by state controller 11 and is used for selecting the enable signal selector 12 of output scanning chain enable signal to form, described state controller 11 links to each other with reset signal input 102, and according to the value of reseting input signal 102 control reset mode, an input of described enable signal selector 12 links to each other with state controller 11, and another input of described scan chain enable signal selector 12 links to each other with test scan enable signal input 103; Described scan chain clock control module 2 forms by the one-level clock selector 21 of cascade with for the secondary clock selector 22 to integrated circuit output clock signal, the input of described one-level clock selector 21 respectively with work clock input 104, reset clock input 105 links to each other, the control end of described one-level clock selector 21 links to each other with the output of state controller 11, an input of described secondary clock selector 22 links to each other with test clock input 106, and another input of described secondary clock selector 22 links to each other with the output of one-level clock selector 21; Described input data selector 3 is corresponding one by one with test data input 107, and an input of described input data selector 3 is continuous with corresponding test data input 107, and another input of described input data selector 3 is prefabricated reset values 0 or 1; The selection control end of described enable signal selector 12, secondary clock selector 22 and each input data selector 3 all links to each other with test enable end 101.
Carrying out register when resetting, the register repositioning control device of present embodiment is set to effectively and provides reset clock with the scan enable signals of inner each register of digital integrated circuit, then at the scanning mode that resets, be reset to 0 scan chain begin chain input reset values 0 at needs, be reset to 1 scan chain begin chain input reset values 1 at needs, and under the control of reset clock, reset values write successively each register in the scan chain, the gated sweep chain withdraws from the scanning mode that resets behind the register that reset values is write all scanning last-of-chains, resets thereby finish.
The input port of the register repositioning control device of present embodiment is as follows: test enable end 101 is used for input test enable signal DFT_EN, reset signal input 102 is used for input reset signal RST, scan chain enable signal T_SE when test scan enable signal input 103 is used for input test, work clock input 104 is used for input service clock signal F_CK, reset clock input 105 is used for input reset clock signal R_CK, test clock input 106 is used for input test clock signal T_CK, test data input 107 is respectively applied to input scan test data T_SI
0T_SI
iThe output port of the register repositioning control device of present embodiment is as follows: the output of enable signal selector 12 is used in sweep test or output scanning chain enable signal SE when resetting; The output of secondary clock selector 22 is used for when test output test clock signals T_CK, output reset clock signal R_CK and at the complete rear output services clock signal F_CK that resets when resetting; The output of input data selector 3 is used for exporting reset values or output scanning test data when test when resetting.As shown in Figure 3, typical register has four input ports and a delivery outlet, and the input port is respectively data input pin D, scan input end SI, scan enable end SE and clock end CK, and output is Q.At the rising edge of clock end CK, if scan enable end SE is 0, then Q holds sampling D end data.From the input and output truth table of register as can be known, if scan enable end SE is input as 1, Q end sampling SI end data then.In other cases, no matter CK be 0 or 1, Q end all remain unchanged.
As shown in Figure 4, in the present embodiment in the digital integrated circuit register string in the full chip be one or more scan chain, and be reset to 0 and be reset to 1 register and be organized in respectively on one or more scan chain.As shown in Figure 4, have scan chain 0, scan chain 1 ..., scan chain i amounts to i+1 bar scan chain, wherein the register on the scan chain 0 all need to be reset to 0, the register on the scan chain i all need to be reset to 1.The begin chain of all scan chains all by the control of register repositioning control device, links to each other with the output of input data selector 3; Also all by the control of register repositioning control device, input end of clock CK links to each other with the output of secondary clock selector 22 for the input end of clock CK of all registers and scan enable end SE, and scan enable end SE links to each other with the output of enable signal selector 12.
The embodiment of the invention is as follows for the detailed operation process of the register repositioning control device of digital integrated circuit:
1, test enable signal DFT_EN is 1 effectively the time, and the gated sweep chain enters test pattern, and this moment, the register repositioning control device of present embodiment can be used for realizing the test of digital integrated circuit.Scan chain enable signal T_SE was scan chain enable signal SE when at this moment, enable signal selector 12 was selected test; Secondary clock selector 22 selects test clock signals T_CK as the clock signal of output; Input data selector 3 is selected respectively input test data T_SI
0T_SI
iInputting each scan chain begin chain inputs as scan chain.
2, test enable signal DFT_EN is 0 when invalid, if reset signal RST is effective, then this moment present embodiment the register repositioning control device enter the scanning mode that resets, can be used for realizing that the register of digital integrated circuit reset.At this moment, by state controller 11 output scanning enable signals, and selected as scan chain enable signal SE by enable signal selector 12; State controller 11 control one-level clock selectors 21 are selected reset clock signal R_CK and are exported as clock signal C K by secondary clock selector 22; Input data selector 3 selects respectively prefabricated reset values to input data as scan chain, if also be that all registers all need to be reset to 0 on this chain, then selects 0 as the input data output that resets; If all registers all need to be reset to 1 on this chain, then select 1 as the input data output that resets.After entering the scanning mode that resets, reset signal RST is namely revocable, and it is invalid to become.After this within the regular hour, state controller 11 is the hold reset scanning mode, thereby makes all scan chains all finish the scanning that resets, and also namely all register is all finished and resetted.After the register on all scan chains is all write reset values, it is invalid that state controller 11 is set to scan chain enable signal SE, and control one-level clock selector 21 clock signal F_CK and export as clock signal C K by secondary clock selector 22 when selecting work, thereby the gated sweep chain withdraws from the scanning mode that resets, and enters operating state.So far, all registers all are reset to the initial value of expectation by scan chain.
The above only is preferred implementation of the present invention, and protection scope of the present invention also not only is confined to above-described embodiment, and all technical schemes that belongs under the thinking of the present invention all belong to protection scope of the present invention.Should be pointed out that for those skilled in the art in the some improvements and modifications that do not break away under the principle of the invention prerequisite, these improvements and modifications also should be considered as protection scope of the present invention.
Claims (2)
1. chip internal register repositioning method based on scan chain is characterized in that implementation step is as follows:
1) in chip design stage, at chip internal needs are reset to 0 register and make up at least one scan chain, needs are reset to 1 register make up at least one scan chain, and the scanning output end of previous register links to each other with the scan input end of a rear register in the same scan chain;
2) in the chip operational phase, the scan enable signals of each register of chip internal is set to effectively, be reset to the scan chain begin chain input reset values 0 that 0 register forms at needs, be reset to the scan chain begin chain input reset values 1 that 1 register forms at needs, and provide reset clock, control each scan chain and enter the scanning mode that resets, under the control of input reset clock, reset values write successively each register in the scan chain, after scanning last-of-chain register is written into reset values, it is invalid that scan enable signals is set to, withdraw from the scanning mode that resets, finish chip reset.
2. chip internal register repositioning control device based on scan chain, it is characterized in that: comprise that scan chain enables control unit (1), scan chain clock control module (2) and outputing test data or the input data selector (3) of reset values to the scan chain begin chain respectively, the input port of described repositioning control device comprises test enable end (101), reset signal input (102), test scan enable signal input (103), work clock input (104), reset clock input (105), test clock input (106) and a plurality of test data input (107), described scan chain enables control unit (1) by state controller (11) and is used for selecting the enable signal selector (12) of output scanning chain enable signal to form, described state controller (11) links to each other with reset signal input (102), and according to the value of reseting input signal (102) control reset mode, an input of described enable signal selector (12) links to each other with state controller (11), and another input of described scan chain enable signal selector (12) links to each other with test scan enable signal input (103); Described scan chain clock control module (2) forms by the one-level clock selector (21) of cascade with for the secondary clock selector (22) to integrated circuit output clock signal, the input of described one-level clock selector (21) respectively with work clock input (104), reset clock input (105) links to each other, the control end of described one-level clock selector (21) links to each other with the output of state controller (11), an input of described secondary clock selector (22) links to each other with test clock input (106), and another input of described secondary clock selector (22) links to each other with the output of one-level clock selector (21); Described input data selector (3) is corresponding one by one with test data input (107), and an input of described input data selector (3) is continuous with corresponding test data input (107), and another input of described input data selector (3) is prefabricated reset values 0 or 1; The selection control end of described enable signal selector (12), secondary clock selector (22) and each input data selector (3) all links to each other with test enable end (101).
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