CN106324463A - Scan chain control circuit design method and scan chain circuit - Google Patents
Scan chain control circuit design method and scan chain circuit Download PDFInfo
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- CN106324463A CN106324463A CN201510342658.5A CN201510342658A CN106324463A CN 106324463 A CN106324463 A CN 106324463A CN 201510342658 A CN201510342658 A CN 201510342658A CN 106324463 A CN106324463 A CN 106324463A
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- scan
- scan chain
- configuration register
- scanning
- enable signal
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Abstract
The invention discloses a scan chain control circuit design method. Based on a traditional scan chain circuit, one or more groups of configuration registers and one or more levels of decoding circuits which are corresponding to the configuration registers and an enable port for controlling the scan chain circuit are set, and thus whether a scan test is carried out is controlled. The invention also discloses the scan chain circuit. The anti-attach ability of the safety chip in inserting into a scan chain can be improved, and the safety of the scan chain is ensured.
Description
Technical field
The present invention relates to security classes chip volume production field tests, particularly relate to a kind of scan chain and control electricity
Road method for designing.The invention still further relates to a kind of scan chain circuits.
Background technology
Testing cost gradually during the whole manufacturing of chip proportion increasing, therefore measure
Produce method of testing to be widely applied in chip, such as testing scanning chain.But due to security classes core
Sheet is based on security consideration, or uses the most original function test method so that testing cost cannot drop
Low.
Fig. 1 is traditional scan chain circuit structure chart, and Fig. 2 is the cut-away view of traditional scan chain circuit.
As a example by circuit shown in Fig. 1 Fig. 2, all depositors are by external pin clock clk, reset rst, test
Pattern test_mode, scanning enables scan_en and directly controls, as long as having broken through scan_en place
Physical message, user just may be used by scan data input scan_si and scan data output scan_so
To read the numerical value of any depositor at any time so that whole chip does not has any secret to say.For society
For protecting class chip, safety is the first element, and it is invisible that safety itself comprises the part logic in chip.
Traditional scan chain method of testing violates this demand.
Summary of the invention
The technical problem to be solved in the present invention is to provide a kind of scan chain design on control circuit method, it is possible to
Improve the safety chip anti-attack ability when interleave scan chain, it is ensured that the safety of scan chain self；For
This, the present invention also provides a kind of scan chain circuits.
For solving above-mentioned technical problem, the scan chain design on control circuit method of the present invention is that employing is as follows
Technical scheme realizes: on the basis of traditional scan chain circuits, arranges one group or assembles more
Put depositor, and one or more levels decoding circuit corresponding, produce scan enable signal
Can control signal, be used for controlling the enable port of scan chain circuits, thus control sweep test and carry out.
Described scan chain circuits, including multi-strip scanning chain, every scan chain includes one or more scanning
Unit, wherein, also includes configuration register and controls logical block, the scan enable signal quilt of input
Described configuration register and control logical block are controlled；
Described configuration register, is used for depositing Configuration Values, may determine that scanning enables according to this Configuration Values
The passage of the scanning enable port that signal arrives each scanning element is opened or is closed；
Described control logical block, arrives the scanning of each scanning element for setting up scan enable signal
The passage of enable port；Configuration Values according to described configuration register generates a series of different scannings and makes
The control signal of energy signal, the control signal of these scan enable signals and the scan enable signal of input
Combination, forms gate structure, and then generates multiple new scan enable signal, go to control each and sweep
Retouch one or more scanning element in chain.
The present invention uses configuration register and decoding circuit to produce the control signal of scan chain circuits Enable Pin
(i.e. the control signal of scan enable signal), controls the Enable Pin of scan chain circuits, sweeps reaching control
Retouch chain circuit and in domain, hide the purpose of scan chain Enable Pin, being so easy in domain hide and sweep
Retouch chain and enable signal, increase the difficulty that testing scanning chain method is broken when security classes chip, from
And improve the safety chip anti-attack ability when interleave scan chain.
Use the present invention, as long as by some specific mode, businessman can either be made can to test rank
Section be scanned test, it is also possible to after product export control scan chain enable port, thus stop from
The probability of security attack is carried out, to ensure the security performance of product in Scan Design.
Accompanying drawing explanation
The present invention is further detailed explanation with detailed description of the invention below in conjunction with the accompanying drawings:
Fig. 1 is traditional scan chain circuit theory diagram；
Fig. 2 is the circuit theory diagrams of traditional scan chain circuit shown in Fig. 1；
Fig. 3 is the scan chain circuits one example structure figure after improving；
Fig. 4 be improve shown in Fig. 3 after the circuit theory diagrams of scan chain circuits one embodiment；
Fig. 5 is the control logic I structure chart of scan enable signal scan_en；
Fig. 6 is the control logic II structure chart of scan enable signal scan_en.
Detailed description of the invention
See shown in Fig. 3, Fig. 4, it is assumed that in design, scan chain circuits contains n bar scan chain altogether, every
Scan chain includes that clock signal clk, reset signal rst and test pattern control wire size test_mode；
Every scan chain includes one or more scanning element (be on scan chain one of each scanning element
Depositor).Scan chain circuits after improvement, also includes configuration register and controls logical block.Input
Scan enable signal scan_en by described configuration register and control logical block control.
Described configuration register, is used for depositing Configuration Values, may determine that scanning enables according to this Configuration Values
The passage of the scanning enable port that signal scan_en arrives each scanning element is opened or is closed.
Described control logical block, is used for setting up scan enable signal scan_en and arrives each scanning list
The passage of the scanning enable port of unit；Configuration Values according to described configuration register generates a series of differences
The control signal of scan enable signal, the control signal of these scan enable signals and the scanning of input
Enable signal combines, and forms gate structure, and then generates substantial amounts of new scan enable signal, goes control
Make one or more scanning element in each scan chain, make to reach to hide scanning physically
The purpose of energy signal.
Demand according to design determines the distribution of produced scan enable signal, and this distribution is for all
Scanning element, a scanning element can use a scan enable signal, it is also possible to multiple scanning lists
Unit shares a scan enable signal, as long as ensureing that the scanning Enable Pin of all of scanning element is all contained
Lid arrives.Shown in Fig. 4, the scan enable signal being different from tradition scanning circuit single connects
Mode, the connection side of the scanning Enable Pin of each scanning element on scan chain in scanning circuit after improvement
Formula is had nothing in common with each other, and can share a scan enable signal with several scanning elements, it is also possible to each scanning
Unit uses a scan enable signal.
Domestic consumer cannot access described configuration register, and the control signal of described scan enable signal exists
Before dispatching from the factory controlled and invalid under user EXEC.
In test mode, system can be correct to the configuration of described configuration register by specific mode
Value, opens the scanning Enable Pin from the scanning enable port of scan chain circuits to each scanning element
Path so that it is can be scanned enabling the straightway control of signal, thus open scan chain function and enter
Row sweep test.
Before product test completes and encapsulates and dispatches from the factory, again described configuration register is configured,
Disconnect leading to of the scanning Enable Pin from the scanning enable port of scan chain circuits to each scanning element
Road, and cancel or hide the access mode of described configuration register, after making to dispatch from the factory, scan chain circuits cannot
Work.Thus solve user's security hidden trouble by scan chain pry chip internal safety information.
Meanwhile, because the control signal of newly generated scan enable signal have passed through different combination logiies,
Present a kind of random combined logical structure physically, there is certain disguise, and unlike passing
In system scan chain circuits, present the logical structure of high capacity, easily be cracked out, so this
The bright safety that improve chip to a certain extent.
Described control logical block can use multiple different circuit realiration, in an enforcement of the present invention
Controlling logical block in example can use decoding circuit and corresponding gating circuit to realize.
The quantity of described configuration register and figure place are according to scanning element total on all scan chains in design
Number determines, the bit wide of each configuration register can be different.
Described configuration register and decoding circuit design according to project demands, configuration register and decoding electricity
Road is man-to-man relation, the control signal of scan enable signal of decoding circuit generation and original sweeping
Retouch enable signal combination, form gate structure.
Fig. 5 and Fig. 6 gives two kinds of scan enable signals scan_en and controls logic.Fig. 5 shows
Man-to-man configuration register and the population structure of decoding circuit, both cooperations create all of sweeping
Retouch enable signal scan_en.Fig. 6 then shows that every grade of configuration register and decoding circuit control scanning and make
The detailed construction of energy signal scan_en.Configuration Values in configuration register is decoded by decoding circuit,
Then the scanning being transmitted through by upper level enables control signal and carries out secondary gate, then is sent to next grating
Put depositor and decoding circuit.All scan enable signals scan_en of final generation.
Described scan chain design on control circuit method implementation is as follows: first analyze all in design sweeping
Retouch the total quantity of scanning element on chain, determine number and the figure place of configuration register；Secondly design configurations
Depositor and decoding circuit；It is then determined that the access mode of configuration register and unlatching scanning enable path
Value；Then the scan enable signal distribution condition for all scanning elements is determined, finally according to biography
The scan chain circuits method for designing of system completes other parts design of scan chain circuits.Its concrete steps are such as
Under:
1, according in design on all scan chains the sum of scanning element determine configuration register number and
Figure place；The bit wide of each configuration register can be different.Assuming that the bit wide of all configuration registers is total
It is greater than the integer equal to 1, then the maximum scan that finally can produce enables and controls letter with for wa, wa
Number number be 2wa。
2, according to project demands design configurations depositor and decoding circuit thereof, configuration register and decoding electricity
Road is man-to-man relation.The control signal of scan enable signal of decoding circuit generation and original sweeping
Retouch enable signal combination, form gate structure, if the control signal of scan enable signal is 1 effectively, then
Use and door, if the control signal of scan enable signal is 0 effectively, then use or door.Configuration register
Flat pattern, i.e. only one of which depositor can be designed to, directly produced scanning by decoding circuit decoding
Enabling control signal, the logic progression so produced is comparatively short, beneficially sequential, but sets from physics
From the point of view of on meter, track configuration register also ratio comparatively fast from the scanning enable port SE of scanning element, hold
Easily break through, be unfavorable for safety.Configuration register can be designed to tower, is i.e. deposited by multiple configurations
The control of device one-level one-level forms, as shown in Figure 5.Assuming that the bit wide of m-th configuration register is A, that
The scanning that this configuration register can produce after decoding circuit enables control signal number S=2A, each
It is new that the control signal of scan enable signal and each scan enable signal of upper level reconfigure formation
Scan enable signal, each making the scan enable signal that upper level produces all extends 2ATimes,
This design is only broken through the value of all configuration registers, each scan chain just can be made to open,
Improve safety, but the progression controlling logic increased, and is unfavorable for sequential；Can be according to item
Purpose demand appropriate design.
3, according to the practical situation of design, and the demand that this design is to security performance, determine that access is joined
Put the mode of depositor and open the register configuration values of scan chain circuits.The access of configuration register
Mode and Configuration Values are the key means protecting safety information in present design, it is ensured that these 2 not by
People beyond designer obtains and is to ensure that Scan Design is not used for the basis of security attack.
A, the access mode of configuration register must are fulfilled for following two condition:
, dispatch from the factory before can be accessed in test mode；
, dispatch from the factory after domestic consumer cannot access；
B, the Configuration Values of configuration register can be set by design is random, it is also possible to the demand of matching design
Consider.
4, the distribution condition of produced scan enable signal in the 2nd step is determined according to the demand of design,
This distribution condition is aimed at all scanning elements, a scanning element can use a scanning
Enable signal, it is also possible to multiple scanning elements share a scan enable signal, as long as ensureing all of
The Enable Pin of scanning element is all resorted to.
5, according to this Scan Design scheme, produce corresponding scan test vector, emulate, with really
Protect the feasibility of the program.Compared with traditional Scan Design, invention increases a configuration process
(i.e. configuring the value of " configuration register "), before producing scan test vector, it is necessary to first definition is joined
Put sequence；Complete the design of scanning circuit.
Above by detailed description of the invention, the present invention is described in detail, but these have not been constituted
Limitation of the present invention.Without departing from the principles of the present invention, those skilled in the art also may be used
Making many deformation and improve, these also should be regarded as protection scope of the present invention.
Claims (20)
1. a scan chain design on control circuit method, it is characterised in that: in scan chain circuits, if
Put one group or organize configuration register more, and one or more levels decoding circuit corresponding, produce
The control signal of raw scan enable signal, is used for controlling the enable port of scan chain circuits, thus controls
Can sweep test be carried out.
2. the method for claim 1, it is characterised in that: domestic consumer cannot access described in join
Putting depositor, the control signal of described scan enable signal is controlled before dispatching from the factory, and at domestic consumer's mould
Under formula invalid.
3. the method for claim 1, it is characterised in that: making of described control scan chain circuits
Can refer to by port, described configuration register generates a series of different scanning by decoding circuit and enables letter
Number control signal, and then generate multiple new scan enable signal, go to control described scan chain circuits
In one or more scanning element in each scan chain.
4. method as claimed in claim 3, it is characterised in that: determine according to the demand of design and produced
The distribution of raw scan enable signal, this distribution, can a scanning element for all scanning elements
Use a scan enable signal, it is also possible to multiple scanning elements share a scan enable signal, only
Ensure that the scanning Enable Pin of all of scanning element is all resorted to.
5. the method as described in claims 1 to 3 is arbitrary, it is characterised in that: in test mode,
By specific mode, described configuration register can be configured correct value, open from scan chain circuits
Enable port is to the path of the scanning Enable Pin of each scanning element so that it is can be scanned enabling letter
Number straightway control, thus open scan chain function and be scanned test.
6. method as claimed in claim 5, it is characterised in that: when product test completes and encapsulates out
Before factory, again described configuration register is configured, disconnect from the enable port of scan chain circuits
To the path of the scanning Enable Pin of each scanning element, and cancel or hide described configuration register
Access mode, after making to dispatch from the factory, scan chain cannot work.
7. the method for claim 1, it is characterised in that: the quantity of described configuration register and
Figure place determines according to the sum of scanning element on all scan chains in design, the position of each configuration register
Width can be different.
8. the method for claim 1, it is characterised in that: described configuration register and decoding thereof
Circuit designs according to project demands, and configuration register and decoding circuit are man-to-man relation, decoding electricity
The control signal of the scan enable signal that road generates combines with original scan enable signal, forms gate
Structure.
9. the method for claim 1, it is characterised in that: according to design practical situation, with
And the demand that this design is to security performance, determine and access the mode of configuration register and open scan chain
The Configuration Values of the configuration register of circuit.
10. method as claimed in claim 9, it is characterised in that: the access side of described configuration register
Formula must is fulfilled for following two condition:
, dispatch from the factory before can be accessed in test mode；, dispatch from the factory after domestic consumer cannot access；
The Configuration Values of described configuration register can be set by design is random, it is also possible to the need of matching design
Ask and consider.
11. 1 kinds of scan chain circuits, including multi-strip scanning chain, every scan chain includes one or more
Scanning element, it is characterised in that: also include configuration register and control logical block, the scanning of input
Enable signal to be controlled by described configuration register and control logical block；
Described configuration register, is used for depositing Configuration Values, may determine that scanning enables according to this Configuration Values
The passage of the scanning enable port that signal arrives each scanning element is opened or is closed；
Described control logical block, arrives the scanning of each scanning element for setting up scan enable signal
The passage of enable port；Configuration Values according to described configuration register generates a series of different scannings and makes
The control signal of energy signal, the control signal of these scan enable signals and the scan enable signal of input
Combination, forms gate structure, and then generates multiple new scan enable signal, go to control each and sweep
Retouch one or more scanning element in chain.
12. scan chain circuits as claimed in claim 11, it is characterised in that: described configuration register
Being man-to-man relation with controlling logical block, described configuration register is one group or many groups, therewith
Corresponding described control logical block is also one or more.
13. scan chain circuits as claimed in claim 11, it is characterised in that: domestic consumer cannot visit
Asking described configuration register, the control signal of described scan enable signal is controlled before dispatching from the factory, and general
It is invalid to lead under user model.
14. scan chain circuits as claimed in claim 11, it is characterised in that: in test mode,
By specific mode, described configuration register can be configured correct value, open from scan chain circuits
Enable port is to the path of the scanning Enable Pin of each scanning element so that it is can be scanned enabling letter
Number straightway control, thus open scan chain function and be scanned test.
15. scan chain circuits as described in claim 11 or 14, it is characterised in that: according to design
Demand determine the distribution of produced scan enable signal, this distribution, can for all scanning elements
A scan enable signal is used, it is also possible to multiple scanning elements share one and sweep with a scanning element
Retouch enable signal, as long as ensureing that the scanning Enable Pin of all of scanning element is all resorted to.
16. scan chain circuits as claimed in claim 14, it is characterised in that: when product test completes
And before encapsulation is dispatched from the factory, again described configuration register is configured, disconnect from scan chain circuits
Enable port is to the path of the scanning Enable Pin of each scanning element, and cancels or hide described configuration
The access mode of depositor, after making to dispatch from the factory, scan chain cannot work.
17. scan chain circuits as claimed in claim 11, it is characterised in that: described configuration register
Quantity and figure place according in design on all scan chains the sum of scanning element determine, each configuration is posted
The bit wide of storage can be different.
18. scan chain circuits as claimed in claim 11, it is characterised in that: described control logic list
Unit is decoding circuit and corresponding gating circuit；Configuration register and decoding circuit thereof are according to project demands
Design, configuration register and decoding circuit are man-to-man relation, and the scanning that decoding circuit generates enables
The control signal of signal combines with original scan enable signal, forms gate structure.
19. scan chain circuits as claimed in claim 11, it is characterised in that: according to the reality of design
Situation, and the demand that this design is to security performance, determine and access the mode of configuration register and open
Open the Configuration Values of the configuration register of scan chain circuits.
20. scan chain circuits as claimed in claim 19, it is characterised in that: described configuration register
Access mode must be fulfilled for following two condition:
, dispatch from the factory before can be accessed in test mode；, dispatch from the factory after domestic consumer cannot access；
The Configuration Values of described configuration register can be set by design is random, it is also possible to the demand of matching design is combined
Close and consider.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201510342658.5A CN106324463A (en) | 2015-06-19 | 2015-06-19 | Scan chain control circuit design method and scan chain circuit |
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| CN201510342658.5A CN106324463A (en) | 2015-06-19 | 2015-06-19 | Scan chain control circuit design method and scan chain circuit |
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Cited By (3)
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| CN108335707A (en) * | 2018-02-09 | 2018-07-27 | 盛科网络（苏州）有限公司 | A kind of high speed memory designs method and device with mask |
| CN111103959A (en) * | 2019-12-20 | 2020-05-05 | 展讯通信（上海）有限公司 | Register resetting system and chip |
| CN112444735A (en) * | 2020-11-27 | 2021-03-05 | 海光信息技术股份有限公司 | Securely configurable chip and method of operation thereof |
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| CN102565684A (en) * | 2010-12-13 | 2012-07-11 | 上海华虹集成电路有限责任公司 | Security-based scan chain control circuit, scan chain testing circuit and use method |
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Application publication date: 20170111 |