CN114116600A - Chip power consumption reduction design method and chip - Google Patents
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Abstract
本发明公开了一种芯片降功耗设计方法及芯片，从芯片上所设计的移位寄存器链组中确定预用存储器替换的目标移位寄存器链组；将目标移位寄存器链组内各目标移位寄存器链的数字输入信号和数字输出信号相应作为存储器的数字输入信号和数字输出信号，并将目标移位寄存器链组的使能信号作为存储器的使能信号；根据目标移位寄存器链组的寄存器链深度，构建存储器的地址信号；根据目标移位寄存器链组内各寄存器的存储初值，构建存储器的存储初值；将构建好输入输出信号、使能信号、地址信号及存储初值的存储器替换目标移位寄存器链组。可见，本申请可使用存储器代替芯片上所设计的移位寄存器链组，从而大幅减少了芯片的动态功耗，且减少了芯片的占用面积。
The invention discloses a chip power consumption reduction design method and a chip. A target shift register chain group to be replaced with a memory in advance is determined from a shift register chain group designed on the chip; The digital input signal and digital output signal of the shift register chain are correspondingly used as the digital input signal and digital output signal of the memory, and the enable signal of the target shift register chain group is used as the enable signal of the memory; according to the target shift register chain group According to the register chain depth, the address signal of the memory is constructed; according to the storage initial value of each register in the target shift register chain group, the storage initial value of the memory is constructed; the input and output signals, enable signal, address signal and storage initial value will be constructed. replaces the target shift register chain set. It can be seen that the present application can use memory to replace the shift register chain group designed on the chip, thereby greatly reducing the dynamic power consumption of the chip and reducing the occupied area of the chip.
Description
Technical Field
The invention relates to the field of chip design, in particular to a chip power consumption reduction design method and a chip.
Background
Along with the increasing functions of the chip and the increasing operating frequency of the chip, the problems of high power consumption and high heat generation of the chip are more and more serious, the overall performance of the equipment where the chip is located is also more and more seriously affected, and therefore the requirement for low-power-consumption design of the chip is higher and higher. At present, shift registers (shift register chain, which is formed by connecting a plurality of registers and is characterized in that the output of one register directly drives the input of the next register) are adopted in most chip designs to store data, and the shift register chain causes a large number of inversions of the registers due to successive shift operation when storing data, so that the dynamic power consumption of the chip is high.
Therefore, how to provide a register level power reduction scheme is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a chip power consumption reduction design method and a chip, wherein a memory can be used for replacing a shift register chain set designed on the chip, and the memory reads and writes data in a reading and writing pointer mode, so that the value of a storage unit to be written in is only changed when the memory stores the data, and the rest storage units are kept still, thereby greatly reducing the dynamic power consumption of the chip and reducing the occupied area of the chip.
In order to solve the technical problem, the invention provides a chip power consumption reduction design method, which comprises the following steps:
determining a target shift register chain group to be replaced by a memory from a shift register chain group designed on a chip; each shift register chain in the same shift register chain group is respectively used for storing different bits in the same data;
correspondingly taking the digital input signal and the digital output signal of each target shift register chain in the target shift register chain group as the digital input signal and the digital output signal of the memory, and taking the enable signal of the target shift register chain group as the enable signal of the memory;
constructing an address signal of the memory according to the register chain depth of the target shift register chain group;
constructing a storage initial value of the memory according to the storage initial value of each register in the target shift register chain group;
and replacing the target shift register chain group by the memory which is well constructed with input and output signals, an enabling signal, an address signal and a storage initial value.
Optionally, determining a target shift register chain set to be replaced by a memory from the shift register chain sets designed on the chip includes:
judging whether control signals of all registers in a first shift register chain set designed on a chip are the same or not and whether types of all registers in the first shift register chain set are the same or not; the first shift register chain group is any one shift register chain group;
if the judgment result is yes, determining the first shift register chain group as a target shift register chain group to be replaced by the pre-used memory;
and if the judgment result is negative, determining that the first shift register chain group is not the target shift register chain group to be replaced by the pre-used memory.
Optionally, the determining whether the types of the registers in the first shift register chain group are the same includes:
judging whether all registers in the first shift register chain group are synchronous registers or asynchronous registers;
if yes, determining that the types of the registers in the first shift register chain group are the same;
and if not, determining that the types of the registers in the first shift register chain group are not the same.
Optionally, the corresponding digital input signal and digital output signal of each target shift register chain in the target shift register chain group as the digital input signal and digital output signal of the memory includes:
obtaining data input signals DI [ N:0] of the memory according to digital input signals DI [0] to DI [ N ] of each target shift register chain in the target shift register chain group; DI [ M ] is the digital input signal of the M +1 th target shift register chain in the target shift register chain group; m is not less than 0 and not more than N, and M is an integer; n is the total number of the target shift register chains in the target shift register chain group-1;
obtaining data output signals DO [ N:0] of the memory according to digital output signals DO [0] to DO [ N ] of each target shift register chain in the target shift register chain group; and DO [ M ] is a digital output signal of an M +1 th target shift register chain in the target shift register chain group.
Optionally, constructing an address signal of the memory according to the register chain depth of the target shift register chain group includes:
determining the number of storage units of the memory according to the register chain depth of the target shift register chain group; wherein the number of the storage units is more than or equal to the depth of the register chain;
and constructing an address signal for representing the address of the memory unit of the memory according to the number of the memory units of the memory.
Optionally, determining the number of storage units of the memory according to the register chain depth of the target shift register chain group; according to the number of the memory cells of the memory, constructing an address signal for representing the address of the memory cell of the memory, comprising:
calculating a width-ceil (log) relation according to the preset address bit width2depth) calculating an address bit width of the memory to construct an address signal of the memory based on the address bit width; wherein ceil represents rounding up; depth is the register chain depth.
Optionally, constructing an initial storage value of the memory according to an initial storage value of each register in the target shift register chain group, where the method includes:
combining the initial storage values of the A-th registers of all the target shift register chains in the target shift register chain group from high bits to low bits to obtain the initial storage value of the A-th storage unit of the memory; wherein A is a positive integer.
Optionally, the chip power consumption reduction design method further includes:
after the initial storage value of the memory is constructed, if the memory still has residual capacity, the initial storage value of the storage unit under the residual capacity is set to be 0.
Optionally, the memory is an SRAM;
replacing the target shift register chain set with the memory having the input/output signal, the enable signal, the address signal, and the stored initial value, comprising:
and replacing the target shift register chain group with the SRAM with the input and output signals, the enable signal, the address signal and the stored initial value.
In order to solve the technical problem, the invention also provides a chip which is designed by adopting the steps of any chip power consumption reduction design method.
The invention provides a chip power consumption reduction design method, which comprises the steps of determining a target shift register chain group to be replaced by a memory from a shift register chain group designed on a chip; correspondingly taking the digital input signal and the digital output signal of each target shift register chain in the target shift register chain group as the digital input signal and the digital output signal of the memory, and taking the enable signal of the target shift register chain group as the enable signal of the memory; constructing an address signal of a memory according to the register chain depth of the target shift register chain group; constructing a storage initial value of a memory according to the storage initial value of each register in the target shift register chain group; and replacing the target shift register chain group with the memory which is constructed with the input and output signals, the enable signal, the address signal and the storage initial value. Therefore, the memory can be used for replacing the shift register chain set designed on the chip, and the memory reads and writes data in a reading and writing pointer mode, so that the value of the storage unit to be written in is only changed when the memory stores the data, and the rest storage units are kept static, thereby greatly reducing the dynamic power consumption of the chip and reducing the occupied area of the chip.
The invention also provides a chip which has the same beneficial effect as the power consumption reduction design method.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a flowchart of a power consumption reduction design method for a chip according to an embodiment of the present invention;
fig. 2 is a circuit diagram of a shift register chain set replaced with a memory according to an embodiment of the present invention.
Detailed Description
The core of the invention is to provide a chip power consumption reduction design method and a chip, a memory can be used for replacing a shift register chain set designed on the chip, and the memory reads and writes data in a reading and writing pointer mode, so that the memory only needs to change the value of a storage unit to be written when storing data, and the rest storage units are kept still, thereby greatly reducing the dynamic power consumption of the chip and reducing the occupied area of the chip.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart of a power consumption reduction design method for a chip according to an embodiment of the present invention.
The chip power consumption reduction design method comprises the following steps:
step S1: and determining a target shift register chain group to be replaced by the memory from the designed shift register chain group on the chip.
Specifically, a plurality of shift register chain groups are designed on a chip, and considering that some shift register chain groups can be directly replaced by a memory and some shift register chain groups cannot be directly replaced by the memory, the method firstly determines a target shift register chain group to be replaced by the memory from the shift register chain groups designed on the chip so as to provide a basis for subsequent memory replacement.
It should be noted that each shift register chain group includes a plurality of shift register chains, and each shift register chain in the same shift register chain group is used for storing different bits in the same data.
Step S2: and correspondingly taking the digital input signal and the digital output signal of each target shift register chain in the target shift register chain group as the digital input signal and the digital output signal of the memory, and taking the enable signal of the target shift register chain group as the enable signal of the memory.
Specifically, the input/output signal and the enable signal of the memory are constructed according to the input/output signal and the enable signal of the target shift register chain group to be replaced by the memory, namely, the digital input signal of each target shift register chain in the target shift register chain group is used as the digital input signal of the memory, the digital output signal of each target shift register chain in the target shift register chain group is used as the digital output signal of the memory, and the enable signal of the target shift register chain group is used as the enable signal of the memory.
Step S3: and constructing an address signal of the memory according to the register chain depth of the target shift register chain group.
Specifically, the register chain depth of the target shift register chain group represents the data amount storable by the target shift register chain group, the address signal of the memory represents the address range of the memory unit used for storing data in the memory, and the number of the memory units in the memory is equal to the data amount storable by the memory, so the method can construct the address signal of the memory according to the register chain depth of the target shift register chain group.
Step S4: and constructing a storage initial value of the memory according to the storage initial value of each register in the target shift register chain group.
Specifically, it can be understood that the initial value stored in the memory replacing the target shift register chain group should be equal to the initial value stored in the target shift register chain group, so the present application may construct the initial value stored in the memory according to the initial value stored in each register in the target shift register chain group.
Step S5: and replacing the target shift register chain group with the memory which is constructed with the input and output signals, the enable signal, the address signal and the storage initial value.
Specifically, after the input/output signal, the enable signal, the address signal and the initial storage value of the memory are all constructed, the constructed input/output signal, the enable signal, the address signal and the initial storage value of the memory can replace a target shift register chain set designed on a chip.
Therefore, the memory can be used for replacing the shift register chain set designed on the chip, and the memory reads and writes data in a reading and writing pointer mode, so that the value of the storage unit to be written in is only changed when the memory stores the data, and the rest storage units are kept static, thereby greatly reducing the dynamic power consumption of the chip and reducing the occupied area of the chip.
On the basis of the above-described embodiment:
as an alternative embodiment, the method for determining a target shift register chain group to be replaced by a memory from a shift register chain group designed on a chip includes:
judging whether control signals of all registers in a first shift register chain group designed on a chip are the same or not and whether types of all registers in the first shift register chain group are the same or not; the first shift register chain group is any shift register chain group;
if the judgment result is yes, determining the first shift register chain group as a target shift register chain group to be replaced by the memory;
and if the judgment result is negative, determining that the first shift register chain group is not the target shift register chain group to be replaced by the memory.
Specifically, the process of determining the target shift register chain group to be replaced by the memory is as follows: judging whether control signals (such as enabling signals) of all registers in any shift register chain group (called as a first shift register chain group) designed on a chip are the same or not and whether types of all registers in the first shift register chain group are the same or not; if the control signals of all the registers in the first shift register chain group are the same and the types of all the registers in the first shift register chain group are the same, namely the judgment results are yes, the first shift register chain group is determined to be a target shift register chain group to be replaced by a pre-used memory, and the memory can be designed to replace the first shift register chain group; and if the control signals of the registers in the first shift register chain group are not the same and/or the types of the registers in the first shift register chain group are not the same, namely whether the judgment result is the situation exists or not, determining that the first shift register chain group is not the target shift register chain group to be replaced by the memory, namely, the memory cannot be designed to replace the first shift register chain group.
As an alternative embodiment, the determining whether the types of the registers in the first shift register chain group are all the same includes:
judging whether all registers in the first shift register chain group are synchronous registers or asynchronous registers;
if so, determining that the types of the registers in the first shift register chain group are the same;
if not, determining that the types of the registers in the first shift register chain group are not the same.
Specifically, the process of determining whether the types of the registers in the first shift register chain group are the same according to the present application is as follows: judging whether all registers in the first shift register chain group are synchronous registers or asynchronous registers; if all registers in the first shift register chain group are synchronous registers or asynchronous registers, determining that the types of all registers in the first shift register chain group are the same; and if the registers in the first shift register chain group are not all synchronous registers or asynchronous registers, determining that the types of the registers in the first shift register chain group are not the same.
As an alternative embodiment, the method for using the digital input signal and the digital output signal of each target shift register chain in the target shift register chain group as the digital input signal and the digital output signal of the memory respectively comprises the following steps:
obtaining data input signals DI [ N:0] of the memory according to digital input signals DI [0] to DI [ N ] of each target shift register chain in the target shift register chain group; DI [ M ] is the digital input signal of the M +1 th target shift register chain in the target shift register chain group; m is not less than 0 and not more than N, and M is an integer; n is the total number of the target shift register chains in the target shift register chain group-1;
obtaining data output signals DO [ N:0] of the memory according to digital output signals DO [0] to DO [ N ] of each target shift register chain in the target shift register chain group; wherein DO [ M ] is the digital output signal of the M +1 th target shift register chain in the target shift register chain group.
Specifically, the process of using the digital input/output signal of each target shift register chain in the target shift register chain group as the digital input/output signal of the memory correspondingly comprises the following steps: obtaining data input signals DI [ N:0] of the memory according to digital input signals DI [0] to DI [ N ] of each target shift register chain in the target shift register chain group; DI [ M ] is the digital input signal of the M +1 th target shift register chain in the target shift register chain group, and the digital input signal DI [ M ] of the M +1 th target shift register chain is used as DI [ M ] in the data input signal DI [ N:0] of the memory. Similarly, according to the digital output signals DO [0] to DO [ N ] of each target shift register chain in the target shift register chain group, obtaining the data output signal DO [ N:0] of the memory; wherein DO [ M ] is the digital output signal of the M +1 th target shift register chain in the target shift register chain group, and the digital output signal DO [ M ] of the M +1 th target shift register chain is used as DO [ M ] in the data output signal DO [ N:0] of the memory.
As shown in fig. 2, fig. 2 shows a shift register chain set for storing 4-bit data, the shift register chain set includes 4 shift register chains, the 4 shift register chains are respectively used for storing different bits in the 4-bit data, the digital input signals of the 4 shift register chains are DI [0], DI [1], DI [2], DI [3], and the digital output signals are DO [0], DO [1], DO [2], DO [3], the data input signal for the memory replacing the shift register chain group is DI [3:0] (formed by combining DI [3], DI [2], DI [1], DI [0] from high bit to low bit), and the data output signal for the memory replacing the shift register chain group is DO [3:0] (formed by combining DO [3], DO [2], DO [1], DO [0] from high bit to low bit).
As an alternative embodiment, constructing the address signal of the memory according to the register chain depth of the target shift register chain group includes:
determining the number of storage units of a memory according to the register chain depth of a target shift register chain group; wherein, the number of the storage units is more than or equal to the depth of the register chain;
and constructing an address signal for representing the address of the memory cell of the memory according to the number of the memory cells of the memory.
Specifically, the process of constructing the address signal of the memory comprises the following steps: firstly, the number of storage units of a memory for replacing a target shift register chain group is determined according to the register chain depth of the target shift register chain group, and it can be understood that the number of storage units is greater than or equal to the register chain depth, so that all data stored in the target shift register chain group can be completely transferred to the memory, and the integrity of the data after the target shift register chain group is replaced is ensured. Then, according to the number of the memory cells of the memory, an address signal representing the address of the memory cell of the memory is constructed.
As an alternative embodiment, the number of memory cells of the memory is determined according to the register chain depth of the target shift register chain group; according to the number of the memory cells of the memory, constructing an address signal for representing the address of the memory cell of the memory, comprising:
calculating a width-ceil (log) relation according to the preset address bit width2depth) calculating the address bit width of the memory to construct an address signal of the memory based on the address bit width; wherein ceil represents rounding up; depth is the register chain depth.
Specifically, the address signal of the memory can be constructed based on the address bit width of the memory, and the address signal is replacedThe address bit width of the memory of the target shift register chain group and the register chain depth of the target shift register chain group have a certain corresponding relation: width ═ ceil (log)2depth), i.e., the address bit width of the memory is log2Rounding up depth, if the register chain depth of the target shift register chain group is 16, the address bit width of the memory is 4, and the number of memory cells of the memory can be 2416; the depth of the register chain of the target shift register chain group is 17, the address bit width of the memory is 5, and the number of the memory units of the memory can be 25This ensures that all data stored in the target shift register chain set can be transferred to memory as full as 32.
In addition, the output of the counter can be used as the read-write address of the memory, and the counter can be realized by using a primitive with an addition function on an FPGA (Field Programmable Gate Array).
As an alternative embodiment, the constructing the initial storage value of the memory according to the initial storage value of each register in the target shift register chain group includes:
combining the initial storage values of the A-th registers of all the target shift register chains in the target shift register chain group from high bits to low bits to obtain the initial storage value of the A-th storage unit of the memory; wherein A is a positive integer.
Specifically, the process of constructing the initial storage value of the memory comprises the following steps: and combining the initial storage values of the A-th registers of all the target shift register chains in the target shift register chain group from high bits to low bits, wherein the combined value is the initial storage value of the A-th storage unit of the memory. For example, the initial storage values of the 1 st register of each target shift register chain in the target shift register chain group are combined from high to low, and the combined value is the initial storage value of the 1 st storage unit of the memory, as shown in fig. 2, the initial storage values of the 1 st register (the initial storage values of the first row of registers) of the 4 shift register chains in the shift register chain group of fig. 2 are combined from high to low to obtain 4-bit data, and the combined 4-bit data is the initial storage value of the 1 st storage unit of the memory.
As an optional embodiment, the chip power consumption reduction design method further includes:
after the initial storage value of the memory is constructed, if the memory still has the residual capacity, the initial storage value of the storage unit under the residual capacity is set to 0.
Further, according to the method, after the initial storage value of the memory is constructed according to the initial storage value of each register in the target shift register chain group, whether the memory has residual capacity or not is judged, and if the memory still has residual capacity, the initial storage value of the storage unit under the residual capacity of the memory is set to be 0.
As an alternative embodiment, the memory is an SRAM;
replacing the target shift register chain set with the memory having the input/output signal, the enable signal, the address signal, and the stored initial value, the method comprising:
and replacing the target shift register chain group with the constructed input and output signals, the enable signal, the address signal and the SRAM storing the initial value.
Specifically, the Memory of the present application may be an SRAM (Static Random-Access Memory), and the SRAM can store data stored therein without a refresh circuit.
The application also provides a chip, and the chip is designed by adopting the steps of any one of the chip power consumption reduction design methods.
For the introduction of the chip provided in the present application, reference is made to the above embodiments of the power consumption reduction design method, which are not repeated herein.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A chip power consumption reduction design method is characterized by comprising the following steps:
determining a target shift register chain group to be replaced by a memory from a shift register chain group designed on a chip; each shift register chain in the same shift register chain group is respectively used for storing different bits in the same data;
correspondingly taking the digital input signal and the digital output signal of each target shift register chain in the target shift register chain group as the digital input signal and the digital output signal of the memory, and taking the enable signal of the target shift register chain group as the enable signal of the memory;
constructing an address signal of the memory according to the register chain depth of the target shift register chain group;
constructing a storage initial value of the memory according to the storage initial value of each register in the target shift register chain group;
and replacing the target shift register chain group by the memory which is well constructed with input and output signals, an enabling signal, an address signal and a storage initial value.
2. The chip power consumption reduction design method according to claim 1, wherein determining a target shift register chain group to be replaced by a memory from shift register chain groups designed on a chip comprises:
judging whether control signals of all registers in a first shift register chain set designed on a chip are the same or not and whether types of all registers in the first shift register chain set are the same or not; the first shift register chain group is any one shift register chain group;
if the judgment result is yes, determining the first shift register chain group as a target shift register chain group to be replaced by the pre-used memory;
and if the judgment result is negative, determining that the first shift register chain group is not the target shift register chain group to be replaced by the pre-used memory.
3. The method for designing chip power consumption reduction according to claim 2, wherein the step of judging whether the types of the registers in the first shift register chain group are the same comprises the steps of:
judging whether all registers in the first shift register chain group are synchronous registers or asynchronous registers;
if yes, determining that the types of the registers in the first shift register chain group are the same;
and if not, determining that the types of the registers in the first shift register chain group are not the same.
4. The chip power consumption reduction design method according to claim 1, wherein the corresponding digital input signals and digital output signals of each target shift register chain in the target shift register chain group as the digital input signals and digital output signals of the memory comprises:
obtaining data input signals DI [ N:0] of the memory according to digital input signals DI [0] to DI [ N ] of each target shift register chain in the target shift register chain group; DI [ M ] is the digital input signal of the M +1 th target shift register chain in the target shift register chain group; m is not less than 0 and not more than N, and M is an integer; n is the total number of the target shift register chains in the target shift register chain group-1;
obtaining data output signals DO [ N:0] of the memory according to digital output signals DO [0] to DO [ N ] of each target shift register chain in the target shift register chain group; and DO [ M ] is a digital output signal of an M +1 th target shift register chain in the target shift register chain group.
5. The chip power consumption reduction design method according to any one of claims 1 to 4, wherein constructing the address signal of the memory according to the register chain depth of the target shift register chain group comprises:
determining the number of storage units of the memory according to the register chain depth of the target shift register chain group; wherein the number of the storage units is more than or equal to the depth of the register chain;
and constructing an address signal for representing the address of the memory unit of the memory according to the number of the memory units of the memory.
6. The chip power consumption reduction design method according to claim 5, wherein the number of the storage units of the memory is determined according to the register chain depth of the target shift register chain group; according to the number of the memory cells of the memory, constructing an address signal for representing the address of the memory cell of the memory, comprising:
calculating a width-ceil (log) relation according to the preset address bit width2depth) calculating an address bit width of the memory to construct an address signal of the memory based on the address bit width; wherein ceil represents rounding up; depth is the register chain depth.
7. The chip power consumption reduction design method according to claim 5, wherein constructing the initial storage value of the memory according to the initial storage value of each register in the target shift register chain group comprises:
combining the initial storage values of the A-th registers of all the target shift register chains in the target shift register chain group from high bits to low bits to obtain the initial storage value of the A-th storage unit of the memory; wherein A is a positive integer.
8. The chip power consumption reduction design method of claim 7, further comprising:
after the initial storage value of the memory is constructed, if the memory still has residual capacity, the initial storage value of the storage unit under the residual capacity is set to be 0.
9. The chip power consumption reduction design method of claim 5, wherein the memory is an SRAM;
replacing the target shift register chain set with the memory having the input/output signal, the enable signal, the address signal, and the stored initial value, comprising:
and replacing the target shift register chain group with the SRAM with the input and output signals, the enable signal, the address signal and the stored initial value.
10. A chip, characterized in that the chip is designed by the steps of the chip power consumption reduction design method according to any one of claims 1 to 9.
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