CN112187278A - Sonar signal simulator delay control sonar signal simulation method and device - Google Patents
Sonar signal simulator delay control sonar signal simulation method and device Download PDFInfo
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Abstract
本发明涉及一种声纳信号模拟器延时控制的声纳信号模拟方法及装置，通过FPGA使用DDS的方式生成信号，充分的利用了FPGA上的运算资源，ARM只需要根据声纳信号模型计算频率控制字和相位控制字交由FPGA完成DDS。本发明将信号时延模块与串并转换模块结合，通过调整可变长度移位寄存器长度以调整时延大小，同时使用梯级组合型移位寄存器有效的降低了移位寄存器触发链组合逻辑所需要的资源。本发明通过FPGA的并行处理能力同步的产生多路不同时延的并行信号，避免了采用循环读取地址的方式导致系统效率降低。
The invention relates to a sonar signal simulation method and device for delay control of a sonar signal simulator. Signals are generated by using DDS through FPGA, and the computing resources on the FPGA are fully utilized, and the ARM only needs to calculate according to the sonar signal model. The frequency control word and the phase control word are handed over to the FPGA to complete the DDS. The invention combines the signal delay module with the serial-parallel conversion module, adjusts the delay size by adjusting the length of the variable-length shift register, and at the same time uses the ladder combination type shift register to effectively reduce the need for the shift register to trigger the chain combination logic Resources. The invention generates multiple parallel signals with different time delays synchronously through the parallel processing capability of the FPGA, thereby avoiding the reduction of system efficiency caused by the method of cyclically reading addresses.
Description
Technical Field
The invention belongs to the technical field of underwater acoustic signal processing and electronics, and relates to a sonar signal simulation method and device controlled by a sonar signal simulator in a delay mode.
Background
In the development and delivery of sonar equipment, extensive (lake) sea testing is required to effectively assess and verify the acoustic system and overall performance of the equipment. The test needs to consume a large amount of manpower, material resources and financial resources, the test period is long, the influences of factors such as sea conditions and climate are more, the test times are limited, and compared with a lake test or a sea test, the on-road semi-physical simulation system can not only save a large amount of manpower and material resources, but also provide system tests in the processes of scientific research, production and use.
In the field of sonar signal processing, most of the delay control methods of the existing sonar signal simulator are realized by adopting a DSP (digital signal processor), the methods are all serial working modes, even if multi-core parallel is adopted, an operation control mechanism is not perfect, and the working efficiency is not as good as that of an FPGA (field programmable gate array) for parallel operation. In the method implemented by using the FPGA, CN104022782B chinese, a digital multichannel analog signal generation method, proposes to implement the delay and the serial-parallel conversion in terms of digital signals by using a random register to cyclically read addresses, however, the method still has the possibility of improvement in terms of signal delay and resource occupation.
Disclosure of Invention
Technical problem to be solved
In order to avoid the defects of the prior art, the invention provides a sonar signal simulation method and a sonar signal simulation device based on delay control, which solve the problem that resources are occupied for realizing sonar signal simulation in an FPGA (field programmable gate array) at present.
Technical scheme
A sonar signal simulation method based on delay control of a sonar signal simulator is characterized by comprising the following steps: the multi-tap shift register composed of the array cascade combination type shift register respectively controls the data read-in and read-out of the shift register through the different phase clock, and comprises the following steps:
step 1: generating required single-period signal data through Matlab, and storing the signal data into a ROM of the FPGA chip; generating sonar signals from the monocycle signal data in the ROM by adopting a DDS method and storing the sonar signals into the FIFO;
step 2: the read-in logic is triggered by a clock, whether an EMPTY signal of the FIFO is in a low level or not is judged after the read-in logic is triggered, if the EMPTY signal is in the low level, data is read in, and the shift register reads in the data to perform shift operation;
and step 3: adding 1 to the data reading count every time data is read in, and after the data reading count is accumulated to the maximum value of the shift register, triggering the reading logic by a different-phase clock which is delayed by 90 degrees compared with a reading logic clock, and reading the data in the shift register by each channel according to different addresses after triggering;
address ADDR of read data of ith channeliThe calculation method is as follows:
ADDRi＝i*addr
addr is a time delay address difference value calculated by a sonar array model;
and 4, step 4: D/A digital-to-analog conversion is carried out on the data in the different address reading shift registers to obtain analog signals, and then noise addition, filtering and amplification are carried out to obtain analog underwater sound output signals.
By AMPnoiseAnd carrying out noise adding processing on the underwater sound output signal.
The AMPnoiseCalculating the SNR (signal to noise ratio), specifically using a value with the length of 8 bits to represent the noise amplitude, and calculating the ratio S/N of the signal amplitude to the noise amplitude: S/N ═ exp (SNR/20); 2. quantizing the reciprocal of S/N to 8bit data AMPnoiseMake AMPnoiseThe ratio to 8' b 11111111111 is approximately the reciprocal of S/N with an accuracy of 1/255.
Obtaining a delay address difference value addr calculated by the sonar array model:
frequency of the output signal
Wherein f isclkIs the clock frequency, N is the address bit number of ROM; FCW is frequency control word;
calculating the Doppler frequency fd2f v/c, where c is the speed of sound in water;
calculating frequency control words
Delay address difference addr ═ fsD sin (θ)/c, wherein fsEqual to the sampling frequency at which the DDS generates the signal.
The sound velocity c in the water is 1500 m/s.
A device for realizing the sonar signal simulation method of the sonar signal simulator time delay control is characterized by comprising a processor module, a digital programmable logic array module, a digital-to-analog conversion module and a low-pass filter; the input end of the processor module is connected with an upper computer, the output end of the processor module is connected with the digital programmable logic array module, and the digital programmable logic array module forms a plurality of channels to be connected with the corresponding digital-to-analog conversion modules; the digital-to-analog conversion modules are respectively connected with corresponding low-pass filters in sequence, and each low-pass filter is connected with a corresponding underwater acoustic transducer to form an underwater acoustic signal generation channel.
The processor module is an ARM processor integrated on the digital programmable logic array module.
The digital programmable logic array module adopts an FPGA.
Advantageous effects
According to the sonar signal simulation method and device based on delay control of the sonar signal simulator, signals are generated by using a DDS mode through the FPGA, operation resources on the FPGA are fully utilized, and ARM only needs to calculate frequency control words and phase control words according to a sonar signal model and then the DDS is completed by the FPGA.
The invention combines the signal time delay module and the serial-parallel conversion module, adjusts the time delay by adjusting the length of the variable-length shift register, and effectively reduces the resources required by the combined logic of the trigger chain of the shift register by using the step combination type shift register.
The invention synchronously generates a plurality of paths of parallel signals with different time delays through the parallel processing capacity of the FPGA, thereby avoiding the reduction of system efficiency caused by adopting a mode of circularly reading addresses.
Drawings
FIG. 1: the sonar signal simulation system forms a block diagram;
FIG. 2: a system work flow diagram;
FIG. 3: a schematic diagram of a delay module;
Detailed Description
The invention will now be further described with reference to the following examples and drawings:
as shown in fig. 1, the main components of the sonar signal simulation system are as follows: the device comprises a processor module, a digital programmable logic array module, a digital-to-analog conversion module and a low-pass filter, wherein the processor module is connected with an upper computer and is connected with the digital programmable logic array module; the digital programmable logic array module forms a plurality of channels to be connected with the corresponding digital-to-analog conversion module; the digital-to-analog conversion modules are respectively connected with the corresponding low-pass filters in sequence; each low-pass filter is connected with a corresponding underwater acoustic transducer to form an underwater acoustic signal generating channel.
The processor module is connected with an upper computer, and the upper computer sends parameters of the target model to the processor module; the output of the system is an electric signal generated after digital-to-analog conversion, low-pass filtering and amplification, and the underwater acoustic transducer can be driven by the electric signal.
The processor module is an ARM processor integrated on the digital programmable logic array module, generates required parameters according to parameters input from an upper computer through a bright spot model, and outputs the required parameters to the digital programmable logic array module, wherein the parameters comprise frequency control words, phase control words, time delay address difference values, noise amplitude control words and signal pulse width values.
The digital programmable logic array module is realized by an FPGA and is characterized in that the FPGA comprises a DDS module, a noise generation module, a serial-parallel conversion delay module, a signal noise adding module and a digital-to-analog conversion interface module; the direct digital frequency synthesizer module is connected with the serial-parallel conversion time delay module; the serial-parallel conversion time delay module generates a plurality of paths of time delay signals and is connected with a corresponding signal noise adding module channel; the noise generation module is connected with the signal noise adding module and generates multi-path noise; and each channel of the signal noise adding module is connected with a corresponding digital-to-analog conversion interface module.
The direct digital frequency synthesizer module is characterized in that required monocycle signal data are generated through Matlab and stored in a ROM of an FPGA chip; the direct digital frequency synthesizer module receives the phase control word and the frequency control word from the processor module, wherein the phase control word can adjust the phase of the output sine wave, the frequency control word can adjust the frequency of the output signal, and the direct digital frequency synthesizer module outputs the output signal to enter FIFO and waits for the serial-parallel conversion delay module to read.
The serial-parallel conversion time delay module is characterized in that a multi-tap shift register consisting of a plurality of groups of cascade combined shift registers respectively controls the data read-in and read-out of the shift register through a different phase clock, and the operation logic is as follows:
(1) the read-in logic is triggered by a clock, whether an EMPTY signal of the FIFO is in a low level or not is judged after the read-in logic is triggered, if the EMPTY signal is in the low level, data is read in, and the read-in data is subjected to shift operation;
(2) adding 1 to the data reading count every time data is read in, and reading out the enable when the data reading count is accumulated to the maximum value of the shift register;
(3) the read-out logic is triggered by a different phase clock which delays 90 degrees compared with the read-in logic clock, and after triggering, each channel reads data in the shift register according to different addresses;
(4) address ADDR of read data of ith channeliThe calculation method is as follows:
ADDRi＝i*n
and n is a time delay address difference value input from the processor module and is calculated by the bright spot target model.
The upper computer can send model parameters to the system through the Ethernet, wherein the model parameters comprise signal frequency f, signal-to-noise ratio SNR, signal pulse width T, target azimuth theta, target radial velocity v, array element number N and array element spacing d; after calculation by the processor module, obtaining a frequency control word, a phase control word, a time delay address difference value, a signal amplitude control word, a noise amplitude control word and a signal pulse width value, and sending the parameters to the digital programmable logic array module; in the digital programmable logic array module, the following functions are realized according to the data transmitted by the processor module:
(1) realizing direct digital frequency synthesis according to the frequency control word, the phase control word and the signal pulse width value;
(2) realizing time delay and serial-parallel conversion functions according to the time delay address difference;
(3) realizing a signal noise adding function according to the noise amplitude control word;
then, data are sent to the digital-to-analog conversion module through the digital-to-analog conversion interface; the signal is converted into an analog signal through digital-to-analog conversion and then passes through a low-pass filter to obtain an analog sonar signal.
Further, as shown in FIG. 2, the frequency control word is calculated in relation to the frequency of the generated signal and the depth of the FPGA chip ROM, the frequency f of the output signaloutThe calculation formula is as follows:
wherein f isclkIs the clock frequency, N is the address bit number of ROM; FCW is a frequency control word. It can be seen that the greater the ROM depth used here, the greater the accuracy of the frequency of the signal that can be generated. Meanwhile, the calculation of the frequency control word also needs to consider the Doppler frequency. The specific calculation process is as follows:
(1) calculating the Doppler frequency fd
fd＝2f*v/c
Where c is the speed of sound in water, typically 1500 m/s.
(2) Calculating a frequency control word FCW
Further, the use of the phase control word for control may also affect the DDS address lookup, typically the phase control word is 0.
Furthermore, the value of the delay address difference addr is the sampling frequency f of the signal generated by the array element spacing, the target azimuth angle and the DDSsThe decision, in the processor module, is calculated as follows:
addr＝fs*d*sin(θ)/c
wherein f issEqual to DDSThe sampling frequency of the signal.
Further, a noise amplitude control word AMPnoiseCalculating the SNR by using a length of 8bit to represent the noise amplitude, and the method comprises the following steps:
(1) calculating the ratio S/N of the signal amplitude and the noise amplitude
S/N＝exp(SNR/20)
(2) Quantizing the reciprocal of S/N to 8bit data AMPnoiseMake AMPnoiseThe ratio to 8' b 11111111111 is approximately the reciprocal of S/N with an accuracy of 1/255.
DDS: further, the signal pulse width value NTCalculated from the pulse width T of the signal, and having a value NT＝T*fs。
The FPGA has a DDS module, a noise generation module, a serial-parallel conversion delay module, a signal noise adding module and a digital-to-analog conversion interface module, and the specific frame and flow are shown in FIG. 1.
The DDS module receives the frequency control word and the phase control word, generates a query table address by matching with the phase accumulation register, and then generates data in an address query mode, wherein the frequency stepping precision delta f and the phase stepping precision delta p of the DDS module are calculated according to the following formula:
Δp＝(2π/2N)
therein, 2NThe sample depth at which the desired monocycle signal data is generated for Matlab.
The noise generation module also generates noise based on a method of reading data stored in the ROM beforehand. The specific implementation is to use MATLAB to generate a noise signal that obeys a certain mean and variance. The data is then stored in the FPGA for playback to generate white gaussian noise.
As shown in fig. 3, the serial-to-parallel conversion delay module uses a multi-tap shift register based on RAM, where 1bit data is taken as an example, and is constrained to form a step combination type shift register, and simultaneously, is constrained to logically synthesize the output of the shift register into a single register, and specifically operates as follows:
(1) first, the maximum delay tau required by the project needs to be evaluatedmaxAnd a sampling frequency fsThe required set of shift register lengths M should satisfy:
M＞τmax*fs
M＝2n+1-1
wherein n is the number of steps;
(2) a step-and-combination shift register is created, which is characterized by a 2: 1, controlling multiplexers, wherein each multiplexer has n independent control bits, and the n control bits are in an exponential relationship; and is a cascade composed of shift registers of different lengths, the 0 th stage is composed of 20-1 flip-flops, and the 1 st stage is composed of 2 flip-flops12-th flip-flop chain, stage 2 consisting of 224 flip-flop chains, the nth stage consisting of 2nAnd a trigger is linked. In the step-combination type structure, it is not necessary to control the input/output of each flip-flop, and a length continuous change with a resolution of 1 can be realized by controlling the input/output of each step by the multiplexer control bit.
(3) Because the length of the cascade combination type shift register is adjustable, the output signal of the ith array element can be obtained as the output of the (i-1) th group of cascade combination type shift register in a mode of connecting N-1 cascade combination type shift registers in series in the invention.
(4) If a large amount of trigger resources are consumed by using a trigger to build the shift register, the problem can be effectively avoided by using the shift register based on the RAM, and meanwhile, the minimum length of the shift register based on the RAM is limited to 3, in the example, the 0 th stage and the 1 st stage of the cascade combination type shift register are formed by using the trigger; the 0 th stage and the 1 st stage can be omitted under the condition that the requirement of delay precision is not high.
Furthermore, when the shift register is operated, the different-phase clocks are adopted to respectively perform read-write operation, and the specific logic is as follows:
(1) the read-in logic is triggered by a clock, whether an EMPTY signal of the FIFO is in a low level or not is judged after the read-in logic is triggered, if the EMPTY signal is in the low level, data is read in, and the read-in data is subjected to shift operation;
(2) adding 1 to the data reading count every time data is read in, and reading out the enable when the data reading count is accumulated to the maximum value of the shift register;
(3) the read-out logic is triggered by a different phase clock which delays 90 degrees compared with the read-in logic clock, and after triggering, each channel reads data in the shift register according to different addresses;
(4) address ADDR of read data of ith channeliThe calculation method is as follows:
ADDRi＝i*n
and n is a time delay address difference value input from the processor module and is calculated by the bright spot target model. In practice, the read address is used to control the length of the variable length shift register.
The signal noise adding module adds noise to the signal of each channel, because the signal noise adding process may cause carry, the processing method is to carry out left shift to the data after adding noise and abandon the last bit, so as to ensure that the data can not overflow.
The low-pass filter should ensure that the bandwidth of the pass band is large enough, because the signal after the digital-to-analog conversion contains the required white noise, which also puts a certain requirement on the noise control of the digital-to-analog conversion module, and it needs to ensure that the noise generated by the digital-to-analog conversion does not affect the signal-to-noise ratio.
In the application example, the sonar signal simulation system is realized based on an SOC FPGA, and currently, many FPGAs integrate a powerful ARM processor and a large number of FPGA resources, and under the control of the ARM, the FPGA can liberate a large number of resources for calculation, and at the same time, a single board can complete the functions from receiving parameters to generating multi-path digital signals.
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