CN117095731B - Test equipment and computing equipment - Google Patents
Test equipment and computing equipment Download PDFInfo
- Publication number
- CN117095731B CN117095731B CN202311309491.3A CN202311309491A CN117095731B CN 117095731 B CN117095731 B CN 117095731B CN 202311309491 A CN202311309491 A CN 202311309491A CN 117095731 B CN117095731 B CN 117095731B
- Authority
- CN
- China
- Prior art keywords
- memory
- test
- comparator
- data
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
The embodiment of the specification provides a test device and a computing device, and the comparator and the memory are packaged independently, so that the memory does not need to consider factors such as device manufacturing process and technology compatible with the comparator when being manufactured, the wafer size required by the memory is reduced, and the cost of the memory is reduced. Correspondingly, the manufacturing process and the process of a device compatible with a memory are not required to be considered in the preparation of the comparator, so that the overall size of the comparator is reduced, the overall size of the test equipment is reduced on the basis that the test function can be realized, and the equipment cost is reduced.
Description
Technical Field
The present disclosure relates to the field of computer application, and in particular, to a memory testing technique in the field of computer application, and more particularly, to a testing apparatus and a computing apparatus.
Background
Memory is typically used to provide storage space for data, and may provide data reading and storage functions. The memory is an important component of a system on Chip (SoC) and other systems, and in the system on Chip, the memory is a key component for storing instructions and related data, so that ensuring that the memory is in a normal working state has important significance for normal operation of the system.
At present, the equipment for executing the test function has the problems of larger size and higher cost of the required wafer.
Disclosure of Invention
The embodiment of the specification provides test equipment and computing equipment, and the problems that the wafer size required by the equipment is larger and the cost is higher due to factors such as device manufacturing procedures and processes which are compatible with a comparator when the memory is designed and manufactured are avoided by the mode that the comparator and the memory are packaged independently.
In order to achieve the technical purpose, the embodiment of the specification provides the following technical scheme:
in a first aspect, an embodiment of the present specification provides a test apparatus comprising: a comparator and a memory packaged independently of each other; the first input end of the comparator is connected with the output end of the memory, and the second input end of the comparator is used for receiving test input data; the input end of the memory is used for receiving the test input data; wherein,
the memory is used for receiving the test input data and outputting test output data to the comparator;
the comparator is used for receiving the test input data and the test output data and performing memory self-test on the memory according to the test input data and the test output data of the memory.
In the embodiment, the comparator and the memory are packaged independently, so that the memory does not need to consider factors such as a device manufacturing process and a technology compatible with the comparator when being manufactured, the wafer size required by the memory is reduced, and the cost of the memory is reduced. Correspondingly, the manufacturing process and the process of a device compatible with a memory are not required to be considered in the preparation of the comparator, so that the overall size of the comparator is reduced, the overall size of the test equipment is reduced on the basis that the test function can be realized, and the equipment cost is reduced.
In some embodiments, the test apparatus further comprises: a selector, the comparator and the memory being packaged independently of each other;
the selector includes a test mode and a test path, the selector configured to: in the test mode, data received through the test path is transferred to the memory connected to the selector.
By setting the selector, the occupied pins of the memory can be reduced, and by setting the mode of the selector, different data can be selected to be input into the memory, so that the hardware requirement on the memory is reduced.
In some embodiments, the selector further comprises: a working mode and a working path;
the selector is further configured to switch to the test mode when the received enabling signal is in a first state, and switch to the working mode when the received enabling signal is in a second state;
in the operating mode, data received through the operating path is transferred to the memory connected to the selector.
In the embodiment, the purpose of transmitting the test input data or the normal working data to the memory is realized by the selector in the test mode or not, so that the input of different data can be realized under the condition of occupying one pin of the memory, the data input requirement of the memory in the test and normal working is met, and the hardware requirement of the memory is reduced.
In some embodiments, the selector further comprises: an enable signal input, a first signal input, a second signal input, and a signal output; wherein,
the enabling signal input end is used for receiving the enabling signal;
the signal output end is connected with the input end of the memory;
The first signal input end to the signal output end form the test path;
the second signal input end to the signal output end form the working channel.
Different signal input ends are used as input ends of input data of the test path and the working path, so that interference among different data is reduced.
In some embodiments, the comparator is further to: and outputting a test result of performing memory self-test on the memory.
The test result output by the comparator can be transmitted to the memory controller, so that the memory controller can learn the test result of the memory and then adopt a corresponding control strategy.
In some embodiments, a first input of the comparator is connected to an output of the memory for receiving the test output data;
the second input end of the comparator is connected with the output end of the memory controller and is used for receiving the test input data;
the output end of the comparator is used for being connected with a memory controller, and the test result is transmitted to the memory controller through the output end of the comparator.
In the embodiment, the data is received and output through multiple ports, so that the possible abnormality caused by the fact that the comparator receives multiple data through a single port can be reduced, and the robustness of the device is improved.
In some embodiments, the comparator is further configured to output test information according to the test result; the test information is used to indicate whether the memory is normal.
In some embodiments, the test information carries an identity of the memory;
the test information includes: a first value and a second value; the first value is used for identifying that the memory indicated by the identity of the memory is abnormal, and the second value is used for identifying that the memory indicated by the identity of the memory is normal.
The location of the abnormal memory can be realized through the identity mark carried by the test information, which is beneficial to the location and repair of the problem.
In some embodiments, the test apparatus further comprises: a circuit board;
the circuit board comprises an interconnection line, the circuit board is used for bearing the comparator and the memory, and the comparator and the memory are electrically connected through the interconnection line.
The comparator and the memory are carried by the circuit board, and the comparator and the memory are connected by the interconnection line on the circuit board, so that the hardware position can be planned and laid out, and good communication among all the hardware can be ensured.
In a second aspect, embodiments of the present disclosure provide an electronic device, including: a memory controller and a plurality of test devices, the test devices comprising: a comparator and a memory packaged independently of each other;
the memory controller is used for responding to a test instruction and controlling a plurality of test devices to perform memory self-test on the memories respectively included;
the memory self-test includes: the comparator tests the memory according to the test input data of the memory and the test output data of the memory.
In some embodiments, the plurality of test devices are divided into a plurality of test device groups, each test device group in the plurality of test device groups includes at least one test device, the number of memory controllers is a plurality of memory controllers, and any one of the plurality of memory controllers is respectively connected with one test device group in a communication manner, and physical characteristics of memories included in the test device groups are the same.
According to the technical scheme, the test equipment and the computing equipment provided by the embodiment of the specification enable the memory to be prepared without considering factors such as device manufacturing process and technology compatible with the comparator by means of packaging the comparator and the memory independently, and are beneficial to reducing the wafer size required by the memory, so that the cost of the memory is reduced. Correspondingly, the manufacturing process and the process of a device compatible with a memory are not required to be considered in the preparation of the comparator, so that the overall size of the comparator is reduced, the overall size of the test equipment is reduced on the basis that the test function can be realized, and the equipment cost is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present description or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present description, and that other drawings may be obtained according to the drawings provided without inventive effort to a person skilled in the art.
Fig. 1 is a system architecture diagram of a possible application scenario provided in an embodiment of the present disclosure.
Fig. 2 is a system architecture diagram of another possible application scenario provided in one embodiment of the present disclosure.
Fig. 3 is a schematic flow chart of a testing method according to an embodiment of the present disclosure.
Fig. 4 is a schematic structural diagram of a chain scanning module according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram illustrating a connection relationship between a memory controller and a memory self-test module according to an embodiment of the present disclosure.
Fig. 6 is a schematic structural diagram of a system according to an embodiment of the present disclosure.
Fig. 7 is a schematic structural diagram of another system according to an embodiment of the present disclosure.
Fig. 8 is a schematic structural diagram of yet another system according to an embodiment of the present disclosure.
Fig. 9 is a schematic structural diagram of a test apparatus according to an embodiment of the present disclosure.
Fig. 10 is a schematic structural diagram of another test apparatus according to an embodiment of the present disclosure.
Fig. 11 is a schematic structural view of still another test apparatus according to an embodiment of the present disclosure.
Fig. 12 is a schematic structural diagram of still another test apparatus according to an embodiment of the present disclosure.
Detailed Description
Unless defined otherwise, technical or scientific terms used in the embodiments of the present specification should be given the ordinary meaning as understood by one of ordinary skill in the art to which the present specification belongs. The terms "first," "second," and the like, as used in the embodiments of the present disclosure, do not denote any order, quantity, or importance, but rather are used to avoid intermixing of the components.
Throughout the specification, unless the context requires otherwise, the word "plurality" means "at least two", and the word "comprising" is to be construed as open, inclusive meaning, i.e. as "comprising, but not limited to. In the description of the present specification, the terms "one embodiment," "some embodiments," "example embodiments," "examples," "particular examples," or "some examples," etc., are intended to indicate that a particular feature, structure, material, or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present specification. The schematic representations of the above terms do not necessarily refer to the same embodiment or example.
The technical solutions of the embodiments of the present specification will be clearly and completely described below with reference to the drawings in the embodiments of the present specification, and it is apparent that the described embodiments are only some embodiments of the present specification, not all embodiments. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are intended to be within the scope of the present disclosure.
The memory and the register are important components of a system on Chip (SoC) and other systems, in the SoC, the memory is a key component for storing instructions and related data, the register is a high-speed storage unit for temporarily storing and accessing data, and the register has extremely fast read-write speed and can provide efficient data access and processing capability.
In conclusion, ensuring that the memory and the register are in normal working states has important significance for normal operation of the system. Therefore, in a system having an arithmetic capability such as a plurality of systems on a chip, a status check of a register and a memory is generally checked by a system test.
During testing and use of systems with computing and memory capabilities, such as systems on chip, it may be necessary to test the memory and registers within the system to ensure that the overall function of the system is normal. For example, in a test scenario before the system leaves the factory or in a self-checking scenario after the system is restarted, the memories and registers in the system can be tested to ensure that the functions of the memories and registers are normal.
Taking a system on chip as an example, before the system leaves a factory, the memory and the register of the system can be respectively tested in a needle test mode through ATE (Automatic TestEquipment ), whether the memory and the register are normal or not is judged according to a test result, and if the memory or the register is abnormal, defective products can be intercepted in time to leave the factory. After the system on chip is put into use, the memory and the register may be abnormal in the use process, so that the memory and the register in the system can be self-checked when the system is started or restarted, whether the memory and the register are normal or not is judged according to a self-check result, if the memory or the register is abnormal, the system can be wrongly reported or prevented from being started, and the abnormal operation of the system caused by the abnormal use of the memory or the register is avoided.
As can be seen from the above description, testing the memory or register of the system is significant in ensuring the normal performance of the system. However, the test for the memory and the register at present requires the corresponding test hardware to be respectively arranged for the test logic of the memory and the register, and has the problem of higher cost.
In order to solve the problem, the inventor finds that the time-sharing test of the memory and the register can be realized by multiplexing part of hardware through the test logic of the memory and the register, so that the hardware resources can be saved in the test process, and the test cost can be reduced.
Furthermore, the inventor found through research that, for the memory self-test scenario, if the comparator in the test device is integrated in the memory, in some cases, the memory may be designed and manufactured, and the device manufacturing process, the process and other factors of the comparator are required to be compatible, which results in larger wafer size and higher cost for the test device. In order to avoid the problem, the comparator and the memory are packaged independently, so that the memory does not need to consider factors such as device manufacturing process and technology compatible with the comparator when being manufactured, the wafer size required by the memory is reduced, and the cost of the memory is reduced. Correspondingly, the manufacturing process and the process of a device compatible with a memory are not required to be considered in the preparation of the comparator, so that the overall size of the comparator is reduced, the overall size of the test equipment is reduced on the basis that the test function can be realized, and the equipment cost is reduced.
Based on the above-described concept, the present embodiment provides a test method, and the test method provided by the present embodiment will be exemplarily described below with reference to the accompanying drawings.
Referring to fig. 1, fig. 1 illustrates a possible application scenario of the test apparatus and the corresponding test method provided in the embodiments of the present disclosure, where the application scenario may specifically be a test scenario before the system 10 leaves the factory, and the ATE20 establishes a communication connection with the microcontroller 11 inside the system 10 through a probe, and the microcontroller 11 establishes a communication connection with the memory self-test module 12 and the chain scan module 13 respectively. ATE20 implements time-sharing testing of memory self-test module 12 and chain scan module 13 by controlling the mode of microcontroller 11. The memory self-test module 12 may include a memory controller 121 and a test unit 122 in communication with the memory controller 121. The test unit comprises a memory to be tested.
Referring to fig. 2, fig. 2 shows another possible application scenario of the test apparatus and the corresponding test method provided in the embodiment of the present disclosure, where the application scenario may specifically be a startup scenario after the system 10 is put into use, where the microcontroller 11 in the system 10 establishes a communication connection with the external controller 31 in the computing apparatus 30, and where the microcontroller 11 establishes a communication connection with the memory self-test module 12 and the chain scan module 13, respectively. The external controller 31 can realize the time-sharing test of the memory self-test module 12 and the chain scan module 13 by controlling the mode of the microcontroller 11. In some embodiments, ATE20 of FIG. 1 and external controller 31 of FIG. 2 may both be referred to as external controllers. The system 10 in fig. 1 and 2 may be a system on a chip or the like, which is provided with a microcontroller 11, a memory self-test module 12 and a chain scan module 13. In fig. 1 and 2, the memory self-test module 12 may include a plurality of memories to be tested, and the chain scan module 13 may include a DFT (Design for Testability, design testability) scan chain, which may include a plurality of registers connected in series in sequence.
Referring to fig. 4, the DFT scan chain 131 in the chain scan module 13 may refer to fig. 4, in the chain scan module 13, at least one DFT scan chain 131 may be included, and in the DFT scan chain 131, a series connection manner of registers may include: the SI pin of the first register is used for receiving data input to the DFT scan chain 131 during the scan test of the chain, and the Q pin of the first register is connected with the SI pin of the second register, so that the data output by the first register through the Q pin is input from the SI pin as the input data of the second register; for other registers, the connection relation between the Q pin of the last register and the SI pin of the next register is satisfied, and the Q pin of the last register is used for connecting a memory controller. For registers, the D (Data) pin is the input pin for inputting Data into the register. The SI (Serial In) pin is also an input pin, and is used In the Serial input mode. The SI pin is used to input data into the register in a bit-by-bit sequence, with the input data bits being shifted into the register during each clock pulse. The SE (Serial Enable) pin is an input pin, which is used in serial input mode. The SE pin is used to control the loading time of the input data, and when the SE pin is high, the input data is loaded into the register. The Q pin is an output pin for outputting data stored in the register. Through the Q pin, the data in the register can be read. In addition, the register includes a clock pin for receiving the clock signal CLK.
Of course, in some possible application scenarios, the memory self-test module 12 or the chain scan module 13 may not be included, that is, in some application scenarios, the memory self-test may be performed only for the memory in the memory self-test module 12, or the chain scan test may be performed only for the register in the chain scan module 13, which is not limited in this specification.
Taking the microcontroller 11 shown in fig. 1 or fig. 2 as an example, the microcontroller 11 is respectively connected with a chain scanning module 13 and a memory self-test module 12 in a communication manner, the chain scanning module 13 comprises a design testability DFT scanning chain, the microcontroller 11 is connected with the DFT scanning chain in a communication manner, and the DFT scanning chain comprises a plurality of registers which are sequentially connected in series; the memory self-test module 12 includes a plurality of memories; the embodiment of the specification provides a testing method, as shown in fig. 3, which includes:
s301: and responding to a first configuration instruction, and enabling the memory self-test module to perform memory self-test on the memory in a memory test mode.
The first configuration instruction may be an instruction sent by the external controller to the microcontroller, where the instruction may configure the microcontroller in a memory test mode and enable the memory self-test module to perform a memory self-test on the memory.
S302: and responding to a second configuration instruction, and performing chain scanning test on the DFT scanning chain of the chain scanning module in a chain scanning mode.
Similarly, the second configuration instruction may be an instruction sent by the external controller 31 to the microcontroller 11, where the instruction may configure the microcontroller 11 in the chain scan mode and perform the chain scan test on the DFT scan chain 131 of the chain scan module 13. In this way, the microcontroller 11 is configured into different modes through different configuration instructions, so that the DFT scan chain 131 of the chain scan module 13 is respectively subjected to the chain scan test and the memory self-test module 12 is enabled to perform the memory self-test on the memory under different modes, the purposes of performing the chain scan and the memory self-test under different modes by the multiplexing microcontroller 11 are achieved, hardware resources required in the test process are saved, and the test cost is reduced.
The memory in the memory self-test module 12 may be used, for example, as a memory of a system, to provide various storage capabilities for the system. In some embodiments, the memory may be, for example, SRAM (Static Random Access Memory ) or DRAM (Dynamic Random Access Memory, dynamic random access memory), where the specific type of the memory is not limited in this specification, and the specific situation is specific.
The DFT scan chain 131 in the chain scan module 13 may refer to fig. 4, in the chain scan module 13, at least one DFT scan chain 131 may be included, and in the DFT scan chain 131, a concatenation manner of registers may include: the SI pin of the first register is used for receiving data input to the DFT scan chain 131 during the scan test of the chain, and the Q pin of the first register is connected with the SI pin of the second register, so that the data output by the first register through the Q pin is input from the SI pin as the input data of the second register; for other registers, the connection relation between the Q pin of the last register and the SI pin of the next register is satisfied, and the Q pin of the last register is used for connecting a memory controller. For registers, the D (Data) pin is the input pin for inputting Data into the register. The SI (Serial In) pin is also an input pin, and is used In the Serial input mode. The SI pin is used to input data into the register in a bit-by-bit sequence, with the input data bits being shifted into the register during each clock pulse. The SE (Serial Enable) pin is an input pin, which is used in serial input mode. The SE pin is used to control the loading time of the input data, and when the SE pin is high, the input data is loaded into the register. The Q pin is an output pin for outputting data stored in the register. Through the Q pin, the data in the register can be read. In addition, the register includes a clock pin for receiving the clock signal CLK.
To improve the efficiency of the memory self-test, in some embodiments, referring to fig. 5, the memory self-test module 12 further includes: a memory controller 121 and a plurality of comparators 125, one of the memories 124 and one of the comparators 125 form a test unit 122, a first input terminal In1 of the comparator 125 is connected to an output terminal O1 of the memory 124, and a second input terminal In2 of the comparator 125 is configured to receive test input data output by the memory controller 121; an input I1 of the memory 124 is for receiving the test input data;
enabling the memory self-test module 12 to perform a memory self-test includes:
sending a test instruction to the memory controller 121; the test instruction is configured to instruct the memory controller 121 to control the plurality of test units 122 to perform a memory self-test on the respective included memories 124;
the memory self-test includes: the comparator 125 tests the memory 124 based on the test input data and the test output data.
In fig. 5, a schematic diagram of the connection relationship between the memory controller 121 and the plurality of test units 122 is shown, and a schematic diagram of the connection relationship between the memory controller 121 and the memory 124 and the comparator 125 in the test units 122 in a dashed line frame is shown. In this embodiment, the single memory controller 121 may be in communication connection with the plurality of test units 122, so in the process of memory self-test, the microcontroller 11 may instruct the memory controller 121 to control the plurality of test units 122 to perform memory self-test on the respective memories 124 through the test instruction, thereby achieving the purpose of performing memory self-test on the plurality of memories 124 through the single memory controller 121, and without separately arranging one memory controller 121 for each memory 124, which is beneficial to reducing resource occupation, cost and influence on path delay.
In one possible embodiment, still referring to fig. 5, the memory self-test specifically includes: the comparator 125 compares the test input data of the memory 124 with the test output data of the memory 124 and outputs test information according to the comparison result; the test information is used to indicate whether the memory 124 is normal.
In this embodiment, the test information can be used to determine whether the state of the memory 124 is normal, so as to determine the test result of the memory self-test of the memory 124.
To enable locating of the abnormal memory 124, in an alternative embodiment, the test information carries an identity of the memory 124;
the test information includes: a first value and a second value; the first value is used to identify that the memory 124 indicated by the identity of the memory 124 is abnormal, and the second value is used to identify that the memory 124 indicated by the identity of the memory 124 is normal.
In this embodiment, since the test information carries the identity of the memory 124, it can be determined whether the specific memory 124 is abnormal according to the specific value of the test information. For example, still referring to fig. 5, the mb_fail signal in fig. 5 represents the test information, and the distinction between the different memories 124 may be achieved by the signal name of the mb_fail signal, i.e. the signal name of the mb_fail signal is used as the identity of the memory 124. Specifically, for example, the identity of the memory 0 may be mb_fail0, and the identity of the memory 1 may be mb_fail1, so that when the value of mb_fail0 is the first value, the state of the memory 0 is abnormal, and when the value of mb_fail0 is the second value, the state of the memory 0 is normal, so that the positioning of the abnormal memory 124 may be implemented, which is beneficial to positioning and repairing the problem after the abnormal memory 124 is found.
In order to implement self-test management of the memories 124 with which the memory controller 121 is communicatively connected, in one embodiment, referring to fig. 6, the test instruction is further configured to instruct the memory controller 121 to receive the test information output by the plurality of test units 122, and return an error message when any one of the test information includes the first value;
the error message is used to indicate that at least one of the plurality of test units 122 includes an abnormal memory 124;
the test method further comprises the following steps:
and outputting the error information or terminating the starting process when the error information is received.
In this embodiment, when any one of the test units 122 connected to the memory controller 121 has an abnormal memory 124, the memory controller 121 sends an error message to the microcontroller 11 to alert the microcontroller 11 that the memory 124 is abnormal, so that the microcontroller 11 outputs the error message in time or terminates the system start-up process.
In fig. 6, each test unit 122 sends test information indicating whether the memory 124 is abnormal, i.e. mb_fail0 and mb_fail1 … … mb_failn, to the memory controller 121, and the memory controller 121 determines whether any one or more memories 124 are abnormal according to the values of the test information. For example, when the value of mb_fail0 is the first value, it indicates that there is an abnormality in the memory 124 represented by mb_fail0; when the values of mb_fail0 and mb_fail1 are both the first values, it indicates that the memory 124 represented by mb_fail0 and mb_fail1 is abnormal; in these cases, the memory controller 121 sends an error message fail to the microcontroller 11, and alerts the microcontroller 11 of the presence of an abnormal memory 124.
In addition to determining whether an abnormal memory 124 exists in the plurality of test units 122 based on the test information, the abnormal memory 124 may be located based on the test information to facilitate rapid location and repair of the abnormal memory 124. For example, in one embodiment, referring still to fig. 6, the test instruction is further configured to instruct the memory controller 121 to receive the test information output by the plurality of test units 122;
the test method further comprises the following steps:
outputting an error positioning instruction to the memory controller 121, where the error positioning instruction is configured to instruct the memory controller 121 to output abnormal test information, and the value of the abnormal test information is the first value;
and receiving the abnormal test information, positioning an abnormal memory 124 according to the abnormal test information, wherein the abnormal memory 124 is a memory 124 indicated by the identity of the memory 124 carried by the abnormal test information.
In this embodiment, the microcontroller 11 may instruct the memory controller 121 to output the abnormal test information by sending an error positioning instruction to the memory controller 121, so that the microcontroller 11 may position the abnormal memory 124 according to the abnormal test information, thereby implementing the positioning of the abnormal memory 124, and being beneficial to helping the repair of the abnormal memory 124. For example, still taking the system shown in fig. 6 as an example, when the value of mb_fail0 is the first value, which indicates that there is an abnormality in the memory 124 represented by mb_fail0, the memory controller 121 may return mb_fail0 to the microcontroller 11, so that the microcontroller 11 determines the location of the abnormal memory 124 according to mb_fail0; also, for example, when the values of mb_fail0 and mb_fail1 are both the first values, indicating that there is an abnormality in the memory 124 represented by mb_fail0 and mb_fail1, the memory controller 121 may return mb_fail0 and mb_fail1 as abnormality test information to the microcontroller 11, so that the microcontroller 11 determines the location of the abnormal memory 124 according to mb_fail0 and mb_fail1.
In order to ensure reliable operation of the system 10, in one embodiment of the present disclosure, referring to fig. 7, the number of the memory controllers 121 is plural, the plurality of test units 122 is divided into a plurality of sub-test unit groups, each of the plurality of sub-test unit groups includes at least one test unit 122, and any one of the plurality of memory controllers 121 is respectively connected to one of the sub-test unit groups in a communication manner, and physical characteristics of the memories 124 included in the sub-test unit groups are the same.
In general, the physical characteristics of different memories 124 may be different, so as to ensure that the physical characteristics of the memories 124 in the test units 122 connected to the same memory controller 121 are the same, so as to avoid the problem of data transmission errors that may occur between the memory controller 121 and the incompatible memories 124. In some embodiments, the physical characteristics of the memory 124 included in the subtest unit 122 are matched with the memory controller 121 with which the communication connection is established, so that a situation of data transmission errors between the memory controller 121 and the memory 124 can be avoided, which is beneficial to improving the operation reliability of the system 10.
The physical characteristics of the memory 124 may include electrical and timing characteristics of the memory 124, such as at least one of supply voltage, clock rate, and data bandwidth, and the like, while the external appearance of the physical characteristics of the memory 124 typically includes the number of interfaces by which the physical characteristics of the memory 124 may be quickly and easily determined. The number of interfaces may include the number of interfaces for transmitting clock signals, the number of interfaces for transmitting data, and so on. In some implementations, the physical characteristics may also include an interface type. The present specification is not limited thereto.
In the case where there are multiple memory controllers 121 in the system 10, each memory controller 121 establishes a communication connection with at least one test unit 122, in order to improve the self-test efficiency of the memory, in one embodiment of the present disclosure, still referring to fig. 7, the test instruction carries attribute information corresponding to the memory 124, where the attribute information corresponding to the memory 124 is used to indicate the physical characteristics of the memory 124;
the sending a test instruction to the memory controller 121 includes:
the test instruction is sent to a plurality of target memory controllers 121, where the plurality of target memory controllers 121 are respectively connected to a plurality of target sub-test units, and physical properties of memories 124 included in the plurality of target sub-test units are the same.
In this embodiment, the memory 124 in the target self-test unit 122 group connected to the multiple target memory controllers 121 can be subjected to the memory self-test at the same time, which is beneficial to shortening the time required for the memory self-test and improving the test efficiency. Taking fig. 7 as an example, assuming that physical characteristics of the memories 124 included in the sub-test unit group 0 and the sub-test unit group 1 are the same, and that physical characteristics of the memories 124 included in the sub-test unit group N and the sub-test unit group 0 are different, in this embodiment, the memory controller 121 having the communication connection with the sub-test unit group 0 and the sub-test unit group 1 may be used as the target memory controller 121, and a test instruction may be sent to the two target memory controllers 121, so that the two target memory controllers 121 may simultaneously start the self-test of the memories of the sub-test unit group 0 and the sub-test unit group 1, thereby shortening the time consumption required for the test and improving the test efficiency.
In order to reduce the pin occupation of the memory 124, in one embodiment of the present description, still referring to fig. 5, the test unit 122 further includes a selector 123, the selector 123 including a test path;
the test instruction is specifically used for: instruct the memory controller 121 to control the selector 123 to enter a test mode in which the selector 123 is configured to transmit data received by the test path to the memory 124 connected to the selector 123; transmitting the test input data to the memory 124 through a test path of the selector 123; test results of the comparator 125 testing the memory 124 according to the test input data and the test output data are obtained.
In this embodiment, the purpose of transmitting the test input data or the normal operation data to the memory 124 is achieved by the selector 123 being in the test mode, so that the input of different data can be achieved under the condition of occupying one pin of the memory 124, the data input requirement of the memory 124 during the test and the normal operation is satisfied, and the hardware requirement of the memory 124 is reduced. In fig. 5, CLK denotes a clock signal, rst denotes a reset signal, mbist_en denotes an enable signal, the test instruction may include the enable signal, and the selector 123 enters a test mode upon receiving the enable signal. mb_data_in represents a test input signal, and data_in represents a data signal when the memory 124 is operating normally.
For a particularly viable process of memory self-test, one embodiment of the present specification provides an exemplary test process, referring to fig. 8, in which the external controller 31 is connected to the microcontroller 11 via a JTAG (Joint Test Action Group, joint test workgroup) bus, which may include:
s1, given a reference clock clk_ref of the microcontroller 11, then releasing the por_n reset signal, and after the por_n reset signal is released, the microcontroller 11 enters a debugging mode. The por_n reset signal may be used to control the generation of debug mode and the beginning and end of the test procedure.
S2, the external controller 31 configures a hardware debug module inside the microcontroller 11 through the JTAG bus, and the configuration process may include, for example: writing a clock control register in the hardware debugging module through a JTAG bus, and switching to a high-frequency clock to meet the test requirement; writing a reset control register in the hardware debug module, releasing reset signals of all components in the system, and enabling the memory self-test module 12 in all components to perform memory self-test of the memory 124. In the memory self-test process, the memory controller 121 generates different test methods to detect different errors or anomalies of the memory 124, the memory controller 121 sequentially tests the plurality of memories 124 connected with the memory controller 121, and the memory self-tests can be performed in parallel among the plurality of memory controllers 121 to improve the test efficiency. The above-described clock signals, the por_n reset signal, and the instruction for configuring the hardware debug module by the external controller 31 through the JTAG bus may be all or partially included in the first configuration instruction.
S3, after the test is completed, the memory self-test module 12 returns a completion signal to the hardware debugging module inside the microcontroller 11, and notifies the external controller 31 of the completion of the memory self-test through the JTAG bus.
For a test unit 122, it may also be referred to as a test apparatus, and in some cases, if the comparator 125 in the test apparatus is integrated in the memory 124, the memory 124 may be designed and manufactured by a device manufacturing process and a process compatible with the comparator, which results in a larger wafer size and a higher cost for the test apparatus. To avoid this problem, one embodiment of the present specification provides a test apparatus, referring to fig. 9, comprising: a comparator 125 and a memory 124 packaged independently of each other; a first input terminal In1 of the comparator 125 is connected to the output terminal O1 of the memory 124, and a second input terminal In2 of the comparator 125 is configured to receive test input data; an input I1 of the memory 124 is for receiving the test input data; wherein,
the memory 124 is configured to receive the test input data and output test output data to the comparator;
the comparator 125 is configured to receive the test input data and the test output data, and perform a memory self-test on the memory according to the test input data and the test output data of the memory.
In the present embodiment, by packaging the comparator 125 and the memory 124 independently of each other, the memory 124 is manufactured without considering factors such as device manufacturing process and technology compatible with the comparator 125, which is beneficial to reducing the wafer size required by the memory 124, thereby reducing the cost of the memory 124. Correspondingly, the manufacturing process and technology of the device compatible with the memory 124 are not needed to be considered in the preparation of the comparator 125, which is favorable for reducing the overall size of the comparator 125, so that the overall size of the test equipment is reduced and the equipment cost is reduced on the basis of realizing the test function.
In an alternative embodiment, referring to fig. 9 and 10, the test apparatus further includes: a selector 123, the comparator 125, and the memory 124 being packaged independently of each other;
the selector 123 includes a test mode and a test path, the selector 123 being configured to: in the test mode, data received through the test path is transferred to the memory 124 connected to the selector 123.
By setting the selector 123, the pins of the memory 124 can be reduced, and by setting the mode in which the selector 123 is located, different data can be selected to be input to the memory 124, thereby reducing the hardware requirements on the memory 124.
In an alternative embodiment, still referring to fig. 10, the selector 123 further includes: a working mode and a working path;
the selector 123 is further configured to switch to the test mode when the received enable signal is in the first state, and switch to the operation mode when the received enable signal is in the second state;
in the operation mode, data received through the operation path is transferred to the memory 124 connected to the selector 123.
The enable signal may be a signal sent to the selector by the memory controller, and may control the mode of the selector itself by the enable signal, thereby achieving the purpose of inputting data of different paths to the memory 124. The enable signal may be a level signal, and the first state and the second state of the enable signal may be a high-low level state, respectively.
In this embodiment, the purpose of transmitting the test input data or the normal operation data to the memory 124 is achieved by the selector 123 being in the test mode, so that the input of different data can be achieved under the condition of occupying one pin of the memory 124, the data input requirement of the memory 124 during the test and the normal operation is satisfied, and the hardware requirement of the memory 124 is reduced.
In one possible embodiment, referring to fig. 11, the selector further includes: an enable signal Input EN, a first signal Input1, a second signal Input2, and a signal output Out1; wherein,
the enable signal input end EN is used for receiving the enable signal;
the signal output Out1 is connected to an input of the memory 124;
the first signal Input end Input1 to the signal output end Out1 form the test path;
the second signal Input end Input2 to the signal output end Out2 form the working channel.
Different signal input ends are used as input ends of input data of the test path and the working path, so that interference among different data is reduced.
In one possible implementation, the comparator 125 is further configured to: and outputting a test result of performing memory self-test on the memory 124.
The test results output by the comparator 125 may be transmitted to the memory controller, so that the memory controller learns the test results of the memory 124 and adopts a corresponding control strategy.
In an alternative embodiment, still referring to fig. 11, a first input of the comparator 125 is connected to an output of the memory for receiving the test output data;
A second input terminal In2 of the comparator 125 is connected to an output terminal of the memory controller, and is configured to receive the test input data;
the output end of the comparator 125 is used for connecting with a memory controller, and the test result is transmitted to the memory controller through the output end of the comparator 125.
In the present embodiment, by receiving and outputting data through multiple ports, an abnormality that may be caused by the comparator 125 receiving a plurality of data through a single port can be reduced, which is advantageous in improving the robustness of the device.
In an alternative embodiment, the comparator is further configured to output test information according to the test result; the test information is used to indicate whether the memory is normal.
In an optional implementation manner, the test information carries an identity of the memory;
the test information includes: a first value and a second value; the first value is used for identifying that the memory indicated by the identity of the memory is abnormal, and the second value is used for identifying that the memory indicated by the identity of the memory is normal.
For descriptions of test information and identity, reference may be made to the above related descriptions, and details thereof are omitted herein.
In an alternative embodiment, referring to fig. 12, the test apparatus further includes: a circuit board 126;
the circuit board 126 includes an interconnection line, and the circuit board 126 is configured to carry the comparator 125 and the memory 124, where the comparator 125 and the memory 124 are electrically connected through the interconnection line.
The comparator 125 and the memory 124 are carried by the circuit board 126, and the comparator 125 and the memory 124 are connected by interconnecting lines on the circuit board, which is beneficial to planning and laying out hardware positions and ensuring good communication between the hardware.
In one embodiment of the present specification, there is also provided a computing device including the above-described test device, the computing device may include: a memory controller and a plurality of test devices, the test devices comprising: a comparator and a memory packaged independently of each other;
the memory controller is used for responding to a test instruction and controlling a plurality of test devices to perform memory self-test on the memories respectively included;
the memory self-test includes: the comparator tests the memory according to the test input data of the memory and the test output data of the memory.
In an optional implementation manner, the plurality of test devices are divided into a plurality of test device groups, each test device group in the plurality of test device groups includes at least one test device, the number of the memory controllers is a plurality of, and any one of the plurality of memory controllers is respectively in communication connection with one test device group, and physical characteristics of memories included in the test device groups are the same.
For the description of the test apparatus and the test apparatus group, reference is made to the above description of the test units and the sub-test unit group, and the description is omitted here.
Another embodiment of the present application further provides an electronic device, referring to fig. 2, and an exemplary embodiment of the present specification further provides an electronic device, including: a memory controller 121 and a plurality of test devices, the test devices including: a comparator and a memory packaged independently of each other;
the memory controller is used for responding to a test instruction and controlling a plurality of test devices to perform memory self-test on the memories respectively included;
the memory self-test includes: the comparator tests the memory according to the test input data of the memory and the test output data of the memory.
In fig. 2, one test unit 122 may be referred to as one test apparatus.
In an optional implementation manner, the plurality of test devices are divided into a plurality of test device groups, each test device group in the plurality of test device groups includes at least one test device, the number of the memory controllers is a plurality of, and any one of the plurality of memory controllers is respectively in communication connection with one test device group, and physical characteristics of memories included in the test device groups are the same.
It will be appreciated by those skilled in the art that the structure shown in fig. 2 is merely a block diagram of a portion of the structure associated with the present description and does not constitute a limitation of the electronic device to which the present description is applied, and that a particular electronic device may include more or less components than those shown in the drawings, or may combine certain components, or have a different arrangement of components.
In addition to the methods and apparatus described above, the test methods provided by the embodiments of the present description may also be a computer program product comprising computer program instructions which, when executed by a processor, cause the processor to perform the steps in the test methods according to the various embodiments of the present description described in the "exemplary methods" section of the present description.
The computer program product may write program code for performing the operations of embodiments of the present description in any combination of one or more programming languages, including an object oriented programming language such as Java, C++ or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The program code may execute entirely on the user's computing device, partly on the user's device, as a stand-alone software package, partly on the user's computing device, partly on a remote computing device, or entirely on the remote computing device or server.
Furthermore, the present specification embodiment also provides a computer-readable storage medium having stored thereon a computer program that is executed by a processor to perform the steps in the test method according to the various embodiments of the present specification described in the above "exemplary method" section of the present specification.
Those skilled in the art will appreciate that implementing all or part of the above described methods may be accomplished by way of a computer program stored on a non-transitory computer readable storage medium, which when executed, may comprise the steps of the embodiments of the methods described above. Any reference to memory, storage, database, or other medium used in the embodiments provided herein may include non-volatile and/or volatile memory. The nonvolatile memory can include Read Only Memory (ROM), programmable ROM (PROM), electrically Programmable ROM (EPROM), electrically Erasable Programmable ROM (EEPROM), or flash memory. Volatile memory can include Random Access Memory (RAM) or external cache memory. By way of illustration and not limitation, RAM is available in a variety of forms such as Static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double Data Rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous Link DRAM (SLDRAM), memory bus direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM), among others.
The technical features of the above embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples merely represent a few implementations of the present description, which are described in more detail and are not to be construed as limiting the scope of the solutions provided by the examples of the present description. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the present description, which is within the scope of the present description. Accordingly, the protection scope of the patent should be determined by the appended claims.
Claims (11)
1. A test apparatus, comprising: a comparator and a memory packaged independently of each other; the first input end of the comparator is connected with the output end of the memory, and the second input end of the comparator is used for receiving test input data; the input end of the memory is used for receiving the test input data; wherein,
The memory is used for receiving the test input data through the input end of the memory and outputting test output data to the comparator through the output end of the memory;
the comparator is used for respectively receiving the test input data and the test output data through the second input end and the first input end, and performing memory self-test on the memory according to the test input data and the test output data of the memory.
2. The apparatus as recited in claim 1, further comprising: a selector, the comparator and the memory being packaged independently of each other;
the selector includes a test mode and a test path, the selector configured to: in the test mode, data received through the test path is transferred to the memory connected to the selector.
3. The apparatus of claim 2, wherein the selector further comprises: a working mode and a working path;
the selector is further configured to switch to the test mode when the received enabling signal is in a first state, and switch to the working mode when the received enabling signal is in a second state;
In the operating mode, data received through the operating path is transferred to the memory connected to the selector.
4. The apparatus of claim 3, wherein the selector further comprises: an enable signal input, a first signal input, a second signal input, and a signal output; wherein,
the enabling signal input end is used for receiving the enabling signal;
the signal output end is connected with the input end of the memory;
the first signal input end to the signal output end form the test path;
the second signal input end to the signal output end form the working channel.
5. The apparatus of claim 1, wherein the comparator is further to: and outputting a test result of performing memory self-test on the memory.
6. The apparatus of claim 5, wherein a first input of the comparator is coupled to an output of the memory for receiving the test output data;
the second input end of the comparator is connected with the output end of the memory controller and is used for receiving the test input data;
the output end of the comparator is used for being connected with a memory controller, and the test result is transmitted to the memory controller through the output end of the comparator.
7. The apparatus of claim 5, wherein the comparator is further configured to output test information based on the test result; the test information is used to indicate whether the memory is normal.
8. The apparatus of claim 7, wherein the test information carries an identity of the memory;
the test information includes: a first value and a second value; the first value is used for identifying that the memory indicated by the identity of the memory is abnormal, and the second value is used for identifying that the memory indicated by the identity of the memory is normal.
9. The apparatus of any one of claims 1 to 8, further comprising: a circuit board;
the circuit board comprises an interconnection line, the circuit board is used for bearing the comparator and the memory, and the comparator and the memory are electrically connected through the interconnection line.
10. A computing device, comprising: a memory controller and a plurality of test devices, the test devices comprising: a comparator and a memory packaged independently of each other;
the memory controller is used for responding to a test instruction and controlling a plurality of test devices to perform memory self-test on the memories respectively included;
The memory self-test includes: the comparator tests the memory according to the test input data of the memory and the test output data of the memory.
11. The computing device of claim 10, wherein the plurality of test devices is divided into a plurality of test device groups, each test device group of the plurality of test device groups including at least one of the test devices, the number of memory controllers being a plurality, any one of the plurality of memory controllers establishing a communication connection with a respective one of the test device groups, the physical characteristics of the memories included in the test device groups being the same.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311309491.3A CN117095731B (en) | 2023-10-11 | 2023-10-11 | Test equipment and computing equipment |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202311309491.3A CN117095731B (en) | 2023-10-11 | 2023-10-11 | Test equipment and computing equipment |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN117095731A CN117095731A (en) | 2023-11-21 |
| CN117095731B true CN117095731B (en) | 2024-01-30 |
Family
ID=88775636
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202311309491.3A Active CN117095731B (en) | 2023-10-11 | 2023-10-11 | Test equipment and computing equipment |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN117095731B (en) |
Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201117296Y (en) * | 2007-11-05 | 2008-09-17 | 深圳艾科创新微电子有限公司 | Embedded type memory built-in self-testing structure |
| CN102970013A (en) * | 2012-11-28 | 2013-03-13 | 中国人民解放军国防科学技术大学 | Resetting method and resetting control device of register inside chip based on scanning chain |
| CN103310852A (en) * | 2013-05-13 | 2013-09-18 | 桂林电子科技大学 | MBIST (Memory Built In Self Test) controller structure system based on IEEE (Institute of Electrical and Electronics Engineers) 1500 standard and compatible with SRAM/ROM (Static Random Access Memory/Read Only Memory) |
| US8650524B1 (en) * | 2012-11-09 | 2014-02-11 | Cadence Design Systems, Inc. | Method and apparatus for low-pin count testing of integrated circuits |
| CN104078082A (en) * | 2013-03-29 | 2014-10-01 | 芯成半导体（上海）有限公司 | Circuit and method for testing storage device |
| CN108062267A (en) * | 2017-11-24 | 2018-05-22 | 中国人民解放军国防科技大学 | Configurable register file self-testing method and generating device |
| CN115346591A (en) * | 2022-09-22 | 2022-11-15 | 深圳国微福芯技术有限公司 | Memory test method and test system |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20070064401A1 (en) * | 2005-09-16 | 2007-03-22 | Lih Duo International Co., Ltd. | Printed circuit board and memory module using the same |
| JPWO2008053709A1 (en) * | 2006-11-02 | 2010-02-25 | 日本電気株式会社 | Semiconductor integrated circuit sorting test apparatus and method |
| US8793549B2 (en) * | 2010-08-11 | 2014-07-29 | Lsi Corporation | Low-cost design for register file testability |
-
2023
- 2023-10-11 CN CN202311309491.3A patent/CN117095731B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN201117296Y (en) * | 2007-11-05 | 2008-09-17 | 深圳艾科创新微电子有限公司 | Embedded type memory built-in self-testing structure |
| US8650524B1 (en) * | 2012-11-09 | 2014-02-11 | Cadence Design Systems, Inc. | Method and apparatus for low-pin count testing of integrated circuits |
| CN102970013A (en) * | 2012-11-28 | 2013-03-13 | 中国人民解放军国防科学技术大学 | Resetting method and resetting control device of register inside chip based on scanning chain |
| CN104078082A (en) * | 2013-03-29 | 2014-10-01 | 芯成半导体（上海）有限公司 | Circuit and method for testing storage device |
| CN103310852A (en) * | 2013-05-13 | 2013-09-18 | 桂林电子科技大学 | MBIST (Memory Built In Self Test) controller structure system based on IEEE (Institute of Electrical and Electronics Engineers) 1500 standard and compatible with SRAM/ROM (Static Random Access Memory/Read Only Memory) |
| CN108062267A (en) * | 2017-11-24 | 2018-05-22 | 中国人民解放军国防科技大学 | Configurable register file self-testing method and generating device |
| CN115346591A (en) * | 2022-09-22 | 2022-11-15 | 深圳国微福芯技术有限公司 | Memory test method and test system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN117095731A (en) | 2023-11-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN117093430B (en) | Test method, test device, computing equipment and storage medium | |
| US6256760B1 (en) | Automatic test equipment scan test enhancement | |
| US8127187B2 (en) | Method and apparatus of ATE IC scan test using FPGA-based system | |
| US6505317B1 (en) | System and method for testing signal interconnections using built-in self test | |
| CN111308329B (en) | Circuit, device and method for testability design of many-core computing chip | |
| US9097762B2 (en) | Method and apparatus for diagnosing an integrated circuit | |
| JP3893238B2 (en) | Semiconductor memory device failure analysis device | |
| CN101329385A (en) | Regulation test system and method of on-chip system as well as on-chip system | |
| US11519961B2 (en) | Extended JTAG controller and method for functional debugging using the extended JTAG controller | |
| CN116774018B (en) | Chip testing method and device and electronic equipment | |
| US9455050B2 (en) | Failure diagnosis circuit | |
| US12092685B2 (en) | Chip and chip test system | |
| CN117054864A (en) | Chip testing system, method, chip and medium | |
| CN106291313B (en) | Method and apparatus for testing integrated circuits | |
| CN111366842A (en) | Chip mass production test system and method | |
| CN117095731B (en) | Test equipment and computing equipment | |
| CN112799887B (en) | Chip FT test system and test method | |
| US7716541B2 (en) | Test apparatus and electronic device for generating test signal to a device under test | |
| CN114121120A (en) | Detection system, method and chip of memory | |
| CN116705107B (en) | Memory address transmission circuit, method and device, memory medium and electronic equipment | |
| CN117253526A (en) | Test method and device for memory, computing equipment and storage medium | |
| CN115691632A (en) | Test control system and method | |
| CN117093431A (en) | Test method, test device, computing equipment and storage medium | |
| CN117316249A (en) | Register testing method, device, computing equipment and storage medium | |
| US20160187424A1 (en) | Apparatus for fault injection to semiconductor chip having diagnostic function |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |