CN112183005B - DFT circuit construction method and application in integrated circuit test mode - Google Patents
DFT circuit construction method and application in integrated circuit test mode Download PDFInfo
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Abstract
The invention discloses a DFT circuit construction method under an integrated circuit test mode and application thereof, wherein the method comprises the following steps: s1, acquiring functional clock information in an integrated circuit, and grouping according to a logic interaction relation between functional clocks, so that no logic interaction relation exists between any two functional clocks divided into the same clock group; s2, setting global DFT clocks with the number equal to that of the clock groups, wherein the global DFT clocks correspond to the clock groups one by one, and taking over all functional clocks in the corresponding clock groups by using the global DFT clocks; and S3, for each clock packet, linking the functional clocks in the clock packet to the same scan chain to complete the construction of the scan chain circuit of the clock packet. The method has the advantages of improving the test mode time sequence of the integrated circuit, avoiding the insertion of a large number of buffer units and the like.
Description
Technical Field
The invention relates to the field of Design for Test (DFT) of integrated circuits, in particular to a DFT circuit construction method and application in a Test mode of the integrated circuits, and the DFT circuit construction method comprises a DFT circuit construction system, a storage medium and a DFT circuit construction device.
Background
As integrated circuit fabrication processes advance and the complexity of chips increases, it becomes more challenging to design testability circuits for the chips. Key to design for testability is controllability, which is the ability to set and reset every node inside a circuit, and observability, which is the ability to observe, directly or indirectly, the state of any node in a circuit. The purpose of design for testability is two: firstly, finding out the fixed fault of the chip, such as the disconnection of a test chain circuit caused by a manufacturing process; secondly, the actual performance of the chip is tested, and mass production of the sieve sheet is facilitated. The serial interface module of the very large scale integrated circuit chip is necessary, and a circuit system based on PCIE and an Ethernet protocol has the disadvantages of a large number of clocks, a complex clock structure and a large number of time sequence units. In the face of such a complex circuit system, how to realize testability design friendly to physical design is a difficult problem in front of DFT and physical design engineers.
The traditional testability design method is to combine the clocks at will to form a plurality of clock groups, then take the chip scan clock input port as the clock source of each clock in the clock groups, and under the condition that the number of the chip DFT input ports is limited, usually more than ten sub-system internal clocks need to be taken over by one scan clock input port. The scan chain insertion is spread out in groups of each DFT clock. However, in the conventional design method for testability, two clocks having a logic path in the functional mode are divided into one DFT clock packet, and then the serial chaining of registers is performed according to the DFT clock packet, so that a balanced clock tree in the functional mode becomes unbalanced in the test mode, thereby introducing a large amount of hold time violations, increasing a large number of buffer units, wasting the area of a chip, and increasing the power consumption of the chip.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides a DFT circuit construction method and application in an integrated circuit test mode, which can improve the time sequence of an integrated circuit test mode, avoid the insertion of a large number of buffer units, and effectively avoid the defects that the traditional method needs to introduce a large number of retention time violations and the like.
In order to solve the technical problems, the technical scheme provided by the invention is as follows: a DFT circuit construction method under integrated circuit test mode includes the following steps:
s1, acquiring functional clock information in an integrated circuit, and grouping according to a logic interaction relation between functional clocks, so that no logic interaction relation exists between any two functional clocks divided into the same clock group;
s2, setting global DFT clocks with the number equal to that of the clock groups, wherein the global DFT clocks correspond to the clock groups one by one, and taking over all functional clocks in the corresponding clock groups by using the global DFT clocks;
and S3, for each clock packet, linking the functional clocks in the clock packet to the same scan chain to complete the construction of the scan chain circuit of the clock packet.
Further, in step S1, whether a logic interaction relationship exists between the two functional clocks is determined by determining whether a register in a clock domain of the two functional clocks has a timing check path.
Further, the clock grouping in step S1 is the largest set of functional clocks having no logical interaction relationship between the functional clocks.
Further, step S3 specifically includes: and respectively generating scan chains aiming at the functional clock domains of the functional clocks in each clock packet, and then serially connecting the scan chains of the functional clock domains to obtain the final scan chain. .
A DFT circuit construction system of integrated circuit test mode time sequence comprises a clock grouping module, a clock initialization module and a scan chain generation module;
the clock grouping module is used for acquiring functional clock information in the integrated circuit and grouping according to the logic interaction relationship between the functional clocks, so that the logic interaction relationship does not exist between any two functional clocks which are divided into the same clock group;
the clock initialization module is used for setting global DFT clocks with the number equal to that of the clock groups, the global DFT clocks correspond to the clock groups one by one, and the global DFT clocks are used for taking over all functional clocks in the corresponding clock groups;
and the scan chain generation module is used for linking the functional clocks in the clock groups to the same scan chain for each clock group so as to complete the construction of the scan chain circuit of the clock group.
Further, the clock grouping module determines whether a logic interaction relationship exists between the two functional clocks by judging whether a register under the clock domains of the two functional clocks has a time sequence checking path.
Further, the clock grouping in the clock grouping module is the largest set of functional clocks without logical interaction relationship between the functional clocks.
Further, the scan chain generation module is specifically configured to generate scan chains for the functional clock domains of the functional clocks in each clock packet, and then serially connect the scan chains of the functional clock domains to obtain a final scan chain. .
A storage medium having stored therein a computer program which when executed implements a DFT circuitry construction method in integrated circuit test mode as recited in any preceding claim.
A DFT circuit building apparatus of integrated circuit test pattern timing comprising a processor for executing a computer program stored in a storage medium and the storage medium as described above.
Compared with the prior art, the invention has the advantages that:
1. the invention divides two clocks with logic paths between each other into different clock groups by grouping the functional clocks in the integrated circuit, then serially connects the registers under each functional clock domain in the same clock group and adds the registers into the scan chain to form a complete scan chain, thereby effectively reducing the number of Hold (Hold) check paths between different clock domains and the insertion of a large number of buffer units, avoiding wasting chip area and increasing chip functions, and achieving the purposes of improving test mode time sequence and reducing the difficulty of realizing physical design. Further, two clocks without logic paths between each other are divided into the same clock group, that is, the functional clocks in the same clock group are the largest set of functional clocks satisfying the above-mentioned division condition, so that the number of global DFT clocks can be further reduced, and the number of Hold check paths and the number of inserted buffer units can be reduced.
Drawings
FIG. 1 is a schematic flow chart of an embodiment of the present invention.
Fig. 2 is a functional clock information diagram according to an embodiment of the invention.
Fig. 3 is a schematic diagram of a functional Clock interaction (Clock talk) list according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of clock grouping according to an embodiment of the present invention.
FIG. 5 is a diagram of clock grouping, global DFT clock number and chip top IOPAD according to an embodiment of the present invention.
Fig. 6 is a diagram illustrating global DFT clock takeover clock grouping according to an embodiment of the present invention.
FIG. 7 is a diagram illustrating scan chain construction within a clock packet according to an embodiment of the present invention.
Detailed Description
The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.
The DFT circuit construction method under the integrated circuit test mode of the embodiment comprises the following steps: s1, acquiring functional clock information in an integrated circuit, and grouping according to a logic interaction relation between functional clocks, so that no logic interaction relation exists between any two functional clocks divided into the same clock group; s2, setting global DFT clocks with the number equal to that of the clock groups, wherein the global DFT clocks correspond to the clock groups one by one, and taking over all functional clocks in the corresponding clock groups by using the global DFT clocks; and S3, for each clock packet, linking the functional clocks in the clock packet to the same scan chain to complete the construction of the scan chain circuit of the clock packet.
In step S1 of this embodiment, it is determined whether there is a logical interaction relationship between two functional clocks by determining whether there is a timing check path in a register in a clock domain of the two functional clocks. Specifically, the functional Clock information of the integrated circuit includes a Clock Name (Clock Name), a Clock Period (Clock Period), and a Clock Source (Clock Source); by acquiring the functional clock information of the integrated circuit, a functional clock information list as shown in fig. 2 can be generated, and by retrieving the functional clock information list, it can be determined whether a timing check path exists between the two functional clocks, and when the timing check path exists, a logical interaction relationship exists between the two functional clocks is defined, otherwise, the logical interaction relationship does not exist between the two functional clocks is defined. A functional clock logic interaction relationship diagram may be generated according to the retrieved functional clock information list, as shown in fig. 3, Y indicates that a logic interaction relationship exists between two functional clocks, and N indicates that a logic interaction relationship does not exist between two functional clocks.
As shown in fig. 2, it is assumed that a functional clock a and a functional clock b exist in the integrated circuit design, and one or more timing check paths from a register in clock a (clka) to a register in clock b (clkb) exist between the two functional clocks, which indicates that the functional clock a and the functional clock b have a logical interaction relationship; similarly, when the functional clock a and the functional clock b in the integrated circuit design have one or more timing check paths from the register in the clock b to the register in the clock a, it indicates that the functional clock a and the functional clock b also have a logic interaction relationship.
As shown in fig. 3, it is assumed that a functional clock a (clka), a functional clock b (clkb), a functional clock c (clkc), and a functional clock d (clkd) exist in the integrated circuit design, if the functional clock a has a logical interaction relationship with the functional clocks b and d, the functional clock b has a logical interaction relationship with the functional clocks a and c, the functional clock c has a logical interaction relationship with the functional clocks d and b, and the functional clock d has a logical interaction relationship with the functional clocks a and c; functional clock a and functional clock c are divided into the same clock packet, and functional clock b and functional clock d are divided into another clock packet. For a functional Clock without logic interaction relationship, as shown in fig. 4, the functional Clock a (Function CLKa) and the functional Clock c (Function CLKc) are divided into the same Clock packet, the Clock Domain (Clock Domain) of the Clock packet is denoted as DFT Clock Domain1, the functional Clock b (Function CLKb) and the functional Clock d (Function CLKd) are divided into another Clock packet, and the Clock Domain (Clock Domain) of the Clock packet is denoted as DFT Clock Domain 2.
In this embodiment, the clock grouping in step S1 is preferably the largest set of functional clocks having no logical interaction relationship between the functional clocks. For the logic interaction relationship shown in fig. 3, 4 clock groups are respectively constructed, each clock group including only one functional clock; or 3 clock groups are constructed, for example, the functional clock a is a clock group, the functional clock b and the functional clock d are a clock group, and the functional clock c is a clock group; although the two grouping modes also enable functional clocks in each clock group not to have a logic interaction relationship, the number of global DFT clocks to be constructed is increased, and a better effect is difficult to achieve.
The specific method for constructing the clock packet can be determined according to the existing packet algorithm, and the following packet mode is preferred in this embodiment: and traversing and taking out a current functional clock from the logic interaction relation table, putting the current functional clock into a first clock group, then finding out all functional clocks having logic interaction relation with the current functional clock to obtain a logic interaction relation set, if no logic interaction relation exists among all functional clocks in the logic interaction relation set, putting all functional clocks in the logic interaction relation set into a second clock group, otherwise, grouping all functional clocks in the logic interaction relation set as a group according to no logic interaction relation, and if N groups are obtained, putting the functional clocks of the N groups into 2 nd to N th clock groups in a one-to-one correspondence manner respectively. And repeating the steps until the logic interaction relation table is traversed.
In this embodiment, the global DFT clock number of the same integrated circuit to be optimized is defined according to the number of clock groups, and the global DFT clock number determines the number of chip pin processing modules (IOPAD) at the Top level (Top level) of the integrated circuit chip, and each global DFT clock is enabled to take over all functional clock trees under the corresponding clock group. As the global DFT clock number of the chip defined in this embodiment is 2, as shown in fig. 5, the number of chip pin processing modules (IOPAD) at the top layer of the chip is greater than or equal to 2; each global DFT clock takes over all functional clock trees under the clock packet, as shown in fig. 6, functional clock a and functional clock c are taken over by global DFT clock DFT CLK1, and functional clock b and functional clock d are taken over by global DFT clock DFT CLK 2.
In this embodiment, preferably, step S3 is: and respectively generating scan chains aiming at the functional clock domains of the functional clocks in each clock packet, and then serially connecting the scan chains of the functional clock domains to obtain the final scan chain. The conventional process of generating scan chains is to directly traverse the registers (registers) of the functional clock domains within a clock packet and then directly add the registers to the scan chains, which may result in an increased number of Hold (Hold) timing violations of the registers of different functional clock domains in the test mode. To solve a problem, the scan chain generation method of this embodiment is to generate scan chains for functional clock domains in a clock packet of each global DFT clock, and then serially connect the scan chains of the clock domains to obtain a final scan chain. As shown in the left diagram of fig. 7, the number of functional clocks included in DFT clock domain1 is greater than 1, and SI ports of all registers under functional clock a and functional clock b are connected to a Scan Chain (Scan Chain) respectively; as shown in the right diagram of fig. 7, the head of the Scan chain of all registers under the functional clock b and the tail of the Scan chain of all registers under the functional clock a are connected to complete the design of the clock grouping Scan chain circuit, and SI represents the Scan input (Scan in) of the Scan chain.
The embodiment also comprises a system, a storage medium and a device for realizing the DFT construction method, and the DFT circuit construction of the integrated circuit test mode time sequence is realized.
The DFT circuit construction system of the integrated circuit test mode time sequence of the embodiment comprises a clock grouping module, a clock initialization module and a scan chain generation module; the clock grouping module is used for acquiring functional clock information in the integrated circuit and grouping according to the logic interaction relationship between the functional clocks, so that the logic interaction relationship does not exist between any two functional clocks divided into the same clock group; the clock initialization module is used for setting global DFT clocks with the same number as the clock groups, the global DFT clocks correspond to the clock groups one by one, and the global DFT clocks are used for taking over all functional clocks in the corresponding clock groups; and the scan chain generation module is used for linking the functional clocks in the clock groups to the same scan chain for each clock group so as to complete the construction of the scan chain circuit of the clock group.
In this embodiment, the clock grouping module preferably determines whether a logical interaction relationship exists between the two functional clocks by determining whether a register in the two functional clock domains has a timing check path. The clock grouping in the clock grouping module is preferably the largest set of functional clocks for which no logical interaction exists between the functional clocks. The scan chain generation module is preferably specifically configured to generate scan chains for the functional clock domains of the functional clocks in each clock packet, and then to connect the scan chains of the functional clock domains in series to obtain a final scan chain. .
The storage medium of the present embodiment stores therein a computer program that can implement the DFT circuit building method in the integrated circuit test mode as described above when executed.
The DFT circuit building apparatus of the integrated circuit test pattern timing of the present embodiment comprises a processor and a storage medium, wherein the processor is used for executing the computer program stored in the storage medium, and the storage medium is the storage medium as above.
As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-readable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein. The present application is directed to methods, apparatus (systems), and computer program products according to embodiments of the present application, wherein the instructions that execute on the flowcharts and/or processors of the computer program product create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks. These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
The above description is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above embodiments, and all technical solutions belonging to the idea of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to those skilled in the art without departing from the principles of the present invention should also be considered as within the scope of the present invention.
Claims (10)
1. A DFT circuit construction method under an integrated circuit test mode is characterized by comprising the following steps:
s1, acquiring functional clock information in an integrated circuit, and grouping according to a logic interaction relation between functional clocks, so that no logic interaction relation exists between any two functional clocks divided into the same clock group;
s2, setting global DFT clocks with the number equal to that of the clock groups, wherein the global DFT clocks correspond to the clock groups one by one, and taking over all functional clocks in the corresponding clock groups by using the global DFT clocks;
and S3, for each clock packet, linking the functional clocks in the clock packet to the same scan chain to complete the construction of the scan chain circuit of the clock packet, wherein SI ports of all registers in the same scan chain are respectively connected to the same scan chain.
2. The DFT circuitry construction method in integrated circuit test mode as recited in claim 1, wherein: in step S1, whether a logical interaction relationship exists between two functional clocks is determined by determining whether a register in a clock domain of the two functional clocks has a timing check path.
3. The DFT circuitry construction method in integrated circuit test mode as recited in claim 1, wherein: in step S1, the clock groups are the largest set of functional clocks having no logical interaction relationship between the functional clocks.
4. The DFT circuit construction method under integrated circuit test mode of any of claims 1 to 3, wherein step S3 specifically comprises: and respectively generating scan chains aiming at the functional clock domains of the functional clocks in each clock packet, and then serially connecting the scan chains of the functional clock domains to obtain the final scan chain.
5. A DFT circuitry construction system in a test mode of an integrated circuit, comprising: the device comprises a clock grouping module, a clock initialization module and a scan chain generation module;
the clock grouping module is used for acquiring functional clock information in the integrated circuit and grouping according to the logic interaction relationship between the functional clocks, so that the logic interaction relationship does not exist between any two functional clocks which are divided into the same clock group;
the clock initialization module is used for setting global DFT clocks with the number equal to that of the clock groups, the global DFT clocks correspond to the clock groups one by one, and the global DFT clocks are used for taking over all functional clocks in the corresponding clock groups;
and the scan chain generation module is used for linking the functional clocks in the clock groups to the same scan chain for each clock group so as to complete the construction of the scan chain circuit of the clock group, and the SI ports of all registers in the same scan chain are respectively connected to the same scan chain.
6. The DFT circuitry building system in a test mode for an integrated circuit as recited in claim 5, wherein: the clock grouping module determines whether a logic interaction relationship exists between the two functional clocks by judging whether a register under the clock domains of the two functional clocks has a time sequence checking path.
7. The DFT circuitry building system in a test mode for an integrated circuit as recited in claim 5, wherein: and the clock grouping in the clock grouping module is the maximum set of the functional clocks without logic interaction relation among the functional clocks.
8. The DFT circuit building system under the integrated circuit test mode according to any one of claims 5 to 7, wherein the scan chain generation module is specifically configured to generate scan chains for the functional clock domains of the functional clocks in each clock packet, and then serially connect the scan chains of the functional clock domains to obtain a final scan chain.
9. A storage medium, characterized by: the storage medium has stored therein a computer program which, when executed, implements a DFT circuitry construction method in integrated circuit test mode as recited in any one of claims 1 to 4.
10. A DFT circuitry building apparatus in an integrated circuit test mode, comprising a processor and a storage medium, the processor being configured to execute a computer program stored in the storage medium, characterized in that: the storage medium is the storage medium of claim 9.
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