CN112345924A

CN112345924A - Scan chain control circuit

Info

Publication number: CN112345924A
Application number: CN202011188517.XA
Authority: CN
Inventors: 孙腾达; 俞日龙
Original assignee: Shanghai Zhaoxin Integrated Circuit Co Ltd
Current assignee: Shanghai Zhaoxin Integrated Circuit Co Ltd
Priority date: 2020-10-30
Filing date: 2020-10-30
Publication date: 2021-02-09
Anticipated expiration: 2040-10-30
Also published as: CN112345924B

Abstract

The present invention provides a scan chain control circuit, which includes: chip testing through an interface on a test circuit board without connecting a lead through a lead terminal; when the scan chain control circuit is under the action of a pin shift clock, The scan chain control circuit inputs the pin input data to the scan chain test circuit and outputs the test data after the test is completed; when the scan chain control circuit is under the action of the register shift clock signal, the scan chain control The circuit inputs the register input data to the scan chain test circuit for testing, and then outputs the completed test data. The invention can realize the test data input/output control of the scan chain test circuit, improve the test flexibility, and can test whether the chip can operate correctly even when the test pins are not easily exposed or have poor contact.

Description

Scan chain control circuit

Technical Field

The present invention relates to integrated circuit chip test circuits, and more particularly, to a control circuit of a scan chain test circuit of an integrated circuit chip.

Background

With the continuous development of large-scale integrated circuit chip technology, the chip integration level is higher and higher; consequently, chip testing is becoming more and more difficult. The scan chain test circuit has the advantages of high reliability, accurate test and the like, is widely applied to the test of integrated circuit chips, and becomes an essential component in modern chip design. However, the scan chain test circuit has many test pins, and the conventional test method needs an external lead wire during test, which results in high test difficulty. Especially, when the chip is packaged on the printed circuit board, the test difficulty is increased due to the problems that too many test pins are not easy to be completely exposed or the test pins are not in good contact due to the chip packaging.

Disclosure of Invention

The invention provides a scan chain control circuit, in particular to a scan chain control circuit integrating a scan chain test circuit pin. Under the condition that the test pins are not exposed after the chip is packaged, the data input/output control of the scan chain test circuit can be realized, and the test flexibility is improved.

In a preferred embodiment, the present invention provides a scan chain control circuit comprising: the chip test is carried out through an interface on the test circuit board without the need of externally connecting a lead wire through a lead wire end, when the scan chain control circuit is under the action of a pin shift clock, the scan chain control circuit inputs pin input data into the scan chain test circuit and outputs test data after the test; when the scan chain control circuit is under the action of the shift clock signal of the register, the scan chain control circuit inputs the input data of the register to the scan chain test circuit for testing and then outputs the tested test data.

In some embodiments, the scan chain control circuit can be applied to a Joint Test Action Group (JTAG) Debug interface and/or a Serial Wire Debug (SWD) interface.

In some embodiments, the input pins of the scan chain test circuit are uniformly coupled to the scan chain control circuit.

In some embodiments, the pin input data is transmitted from the scan chain test circuit pin to the scan chain control circuit and then to the scan chain test circuit.

In some embodiments, the scan chain control circuit is capable of generating the register input data through the scan chain control circuit and transmitting to the scan chain test circuit.

In some embodiments, the output pin of the scan chain test circuit is uniformly coupled to the scan chain control circuit.

In some embodiments, the test data of the test completion of the pin input data transmitted by the scan chain test circuit pin is uniformly transmitted to the scan chain control circuit and output through an interface on a test circuit board.

In some embodiments, the test data generated by the scan chain control circuit and tested by the register input data is transmitted to the scan chain control circuit and output through an interface on a test circuit board.

In some embodiments, the scan chain control circuit outputs test data after testing the pin input data transmitted by the scan chain test circuit pin under the action of the pin shift clock.

In some embodiments, in the case that the scan chain control circuit operates in the original test mode, the scan chain control circuit outputs test data after testing the pin input data transmitted by the scan chain test circuit pin under the action of the pin shift clock.

In some embodiments, the scan chain control circuit outputs test data after testing the register input data generated by the scan chain control circuit under the action of the register shift clock.

In some embodiments, in a case where the scan chain control circuit operates in a scan mode, the scan chain control circuit outputs test data after testing the register input data generated by the scan chain control circuit under the action of a register shift clock.

In some embodiments, when the scan chain control circuit operates in the original test mode, the scan chain control circuit can be switched to the scan mode by resetting operation and restarting the scan chain control circuit.

In some embodiments, when the scan chain control circuit operates in the scan mode, the scan chain control circuit can be switched to the original test mode by resetting operation and restarting the scan chain control circuit.

Drawings

Fig. 1 is a basic schematic diagram of a scan chain test circuit according to the present invention.

Fig. 2 is a schematic diagram of a scan chain control circuit according to an embodiment of the invention.

Fig. 3 is a schematic diagram of a data selector according to an embodiment of the invention.

Fig. 4 is a schematic diagram of a clock controller according to an embodiment of the invention.

Fig. 5 is a schematic diagram of a mode controller according to an embodiment of the invention.

FIG. 6 is a diagram of a scan chain control circuit clock signal according to an embodiment of the invention.

Fig. 7 is a flowchart of a scan chain control circuit according to an embodiment of the invention.

FIG. 8 is a schematic diagram of a scan chain test circuit packaged on a PCB according to an embodiment of the invention.

Wherein the symbols in the drawings are briefly described as follows:

100-scan chain test circuit; 200-scan chain control circuit; 202-external equipment; 204-register controller; 206-data selector; 208-a clock controller; 210-mode controller; 212. 212-1, 212-2, 212-3, 212-4 to scan chain test circuits; 214-register clock control module; 216-register mode control module; 400. 402, 406, 408, 500, 502-D flip-flops; 404. 410-gated clock circuit; 412 clock oscillator (PLL); 414 to a first data selector; 416-a second data selector; 504 to a third data selector; 506 to a fourth data selector; reg _ scan _ in [ n:0] -register input data; reg _ scan _ out [ n:0] -register output data; SCAN _ IN [ n:0] -input data; SCAN _ EN-enable clock signal; IP _ CLK to shift clock; DFT _ ON-mode testing clock signals; SE-mode scan enable clock signal; SCAN _ OUT [ n:0] -output data; IC1, IC 2-integrated design circuit to be tested; DFF-D type flip-flops; input _0, Input _1 … Input _ n-Input pins; output _0, Output _1 … Output _ n-Output pin; SI _0, SI _1 … SI _ n-scan chain test circuit input data; TCK-test clock signal; shift _ clk to register Shift clock signal; ext _ clk to pin shift clock; PLL-clock oscillator; ICG gate control clock circuit; func _ clk functional clock signal; scan _ mode _ dp-mode testing a backup clock signal; scan _ en _ dp-mode Scan enable backup clock signals; SE _ i-mode scanning enabling clock signals of the original control scanning chain test circuit; DFT _ ON _ i-test mode clock signal of original control scan chain test circuit; test _ mode — Test mode signal; t1-first time period; t2-second time interval; t3 to the third period; t4-fourth period; t5-fifth period; s702, S704, S706, S708, S710, and a flow chart.

Detailed Description

In order to make the objects, features and advantages of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.

In the following description and in the claims, the terms "include" and "comprise" are used in an open-ended fashion, and thus should be interpreted to mean "include, but not limited to. The term "coupled" is used in this specification to include any direct or indirect electrical connection. Thus, if a first device couples to a second device, that connection may be through a direct electrical connection, or through an indirect electrical connection via other devices and connections.

Certain terms are used throughout the description and claims to refer to particular components and features. As one skilled in the art will appreciate, manufacturers may refer to a component or an element by different names. The present specification and claims do not intend to distinguish between components and features that differ in name but not function.

Fig. 1 is a basic schematic diagram of a scan chain test circuit according to the present invention. IN chip design, the chip test circuit may comprise a plurality of SCAN chain test circuits as shown IN FIG. 1 (e.g., a plurality of SCAN chain test circuits with input pins SI _0, SI _1, SI _2, SI _3 … SI _ N and output pins SO _0, SO _1, SO _2, SO _3 … SO _ N as shown IN FIG. 1), each SCAN chain test circuit providing a designer with analysis of the chip design by coupling to a respective input/output Pin (PAD) and importing test data (SCAN _ IN [ N:0]) or exporting test data (SCAN _ OUT [ N:0]) under the action of a shift clock (IP _ CLK).

However, when a chip is packaged on a PCB board, the input/output pins (PAD pins) of the above chip design may not be exposed due to package coverage or may have poor pin contact due to the package due to packaging reasons. Finally, test inconvenience or inaccurate test data can be caused, the chip design cannot be well analyzed, and the test cost and difficulty are increased. When a chip is packaged on a PCB board, in particular, the following conditions occur to cause inaccurate testing. First, the input pin of the scan chain test circuit of SI _1 is not exposed due to packaging (as shown in fig. 1, drawing an "X" on the PAD pin indicates that the pin is not exposed), so that the tester cannot connect the external lead to the circuit board for subsequent testing. Secondly, it may also cause the output pins not to be exposed (as shown in fig. 1, the output pins of the scan chain test circuit of SI _2 are not exposed), and also cause the tester not to connect the external leads to the circuit board for subsequent testing. Thirdly, even if the pin is exposed, the problems such as poor pin contact may be caused (as shown in fig. 1, Δ "is drawn on the PAD pin to indicate poor pin contact), which may lead to inaccurate test and poor analysis of the chip design. Moreover, the above three situations can occur simultaneously, which results in inaccurate test data and increases the test cost and difficulty.

Therefore, fig. 2 is a schematic diagram of a scan chain control circuit according to an embodiment of the invention. The scan chain control circuit 200 can be applied to a scan chain test circuit 212 of a control integrated circuit chip, so that data input/output control of the scan chain test circuit is realized, and test flexibility is improved. As shown in fig. 2, the scan chain control circuit 200 includes: a register controller 204, a data selector 206, a clock controller 208, and a mode controller 210; the register controller 204 further comprises a register clock control module 214 and a register mode control module 216. The clock controller 208 is coupled to the register controller 204 and the mode controller 210, receives an enable clock signal (SCAN _ EN) and a register Shift clock signal (Shift _ CLK) outputted from the register controller 204, receives a mode SCAN enable clock Signal (SE) outputted from the mode controller 210, and outputs a Shift clock signal (IP _ CLK); the mode controller 210 is coupled to the register controller 204, receives the enable clock signal (SCAN _ EN), and outputs a mode test clock signal (DFT _ ON) and the mode SCAN enable clock Signal (SE); a data selector 206 coupled to the scan chain test circuit 212 and the register controller 204; when the enable clock signal received by the data selector 206 is at a first level, the data selector 206 selects a register input data (Reg _ SCAN _ IN [ n:0]) as an input data (SCAN _ IN [ n:0]) to be input to the SCAN chain test circuit 212; when the enable clock signal received by the data selector 206 is at the second level, the data selector 206 selects a pin input data (SI _0, SI _1 … SI _ n) as an input data (SCAN _ IN [ n:0]) to be input to the SCAN chain test circuit 212. Here, the mode test clock signal (DFT _ ON) and the mode SCAN enable clock Signal (SE) outputted from the mode controller 210 are output signals for controlling output data after the input data (SCAN _ IN [ n:0]) are tested by the SCAN chain test circuit 212. In some embodiments, as shown in part in fig. 6, the test mode clock signal (DFT _ ON) is pulled up to a high level signal by the mode controller 210 after receiving the test clock signal TCK signal (generated by the external device 202 in the test state) 3 clock signals, and the mode scan enable clock Signal (SE) is pulled up to a high level signal by the mode controller 210 after receiving the TCK signal 4 clock signals, or the test mode clock signal (DFT _ ON) and the mode scan enable clock Signal (SE) are pulled up to a high level signal by the mode controller 210 after the TCK signal for several clock cycles, and the test mode clock signal (DFT _ ON) is pulled up to a high level signal before the mode scan enable clock Signal (SE). It should be noted that, the test mode clock signal (DFT _ ON) is pulled up to a high level signal 1 clock cycle before the mode scan enable clock Signal (SE), and those skilled in the art can configure the signal according to actual needs, and the invention is not limited thereto.

The pull-up of the test mode clock signal (DFT _ ON) and the mode SCAN enable clock Signal (SE) to high indicates that the output data (SCAN _ OUT [ n:0] in FIG. 2) after the test by the SCAN chain test circuit 212 can be outputted to the SCAN chain control circuit 200 in FIG. 2 and finally to the external device for the designer to analyze. It should be noted that the test mode clock signal (DFT _ ON) and a mode SCAN enable clock Signal (SE) are used to control the output of the test output data (SCAN _ OUT [ n:0] shown in FIG. 2).

In some embodiments, a pattern scan enable clock signal (SE _ i) and a pattern test clock signal (DFT _ i) of an original control scan chain test circuit are similar to the pull-up principle of the test pattern clock signal (DFT _ ON) and the pattern scan enable clock Signal (SE). The mode scan enable clock signal (SE _ i) and the mode test clock signal (DFT _ i) of the original control scan chain test circuit may be pulled up to a high level signal after receiving a plurality of clock signals of the TCK signal using an internal circuit module (not shown in fig. 5) and the mode test clock signal (DFT _ i) is pulled up to a high level signal before the mode scan enable clock signal (SE _ i) of the original control scan chain test circuit. It should be noted here that the mode test clock signal (DFT _ i) is pulled up to a high level signal 1 clock cycle before the mode scan enable clock signal (SE _ i) of the original control scan chain test circuit. Those skilled in the art can configure the related mode signal control module of the original scan chain test circuit according to the product requirement, and the invention is not limited thereto. For the description of this part, please refer to fig. 5, which is not described herein again.

As shown in FIG. 2, the scan chain test circuit 212 is an IC chip test circuit, and includes n +1(n ≧ 0 and integer) scan chains, the test data of which is Input through the Input Pad, and the output pin is output. The single scan chain test circuit may include: an Input pin (e.g., Input _0, Input _1, …, Input _ n), a plurality of flip-flops connected in series (e.g., D type flip-flop (DFF)), an Output pin (e.g., Output _0, Output _1, …, Output _ n), or any other type of scan chain test circuit of an integrated circuit chip, without limitation.

It should be noted that, as shown in fig. 2, the Input pins (e.g., Input _0, Input _1, …, Input _ n) of the scan chain test circuit 212 may be respectively coupled to the plurality of Input terminals of the data selector 206, and the data selector 206 controls to transmit the test data to the scan chain test circuit 212 (please refer to fig. 3 for details, which are not repeated herein). Therefore, when the chip is packaged on the printed circuit board, even if the Input pins (e.g., Input _0, Input _1, …, Input _ n) of the scan chain test circuit 212 are in poor contact due to being covered or soldered, the related signals can still be transmitted to the scan chain control circuit 200 through the wiring on the test circuit board, so that the scan chain control circuit 200 can be used to transmit the test data to the scan chain test circuit to realize the test requirement, thereby avoiding the adverse factors of the test and greatly improving the test efficiency.

It should be noted that the data selector 206 can also receive the register input data (Reg _ scan _ in [ n:0]) transmitted by the register controller 204, and input the register input data (Reg _ scan _ in [ n:0]) transmitted by the register controller 204 to the scan chain test circuit 212 under the action of the control signal terminal (this part is described with reference to fig. 3, and will not be described herein again). Alternatively, when the chip is packaged on a printed circuit board with scan chain test pins covered or in poor contact, the test data can still be input to scan chain test circuit 212 for testing using register input data (Reg _ scan _ in [ n:0 ]). Furthermore, the n +1bits of the register input data (Reg _ scan _ in [ n:0]) can use high and low level signals to implement the correspondence between the register input data (Reg _ scan _ in [ n:0]) and the scan chain test circuit (the content of this part is described with reference to fig. 3, which is not described herein again), so that the test is more flexible.

It should be noted that the Input pins (e.g., Input _0, Input _1, …, Input _ n) of the scan chain test circuit 212 shown in fig. 2 can also be connected to the corresponding scan chain test circuit. Those skilled in the art can also realize the need for testing by artificial external leads directly in the case where Input pins (e.g., Input _0, Input _1, …, Input _ n) of scan chain test circuit 212 are exposed. In order to make the drawing easier, fig. 2 does not show all the connections, but those skilled in the art can configure the connections according to the actual needs, and the invention is not limited thereto.

The input mode of the test data described in the above embodiment greatly eliminates uncertain factors of the test on the basis of meeting the original test requirements, improves the accuracy and flexibility of the test, reduces the test difficulty of testers, improves the test efficiency, and has certain technical effects.

The data selector 206 inputs test data (SCAN _ IN [ n:0]) to the SCAN chain test circuit 212; under the action of the shift clock signal (IP _ CLK), the mode test clock signal (DFT _ ON) and the mode SCAN enable clock Signal (SE), the test data (SCAN _ IN [ n:0]) is shifted IN the SCAN chain test circuit for scanning, and the test data (SCAN _ OUT [ n:0]) is Output to the register controller 204 through the Output Pad, and the register controller 204 records the test data and integrates (Reg _ SCAN _ OUT [ n:0]) for Output to the external device 202. More details of the shift clock signal (IP _ CLK), the mode test clock signal (DFT _ ON), and the mode scan enable clock Signal (SE) will be described in detail in fig. 4 and 5, and are not repeated herein.

With respect to the output test data (SCAN _ OUT [ n:0]), it should be noted that: the shift clock signal (IP _ CLK) controls the input test data (SCAN _ IN [ n:0]) to be shifted and scanned among a plurality of serially connected flip-flops (e.g., D type flip-flops (DFFs)) of the SCAN chain test circuit 212. The mode test clock signal (DFT _ ON) and the mode SCAN enable clock Signal (SE) control the input test data (SCAN _ IN [ n:0]) to be output after being tested by the SCAN chain test circuit 212. For the details of the related art that the mode test clock signal (DFT _ ON) and the mode SCAN enable clock Signal (SE) control the input test data (SCAN _ IN [ n:0]) to be output after being tested by the SCAN chain test circuit 212, please refer to the description part of FIG. 5, which will not be repeated herein.

Also, with respect to the output test data (SCAN _ OUT [ n:0]), it is noted that: as shown in FIG. 2, the Output pins (e.g., Output _0, Output _1, …, Output _ n) of the scan chain test circuit can be directly connected to register controller 204 and integrate the data Output for analysis by the designer. In some embodiments, a designer may also directly connect an external lead to an Output pin (e.g., Output _0, Output _1, …, Output _ n) and connect to a related test device (e.g., a visual analysis device such as a logic analyzer) to Output test data, and a person skilled in the art may configure the test device according to actual needs, which is not limited to the invention.

The external device 202 may be a visual test analysis device, such as: which may be a logic analyzer, an oscilloscope, or other type of test analysis equipment, without limitation.

The register controller 204 may also include an instruction register and/or a data register, and those skilled in the art may configure a plurality of D flip-flops and/or a plurality of gate structures according to actual use cases to meet the actual test circuit configuration requirements, but the invention is not limited thereto.

In some embodiments, the first level is a high level; the second level is a low level. In addition, although the first level and the second level in fig. 2 are represented by logic "1" and logic "0", respectively, they may be a power supply level (for example, the level is "VDD") and a ground potential (for example, the level is "0") of a transistor or any level that can be identified by the data selector 106 to select the test data from the first input terminal or the second input terminal, which is not limited by the invention.

In some embodiments, the scan chain control circuit may be applied to a Joint Test Action Group (JTAG) Debug interface and/or a Serial Wire Debug (SWD) interface, which is not limited in this respect.

Fig. 3 is a schematic diagram of a data selector according to an embodiment of the invention. The data selector 206 may be a combination of a plurality of data selectors. As shown in fig. 3, the data selector 206 is formed by combining n +1(n ≧ 0 and integer) data selectors, a first input terminal of the data selector 206 is coupled to the scan chain test circuit 212 and receives the pin input data (SI _0, SI _1 … SI _ n) of n +1(n ≧ 0 and integer) bits (bit) transmitted from the scan chain test circuit 212; a second input terminal and a third input terminal are coupled to the register controller 204, and receive the register input data (Reg _ SCAN _ in [ n:0]) of n +1(n ≧ 0 and integer) bits (bit) and the enable clock signal (SCAN _ EN) transmitted from the register controller 204. The third input terminal is a control signal terminal, and those skilled in the art can arbitrarily set the control signal terminal (the third input terminal) signal according to the actual configuration to make the data selector 206 identify whether to select the test data from the first input terminal or the second input terminal, which is not limited by the invention.

When the enable clock signal received by the data selector 206 from the register controller 204 is at a first level (e.g., high level "1"), the data selector 206 selects the n +1bits of register input data (Reg _ SCAN _ IN [ n:0]) as input data (SCAN _ IN [ n:0]) and inputs the data to the SCAN chain test circuit 212; when the enable clock signal received by the data selector 206 and transmitted from the register controller 204 is at a second level (e.g., a low level "0"), the data selector 206 selects the n +1bits of pin input data (SI _0, SI _1 … SI _ n) as input data (SCAN _ IN [ n:0]) to be input to the SCAN chain test circuit 212.

It should be noted that the n +1 scan chain test circuit includes n +1 input pins and n +1 output pins. As shown in fig. 2, Input _0 is an Input pin of the 0 th scan chain test circuit, and Output _0 is an Output pin of the 0 th scan chain test circuit; input _1 is an Input pin of the 1 st scan chain test circuit, and Output _1 is an Output pin … of the 1 st scan chain test circuit; and so on, Input _ n is an Input pin of the nth scan chain test circuit, and Output _ n is an Output pin of the nth scan chain test circuit. The input data of n +1 input pins included in the n +1 scan chain test circuits can be uniformly configured through the data selector 206, and the output data of n +1 output pins included in the n +1 scan chain test circuits can be uniformly output to the external device 202 through the register controller 204 and analyzed; the data input/output control of the scan chain test circuit 212 is realized, and the test flexibility is improved.

IN particular, the test data IN which the register input data (Reg _ SCAN _ IN [ n:0]), the pin input data (SI _0, SI _1 … SI _ n), the test input data (SCAN _ IN [ n:0]), the test output data (SCAN _ OUT [ n:0]), and the register output data (Reg _ SCAN _ OUT [ n:0]) are n +1bits (bits) corresponds to the n +1 SCAN chain test circuit. The data selector 206 is formed by combining n +1 data selectors, and corresponds to the n +1 scan chain test circuits.

The n +1bit (bits) of test data (SCAN _ IN [ n:0]) can select a single SCAN chain test circuit of the n +1 SCAN chain test circuits for testing. IN other words, the n +1bits (bits) of test data (SCAN _ IN [ n:0]) may test all of the n +1 SCAN chain test circuits, or may test only one and/or some SCAN chain test circuits of the n +1 SCAN chain test circuits. The configuration of the present invention is not limited to this, and the present invention can be configured by those skilled in the art according to the actual test requirements.

For example, assume that the scan chain test circuit 212 is a test circuit with 4 scan chains (including 0 th, 1 st, 2 nd, and 3 rd), and the 1 st and 3 rd scan chain test circuits are to be tested. When the third input terminal of the data selector 206 receives the enable clock signal transmitted by the register controller 204 and is at a first level (e.g., high level "1"), the data selector 206 selects the second input terminal test data (e.g., register input data (Reg _ SCAN _ IN [0101])) as the test input data (SCAN _ IN [0101]) to be input to the SCAN chain test circuit 212. When the third input terminal of the data selector 206 receives the enable clock signal transmitted by the register controller 204 and is at a second level (e.g., low "0"), the data selector 206 selects a first input terminal test data (e.g., pin input data (SI _0, SI _1 … SI _ n)) as a test input data (SCAN _ IN [0101]) to be input to the SCAN chain test circuit 212. More specifically, the high level test data "1" of the above test input data is inputted to the 1 st and 3 rd scan chain test circuits, and the low level test data "0" of the above test input data is inputted to the 0 th and 2 nd scan chain test circuits. IN this embodiment, the practical effect that when the chip is packaged on the pcb, the original input pins can still use the register input data (Reg _ SCAN _ IN [0101]) as the test input data (SCAN _ IN [0101]) to be input to the SCAN chain test circuit 212 after being covered can be further embodied, thereby greatly avoiding some adverse factors during the test process and improving the test efficiency.

When the third input terminal of the data selector 206 receives the enable clock signal transmitted by the register controller 204 and is at a second level (e.g., a low level "0"), the data selector 206 selects the first input terminal test data (e.g., pin input data (SI _0, SI _1, SI _2, and SI _3)) as test data (SCAN _ IN [0101]) to be input to the SCAN chain test circuit 212. More specifically, the high level test data "1" of the above test input data is inputted to the 1 st and 3 rd scan chain test circuits, and the low level test data "0" of the above test input data is inputted to the 0 th and 2 nd scan chain test circuits.

The test data (SCAN _ IN [0101]) writes a high level (for example, a high level "1") into the 1 st and 3 rd SCAN chain test circuits to be tested, and writes a low level (for example, a low level "0") into the 0 th and 2 nd SCAN chain test circuits 212 not to be tested.

The data selector 206 inputs test data (SCAN _ IN [0101]) to the SCAN chain test circuit 212; under the action of the shift clock signal (IP _ CLK), the mode test clock signal (DFT _ ON) and the mode SCAN enable clock Signal (SE), the test data (SCAN _ IN [0101]) is shifted and scanned IN the SCAN chain test circuit, and the test data (SCAN _ OUT [0101]) is Output to the register controller 204 through the Output Pad, and the register controller 204 records and analyzes the test data integration (Reg _ SCAN _ OUT [0101]) Output to the external device 202.

Fig. 4 is a schematic diagram of the clock controller 208 according to an embodiment of the invention. As shown in fig. 4, the clock controller 208 is coupled to the register controller 204, receives the enable clock signal (SCAN _ EN) and a register Shift clock signal (Shift _ CLK) transmitted by the register clock control module 214, and outputs the Shift clock signal (IP _ CLK) to a plurality of serially connected D-type flip-flops of the SCAN chain test circuit 212. Under the action of the shift clock signal (IP _ CLK), all the register test data (SCAN _ IN [ n:0]) inputted to the SCAN chain test circuit 212 through the data selector 206 are shifted to the next stage register as a whole, and the value of the last stage register is outputted to the register controller 204 and integrated (Reg _ SCAN _ out [ n:0]) to be outputted to the external device 202.

The register controller 204 is coupled to the external device 202, the external device 202 generates a Test Clock signal (Test Clock, TCK) in a Test state and transmits the Test Clock signal to the register controller 204, and the register controller 204 receives the Test Clock signal (Test Clock, TCK) and generates the enable Clock signal (SCAN _ EN). For example, when the tester of the external device 202 connects the external device 202 to the register controller 204, the tester enables the external device 202 to generate a continuous standard high-low level Test Clock signal (Test Clock, TCK) under Test, and transmits the Test Clock signal to the register controller 204; the register controller 204 generates the enable Clock signal (SCAN _ EN) after receiving one and/or more Clock cycles of the continuous standard high-low Test Clock signal (Test Clock, TCK). As shown in fig. 6, the register controller 204 generates the enable Clock signal (SCAN _ EN) two Clock cycles after receiving the Test Clock signal (TCK), which can be configured by those skilled in the art according to actual requirements without any limitation.

The register clock control module 214 and the clock controller 208 may be configured with a plurality of D flip-flops and/or a plurality of gate structures to meet the actual requirement. For example: the register Clock control module 214 further includes a plurality of D flip-flops 400, D flip-flops 402, and an Input Clock Gating (ICG) circuit 404. The Clock controller 208 further includes a plurality of D flip-flops 406, D flip-flops 408, an Input Clock Gating (ICG) circuit 410, a Clock oscillator (PLL) 412, a first data selector 414, and a second data selector 416. The first data selector 414 and the second data selector 416 may be an integrated data selector formed by combining a plurality of data selectors, and the clock oscillator (PLL) 412 may be disposed outside the clock controller 208 or disposed in a module separately, which can be configured by those skilled in the art according to actual requirements without any limitation.

As shown in fig. 4, a first input terminal of the first data selector 414 is coupled to the scan chain test circuit pin, and receives the pin shift clock (Ext _ clk) transmitted by the scan chain test circuit pin; the second and third input terminals are coupled to the register clock control module 214 of the register controller 204, receive the register Shift clock signal (Shift _ clk) transmitted by the register clock control module 214, and receive the enable clock signal SCAN _ SE transmitted by the register controller 204. Specifically, the first data selector 414 selects one of the Shift _ clk and the Ext _ clk to be transmitted to the second data selector 416 according to the enable clock signal SCAN _ SE received by the third input terminal (control terminal). When the third input terminal of the first data selector 414 receives the enable clock signal SCAN _ SE with a high level, the first data selector 414 selects to output the register shift clock signal to the second data selector 416; otherwise, the output pin shifts the clock to the second data selector 416. It should be noted that the enable clock signal SCAN _ SE can be directly transmitted from the register control 204 to the clock controller 208. In some embodiments, the clock signal can also be transmitted to the clock controller 208 through the register clock control module 214 in the register control 204, which is not limited to the present invention.

A first input terminal of the second data selector 416 receives a continuous functional clock signal (Func _ CLK) generated from a clock oscillator (Phase Locked Loop, PLL), a second input terminal receives a clock signal (Shift _ CLK or Ext _ CLK) transmitted by the first data selector 414, and a third input terminal (signal control terminal) is coupled to the mode controller 210 shown in fig. 2, receives a mode scan clock Signal (SE) transmitted by the mode controller 210, and finally outputs a Shift clock signal (IP _ CLK) to the scan chain test circuit 212 shown in fig. 2. Specifically, when the third input terminal of the second data selector 416 receives a mode scan clock Signal (SE) transmitted by the mode controller 210 of fig. 2 as a high level, the clock signal (Shift _ CLK or Ext _ CLK) transmitted by the first data selector 414 is selected as a Shift clock (IP _ CLK) and output to the scan chain test circuit. When the third input terminal of the second data selector 416 receives a mode scan clock Signal (SE) transmitted by the mode controller of fig. 2 at a low level, the first input terminal is selected to receive a continuous functional clock signal (Func _ CLK) generated by the clock oscillator (PLL) and output the continuous functional clock signal (Func _ CLK) as a shift clock (IP _ CLK) to the scan chain test circuit. It should be noted that, when the second data selector 416 selects the continuous functional clock signal (Func _ CLK) as the shift clock (IP _ CLK) to be output to the scan chain test circuit, it indicates that the scan chain test circuit is operating in the functional mode (Function mode) state at this time. When the second data selector 416 selects the register Shift clock signal (Shift _ CLK) to be output as the Shift clock (IP _ CLK) to the Scan chain test circuit, it indicates that the Scan chain test circuit is operating in the Scan mode (Scan mode) state at this time. When the second data selector 416 selects the pin shift clock (Ext _ CLK) as the shift clock (IP _ CLK) to be output to the scan chain test circuit, it indicates that the scan chain test circuit is operating in the Original test mode (Original test mode) state at this time. In other words, when the mode Scan clock signal SE is high, it indicates that the test mode (e.g., Scan mode or Original test mode) is currently enabled, and therefore the test clock (Shift _ CLK or Ext _ CLK) outputted by the first data selector 414 is selected as the Shift clock (IP _ CLK) to be outputted to the Scan chain test circuit. When the mode scan clock Signal (SE) is low, it indicates that the functional mode is currently enabled, and thus the functional _ CLK output by the first data selector 414 (i.e., a continuous functional clock signal functional _ CLK generated by the clock oscillator 412) is selected as the shift clock (IP _ CLK) to be output to the scan chain test circuit. Furthermore, when the mode scan clock signal SE is at a high level, which test mode is to be activated is determined according to the test mode signal (test _ mode), and for the detailed description of the mode status portion, please refer to the description of the relevant portion of table 1, which is not repeated herein.

Under the action of the shift clock signal (IP _ CLK), all the register test data (SCAN _ IN [ n:0]) inputted to the SCAN chain test circuit 212 through the data selector 206 are shifted to the next stage register as a whole, and the value of the last stage register is outputted to the register controller 204 and integrated (Reg _ SCAN _ out [ n:0]) to be outputted to the external device 202.

It should be particularly explained that the D-type flip-flop 406 of the clock controller 208 further includes an inverter (not shown) for inverting the TCK to ensure the timing consistency of the clocks therein, so as to improve the test performance. When the enable clock signal (e.g., the enable clock signal is "1") transmitted by the register clock control module 214, an inverter (not shown) included in the clock controller 208 inverts (inverts) the high-level enable clock signal and transmits the inverted signal to the D-type flip-flop 406, i.e., the high-level enable clock signal (e.g., the enable clock signal is "1") is converted into a low-level enable clock signal (e.g., the enable clock signal is "0") and transmitted to the clock gating circuit 410 of the clock controller 208 through the D flip-

flops

406 and 408. Locking the continuous function clock signal (Func _ clk) when the enable clock signal is high; otherwise, a stable continuous function clock signal (Func _ clk) is output. It should be noted that, the locking of the continuous functional clock signal (Func _ clk) may be interpreted as blocking the continuous functional clock signal (Func _ clk) from passing downward, or may be interpreted as locking the continuous functional clock signal (Func _ clk) at a high level or a low level without change, and the skilled in the art may interpret the locking accordingly according to the implemented circuit function, but the invention is not limited thereto.

Fig. 5 is a schematic diagram of the mode controller 210 according to an embodiment of the invention. As shown in fig. 5, the mode controller 210 is coupled to the register mode control module 216. The mode controller 210 receives an enable clock signal SCAN _ SE transmitted from the register mode control module 216 and outputs a test mode clock signal (DFT _ ON) and a mode SCAN enable clock Signal (SE) to the SCAN chain test circuit 212. The register mode control module 216 may also be configured with a plurality of D flip-flops to meet the actual requirement. For example: the register mode control module 216 further includes a D flip-flop 500 and a D flip-flop 502. A first input terminal of the fourth data selector 506 of the mode controller 210 receives a mode scan enable clock signal (SE _ i) from the original control scan chain test circuit; a second input terminal coupled to the register mode control module 216 for receiving a Scan enable backup signal (Scan _ en _ dp); the third input receives a Test mode signal (Test _ mode) from the original control scan chain Test circuit. A first input terminal of the third data selector 504 of the mode controller 210 receives a mode test clock signal (DFT _ i) from the original control scan chain test circuit; a second input terminal coupled to the register mode control module 216 for receiving a Scan mode backup signal (Scan _ mode _ dp); the third input receives a Test mode signal (Test _ mode) from the original control scan chain Test circuit. With respect to the mode scan enable clock signal (SE _ i), the Test mode signal (Test _ mode), and the mode Test clock signal (DFT _ i) of the original control scan chain Test circuit, it should be noted that: the mode scan enable clock signal (SE _ i) and the mode test clock signal (DFT _ i) of the Original control scan chain test circuit are mode control signals for the scan chain test circuit operating in the Original test mode, which can be provided by the relevant modules of the Original scan chain test circuit or by the JTAG port (not shown in fig. 5). The pull-up principle of the mode scan enable clock signal (SE _ i) and the mode test clock signal (DFT _ i) of the original control scan chain test circuit is similar to that of the test mode clock signal (DFT _ ON) and the mode scan enable clock Signal (SE). The mode scan enable clock signal (SE _ i) and the mode test clock signal (DFT _ i) of the original control scan chain test circuit are pulled up to a high level signal after receiving a plurality of clock signals of the TCK signal and the mode test clock signal (DFT _ i) is pulled up to a high level signal prior to the mode scan enable clock signal (SE _ i) of the original control scan chain test circuit. It should be noted here that the mode test clock signal (DFT _ i) is pulled up to a high level signal 1 clock cycle before the mode scan enable clock signal (SE _ i) of the original control scan chain test circuit. Those skilled in the art can configure the related mode signal control module of the original scan chain test circuit according to the product requirement, and the invention is not limited thereto. The Test mode signal (Test _ mode) is a control signal for controlling the scan chain Test circuit to operate in which mode state, and the specific functional details are described in relevant parts of table 1, and are not described herein again. The Test mode signal (Test _ mode) can be generated by an associated internal module, and a functional module (not shown in fig. 5) for generating or providing the Test mode signal (Test _ mode) is not shown in the present invention, and can be configured by those skilled in the art.

The test mode clock signal (DFT _ ON) and a mode SCAN enable clock Signal (SE) are signals that control the output of test input data (SCAN _ IN [ n:0]) as described IN FIG. 2 (SCAN _ OUT [ n:0]) after testing by SCAN chain test circuitry 212. In some embodiments, as shown in fig. 6, the test mode clock signal (DFT _ ON) is pulled to a high level signal by the mode controller 210 after receiving 3 clock signals of the TCK signal, and the mode scan enable clock Signal (SE) is pulled to a high level signal by the mode controller 210 after receiving 4 clock signals of the TCK signal, or the test mode clock signal (DFT _ ON) and the mode scan enable clock Signal (SE) are pulled to a high level signal by the mode controller 210 after a number of clock cycles of the TCK signal, and the test mode clock signal (DFT _ ON) is pulled to a high level signal before the mode scan enable clock Signal (SE). It should be noted that, the test mode clock signal (DFT _ ON) is pulled up to a high level signal 1 clock cycle before the mode scan enable clock Signal (SE), and those skilled in the art can configure the signal according to actual needs, and the invention is not limited thereto.

When the test mode clock signal (DFT _ ON) and a mode SCAN enable clock Signal (SE) are pulled high, the output data (SCAN _ OUT [ n:0] shown in FIG. 2) after the SCAN chain test circuit test can be output to the SCAN chain control circuit 200 shown in FIG. 2 and finally to an external device for analysis by a designer.

Specifically, when the Test mode signal (Test _ mode) is at a low level (for example, Test _ mode is "0"), the mode scan enable clock signal (SE _ i) from the original control scan chain Test circuit is selectively outputted as the mode scan enable clock Signal (SE) via the fourth data selector 506 in the mode controller 210, and the third data selector 504 selectively outputs the mode Test clock signal (DFT _ i) from the original control scan chain Test circuit as the mode Test clock signal (DFT _ ON). When the Test mode signal (Test _ mode) is at a high level (for example, Test _ mode is "1"), the mode Scan enable backup clock signal (Scan _ en _ dp) from the register mode control block 216 is selectively output as the mode Scan enable clock Signal (SE) via the fourth data selector 506 in the mode controller 210, and the third data selector 504 selects and outputs the mode Test backup clock signal (Scan _ mode _ dp) from the register mode control block 216 as the mode Test clock signal (DFT _ ON).

FIG. 6 is a diagram of a scan chain control circuit clock signal according to an embodiment of the invention. This will be explained in more detail below with reference to fig. 2, 4, 5 and 6. As shown in the first period T1 in fig. 6, when the tester of the external device 202 in fig. 2 connects the external device 202 to the register controller 204, and in the Test state, the tester makes the external device 202 generate a continuous standard high-low Test Clock signal (Test Clock, TCK) and transmits the Test Clock signal to the register controller 204; the register controller 204 generates a high enable Clock signal (e.g., SCAN _ EN is "1") after receiving one and/or more Clock cycles of the standard high-low Test Clock signal (TCK). At this time, the data selector 206 IN FIG. 2 inputs the test data (SCAN _ IN [ n:0]) to the SCAN chain test circuit 212. It should be noted that when the third input terminal (or referred to as the signal control terminal) of the data selector 206 receives the enable clock signal (e.g., SCAN _ EN is "1") with a high level, it selects the register input data (Reg _ SCAN _ IN [ n:0]) as the input data (SCAN _ IN [ n:0]) to be input to the SCAN chain test circuit 212. As shown IN FIG. 6, it is further noted that the input data (SCAN _ IN [ n:0]) before the time period T1 may be the pin input data SI _0, SI _ n, or data that is otherwise incoming (not of interest as shown IN FIG. 6).

Next, as shown in a second period T2 in fig. 6, when the register clock control module 214 in fig. 4 transmits a high-level enable clock signal SCAN _ EN (e.g., the enable clock signal is "1"), an inverter (not shown) included in the clock controller 208 in fig. 4 inverts (inverts) the high-level enable clock signal and transmits the inverted signal to the D-type flip-flop 406, i.e., the high-level enable clock signal (e.g., the enable clock signal is "1") is converted into a low-level enable clock signal (e.g., the enable clock signal is "0") and transmitted to the clock gating circuit 410 of the clock controller 208 via the D flip-

flops

406 and 408. The continuous function clock signal (Func _ clk) is latched when the enable clock signal is high. Next, as shown in a third period T3 in fig. 6, when the Test mode signal (Test _ mode) in fig. 5 is at a high level (e.g., Test _ mode is "1"), the third data selector 504 in the mode controller 210 selects to output the mode Test standby clock signal (Scan _ mode _ dp) from the register mode control block 216 as the mode Test clock signal (DFT _ ON), i.e., to output the mode Test clock signal at a high level. Next, as shown in a fourth period T4 in fig. 6, when the Test mode signal (Test _ mode) in fig. 5 is at a high level (for example, Test _ mode is "1"), the fourth data selector 506 in the mode controller 210 selects to output the mode Scan enable backup clock signal (Scan _ en _ dp) from the register mode control module 216 as the mode Scan enable clock Signal (SE), i.e., to output the mode Scan enable clock signal at a high level. Finally, as shown in a fifth period T5 in fig. 6, when the clock controller 208 in fig. 4 receives the enable clock signal (SCAN _ EN) and the SCAN enable clock Signal (SE) from the register clock control module 214 and the mode controller 210 at high levels, the clock controller 208 outputs a shift clock IP _ CLK signal having the same frequency as the register shift clock to the SCAN chain test circuit 212 shown in fig. 2 or switches the shift clock IP _ CLK of the clock controller 208 to the register shift clock output by the register controller 204 and transmits the register shift clock to the SCAN chain test circuit 212 shown in fig. 2. At this time, under the action of the shift clock signal (IP _ CLK), the test data (SCAN _ IN [ n:0]) inputted to the SCAN chain test circuit 212 during the first period T1 is shifted IN the SCAN chain test circuit for scanning, and the test data (SCAN _ OUT [ n:0]) is outputted to the register controller 204 IN FIG. 2 through the Output Pad of the SCAN chain test circuit during the fifth period T5, and the register controller 204 records the test data and integrates (Reg _ SCAN _ OUT [ n:0]) and outputs the test data to the external device 202 for the analysis of the tester. It should be noted that fig. 6 also depicts the signal diagram after several clock cycles, i.e., after the period T6 indicating the completion of the test. The clock signal diagram after the partial period of time varies due to the specific circuit structure, and fig. 6 is only a simple illustration and is not specifically illustrated and limited.

It should be noted that the above description in conjunction with the clock signal schematic of fig. 6 is only for the operation state of the scan chain control circuit when the enable clock signal is high, and will be described in detail in conjunction with table 1.

As shown in table 1, the Scan chain control circuit can operate in three modes, namely Scan mode (Scan mode), Original test mode (Original test mode), and functional mode (Function mode). After the scan chain control circuit turns on external device 202 and receives a number of TCK clock cycles transmitted by external device 202 (two clock cycles as shown in fig. 6). When the register controller 204 in the SCAN chain control circuit 200 shown in fig. 2 generates a high level enable clock signal (SCAN _ EN). When the clock controller 208 shown in fig. 4 receives the enable clock signal (SCAN _ EN) at the high level, the data selector 414 in fig. 4 selects the register shift clock (shift _ clk) to output to the data selector 416. The register controller 204 shown in fig. 5 generates the Scan _ mode _ dp and Scan _ en _ dp signals high accordingly.

Further, when the Test mode signal (Test _ mode) is at a high level, the data selector 506 in the mode controller 210 selects a Scan _ en _ dp signal at a high level to be output, and the data selector 504 in the mode controller 210 selects a Scan _ mode _ dp signal at a high level to be output, as shown in fig. 5. It should be noted that in table 1, the outputs of the data selector 506 and the data selector 504 are labeled only Scan _ mode _ dp and Scan _ en _ dp signals, but not labeled as high or low. It should be particularly explained that, when the enable clock signal (SCAN _ EN) and the Test mode signal (Test _ mode) are both high, the SCAN _ mode _ dp and the SCAN _ EN _ dp must be high and there is no low state, but those skilled in the art can design them according to their own requirements, so the SCAN _ mode _ dp and the SCAN _ EN _ dp signal states are not labeled in table 1.

Referring back to FIG. 4, when data selector 416 in FIG. 4 receives the SE signal (which may be a high Scan _ en _ dp signal) with a high level, data selector 416 in FIG. 4 selects shift _ clk to output to the Scan chain test circuit. At this time, it is shown that the Scan chain control circuit operates in Scan mode, and the test data input to the Scan chain test circuit is register input data Reg _ Scan _ in [ n:0 ].

When the register controller in the SCAN chain control circuit 200 shown in fig. 2 generates a low level enable clock signal (SCAN _ EN). When the clock controller 208 shown in fig. 4 receives the enable clock signal (SCAN _ EN) of the low level, the data selector 414 in fig. 4 selects the pin shift clock (Ext _ clk) to be output to the data selector 416. At this time, it is to be noted that the register controller 204 shown in fig. 5 may consider that the Scan _ mode _ dp and the Scan _ en _ dp signals are not generated or that the Scan _ mode _ dp and the Scan _ en _ dp signals of low level are generated.

Further, when the Test mode signal (Test _ mode) is low, the data selector 506 in the mode controller 210 shown in fig. 5 selects the SE _ i signal output of high level, and the data selector 504 in the mode controller 210 selects the DFT _ i signal output of high level. It should be noted that the outputs of the data selector 506 and the data selector 504 in table 1 only mark the SE _ i and DFT _ i signals and do not mark the signals as high or low. It should be specifically explained that SE _ i and DFT _ i are pulled high by other circuit blocks (not shown) shown in fig. 5 at this time.

Referring back to fig. 4, when the data selector 416 in fig. 4 receives the SE signal (which may be a high SE _ i signal) with a high level, the data selector 414 in fig. 4 selects the pin shift clock (Ext _ clk) to output to the scan chain test circuit. At this time, it is shown that the scan chain control circuit operates in the Original test mode state, and the test data input to the scan chain test circuit is the register input data SI _0, SI _1 … SI _ n.

Finally, it should be explained that when the register controller in the SCAN chain control circuit 200 shown in fig. 2 generates a low level enable clock signal (SCAN _ EN). When the clock controller 208 shown in fig. 4 receives the enable clock signal (SCAN _ EN) of the low level, the data selector 414 in fig. 4 selects the pin shift clock (Ext _ clk) to be output to the data selector 416. Further, when the Test mode signal (Test _ mode) is low, the

data selectors

506 and 504 in the mode controller 210 shown in fig. 5 receive the low-level SE _ i signal and DFT _ i signal output by other circuit blocks (not shown) shown in fig. 5. It should be particularly explained that, at this time, the low level SE _ i and DFT _ i indicate that no test is performed, and normal Function verification of the chip is performed, i.e. the chip enters the Function mode, so that the test data is unknown according to the determination of the chip test Function.

It should be noted that the three test mode states can be freely switched, i.e. one test mode state can be switched to one of the other two test mode states after the test mode state is completed. As shown in fig. 6, which represents that the Scan chain control circuit 200 is operating in the Scan mode (Scan mode) state at this time, the test data (Reg _ Scan _ out [ n:0]) is completed to be output to the external device 202 after T5 period for several clock cycles. The SCAN chain control circuit 200 of the present invention can perform a Reset (Reset) operation, and all clock signals (e.g., SCAN _ EN goes low, Func _ CLK is synchronized with the PLL clock (also known as unlocked or blocked), DFT _ ON and SE go low, Shift _ CLK goes low, IP _ CLK is synchronized with the PLL clock, etc.) are restored to the clock state before T1. Next, the scan chain control circuit 200 may restart to operate in the original test mode state or the operating mode state, i.e., to implement the switching of the scan chain control circuit 200 from the scan mode state to the original test mode state or the switching of the scan mode state to the functional mode state. The above description is only for briefly describing the switching between the scan chain control circuit mode states of the present invention, but the present invention is not limited thereto.

TABLE 1

Fig. 7 is a schematic diagram of a scan chain control circuit flow according to an embodiment of the invention. The method mainly comprises the following steps: in step S702, a continuously stable test clock signal TCK is transmitted to the register controller 204 via the external device 202 shown in fig. 2, and the register controller 204 of the SCAN chain control circuit 200 generates a high-level enable clock signal (SCAN _ EN ═ 1) or a low-level enable clock signal (SCAN _ EN ═ 0), i.e., enables the SCAN mode or the original test mode.

IN step S704, the SCAN chain control circuit 200 selectively outputs a test data SCAN _ IN [ n:0] to the SCAN chain test circuit 212 according to the high-level enable clock signal or the low-level enable clock signal. As shown in FIG. 2, when the enable clock signal is high (e.g., the enable signal is "1"), the data selector 206 selects the test data (Reg _ scan _ in [ n:0]) transmitted from the register controller 204 to the second input terminal to be input as the test data to the scan chain test circuit 212. When the enable clock signal is low (e.g., the enable signal is "0"), the data selector 206 selects the test data (SI _0, SI _1 … SI _ n) delivered to the first input terminal by the scan chain test circuit 212 as the test data to be input to the scan chain test circuit 212.

In step S706, clock controller 210 of scan chain control circuit 200 triggers test data to be shifted in scan chain test circuit 212. As shown in fig. 4, because the clock controller 210 receives a high level enable signal when the enable signal is high (e.g., the enable signal is "1"). The first data selector 414 of the clock controller 210 selects the register Shift clock signal (Shift _ clk) transmitted by the register clock control module 214 received by the second input terminal to transmit to the second data selector 416. The second data selector 416 of the clock controller 210 selects a register Shift clock signal (Shift _ CLK) received by the second input terminal and transmitted by the first data selector 414 as a Shift clock signal (IP _ CLK) to be output to the scan chain test circuit 212. When the enable signal is low (e.g., the enable signal is "0"), the clock controller 210 receives a low enable signal. The first data selector 414 of the clock controller 210 selects the pin shift clock signal (Ext _ clk) received by the first input terminal and transmitted from the scan chain test circuit 212 to transmit to the second data selector 416. The second data selector 416 of the clock controller 210 selects a pin shift clock signal (Ext _ CLK) received by the second input terminal and transmitted by the first data selector 414 as a shift clock signal (IP _ CLK) to be output to the scan chain test circuit 212.

In step S708, the test data of all the scan chain test circuits 212 is output. When the enable clock signal is high and the test mode signal is low or the enable clock signal is low and the test mode signal is high, all the register data in the SCAN chain test circuit 212 will be shifted to the next register stage by stage under the action of the shift clock (shift _ clk) or (Ext _ clk), and the test data (SCAN _ OUT [ n:0]) is output through the output pin of the SCAN chain test circuit 212, and the test data (Reg _ SCAN _ OUT [ n:0]) is output to the test access port through the register controller 204 to the external test equipment 202.

In step S710, steps S706 and S708 are repeated until all data is shifted and output to the external device 202.

The principle of testing the scan chain control circuit is described in conjunction with fig. 1 to 7, and how the scan chain control circuit achieves testing flexibility when a chip is packaged on a PCB board will be explained in detail below. FIG. 8 is a schematic diagram of a scan chain test circuit packaged on a PCB according to an embodiment of the invention. As shown in FIG. 8, only integrated design circuits IC1, IC2 to be tested and their corresponding scan chain test circuits 212-1, 212-2, 212-3, 212-4 (shown in the dashed boxes in the figure, the rectangular pattern is illustrated as a D-flip-flop or other test basic cell circuit structure, the invention is not limited thereto), PAD pins and scan chain control circuit 200 are shown. It should be noted here that the integrated design circuits IC1, IC2 to be tested as shown in the figures only show the respective two scan chain test circuits 212-3, 212-4 and 212-1, 212-2. However, the number of the integrated design circuits to be tested and the number of the scan chain test circuits may be determined according to actual test requirements or corresponding test requirements such as product functions of the integrated design circuits to be tested, and a person skilled in the art may design the integrated design circuits according to actual situations. In addition, when a test circuit (also shown as including a scan chain control circuit and a scan chain test circuit) is packaged on a PCB, PAD pins (i.e., input/output pins shown in fig. 2) for the scan chain test are packaged on the PCB. As shown in fig. 8, the pins packaged on the PCB board are represented as PAD pins as hatched rectangles in the figure, but those skilled in the art should not confuse the two pins. Alternatively, in order to distinguish the PAD pin shown in fig. 2 from the PAD pin shown in fig. 8 and facilitate understanding, the PAD pin on the PCB may also be referred to as a lead interface or a lead terminal, and the lead terminal will be described below when the PAD pin on the PCB is described. In addition, for convenience of illustration, fig. 8 only shows the scan chain control circuit 200, and regarding the specific circuit structure of the scan chain control circuit 200 and the scan chain test circuits 212-1, 212-2, 212-3, 212-4, the scan chain control circuit 200 controls the specific details of the scan chain test circuits 212-1, 212-2, 212-3, 212-4, please refer to the descriptions of fig. 2 to fig. 5, which will not be described in detail herein. It should be noted that, as shown in fig. 8, the Input pins (it should be understood that the Input _0, Input _1, …, and Input _ n pins shown in fig. 2, and not shown in fig. 8) of the scan chain test circuits 212-1, 212-2, 212-3, and 212-4 are all directly connected to the respective scan chain test circuits 212-1, 212-2, 212-3, and 212-4, but in fig. 2, the Input pins (Input _0, Input _1, …, and Input _ n) of the scan chain test circuit 212 are not directly connected to the scan chain test circuits. It should be explained here that a person skilled in the art can design the circuit connections according to the connection shown in fig. 2 and also according to the connection shown in fig. 8. For convenience of explaining the circuit principle and illustration of the present invention, fig. 2 is a diagram mainly explaining the circuit design manner in which the scan chain control circuit controls the scan chain test circuit, so the Input pins (Input _0, Input _1, …, Input _ n) of the scan chain test circuit 212 are not directly connected to the scan chain test circuit, and the present invention is not limited thereto.

As shown in FIG. 8, when test circuits (also shown as including scan chain control circuits and scan chain test circuits) are packaged on a PCB board, the two scan chain test circuits 212-3, 212-4 and 212-1, 212-2 of the integrated design circuits IC1, IC2, respectively, are shown as shaded rectangles on the PCB board at the terminals.

At this time, if it is required to test IC1 and/or IC2, it is only necessary to import the data to be tested or export the test data (not shown to distinguish the input terminal and the output terminal, but the invention is not limited thereto) from the lead terminals 212-3 and 212-4 and/or 212-1 and 212-2, respectively, for the designer to analyze the chip design. However, as integrated design circuits are developed, chip testing is faced with many problems when chips are packaged from individual dies (or die) on a wafer to a PCB board. On one hand, each scan chain test circuit is respectively provided with two input pins and two output pins, when the number of the scan chain test circuits is too large (for example, when the number of the scan chain test circuits is 50, 100 pins are provided), the test is respectively carried out from the lead wire of the lead wire end of each scan chain test circuit, so that the test difficulty is greatly increased, and the development test cost is increased. On the other hand, when packaged on a PCB, the package may cause a connection failure of the lead terminals, and may also cause a contact failure such as short circuit and/or open circuit during testing, which may result in a decrease in accuracy of the test result and be unfavorable for analysis.

Based on the above analysis, the input/output pins of all scan chain test circuits are uniformly coupled to the scan chain control circuit as shown in fig. 8 (the input/output pins of scan chain test circuits 212-1, 212-2, 212-3, 212-4 in the dashed line box shown in fig. 8 are uniformly coupled to the scan chain control circuit), and the input of the data to be tested or the output of the test data are controlled via the scan chain control circuit (the input and the output are not shown to be distinguished, but the invention is not limited thereto). The scan chain control circuit is connected to an external device through a test Interface (shown as an Interface in fig. 8).

In some embodiments, the scan chain control circuit may be packaged in a Ball Grid Array (BGA), a flip-chip (flip-chip), a Land Grid Array (LGA), or the like, which is not limited in the disclosure.

Specifically, after the die is packaged on the PCB, if the chip design is relatively simple, the number of the lead terminals is small, and the package quality is good, the test can be performed by directly connecting the lead terminals to the external leads. If the chip design is complicated, the number of the lead terminals is large, or whether the packaging quality is good or not is uncertain (poor contact faults such as short circuit and/or open circuit and the like are caused during testing), the test can be controlled by a scan chain control circuit without passing through the lead terminals. In other words, the scan chain control circuit directly performs chip testing through the interface on the test circuit board without performing testing through external leads of the lead terminals. The SCAN chain control circuit can use the pin input data (SCAN _ IN [ n:0]) to input the test data into the SCAN chain test circuit, and after the test is carried out under the action of the pin shift clock (Ext _ clk), the test data (Scan _ out [ n:0]) after the test is finished is output to the external equipment for the analysis of designers. At this time, the scan chain control circuit is called to operate in an Original test mode. More specifically, the scan chain control circuit may also use the register input data (Reg _ scan _ in [ n:0]), input the test data to the scan chain test circuit under the action of the register Shift clock signal (Shift _ clk) for testing, and then output the test data (Reg _ scan _ out [ n:0]) after testing to the external device for the designer to analyze. At this time, the Scan chain control circuit is called to operate in a Scan mode (Scan mode). Furthermore, after the chip verification test is completed, the scan chain control circuit can be turned off. At this time, the scan chain control circuit is called to operate in a functional mode. For a description of this part, please refer to the description of the parts shown in fig. 2 to fig. 7, which is not repeated herein.

The SCAN chain control circuit can input test data into the SCAN chain test circuit by using pin input data (SCAN _ IN [ n:0]) and output the test data (Scan _ out [ n:0]) after testing under the action of a pin shift clock (Ext _ clk) to an external device. It should be noted that the pin input data (SCAN _ IN [ n:0]) is test data transmitted from the input pin of the SCAN chain test circuit (the pin should be understood as the input pin of the SCAN chain test circuit shown IN fig. 2, but not as the pin on the PAB version) to the SCAN chain control circuit, and transmitted to the SCAN chain test circuit via the SCAN chain control circuit to complete the test (for this part, please refer to the description of fig. 3, which is not described herein again). Finally, the tested test data (Scan _ out [ n:0]) can be directly output to the external device through the lead terminal on the test circuit board, or the tested test data (Scan _ out [ n:0]) can be transmitted to the Scan chain control circuit and output to the external device through the Interface. Specifically, when the test data (Scan _ out [ n:0]) after the test is output, there are two selection methods. First, the output can be directly to the external device through the lead terminal lead on the PCB board. Second, the test data (Scan _ out [ n:0]) after the test can be output to the Scan chain control circuit and output to the external device through the Interface. Regarding the case of outputting the test data, because the principle is similar to the case of inputting the test data, a person skilled in the art can modify the way of outputting the data based on the principle of inputting the test data according to the present invention, and the present invention does not limit the way of outputting the data.

The scan chain control circuit may also use the register input data (Reg _ scan _ in [ n:0]) and input the test data to the scan chain test circuit under the action of the register Shift clock signal (Shift _ clk) to perform the test, and then output the test data (Reg _ scan _ out [ n:0]) after the test is completed to the external device. It should be noted that the register input data is test data generated by a series of registers in the scan chain control circuit (e.g. register input data (Reg _ scan _ in [ n:0]) in fig. 2, but a specific register is not shown) and is transmitted to the scan chain test circuit via the scan chain control circuit to complete the test (for the content, please refer to the description of fig. 2 and fig. 6, which is not described herein again). Finally, the tested test data (Reg _ scan _ out [ n:0]) can be directly output to the external device through the lead terminal on the test circuit board, or the tested test data (Reg _ scan _ out [ n:0]) can be transmitted to the scan chain control circuit and output to the external device through the Interface. Regarding the output principle after the test of the register input data (Reg _ Scan _ in [ n:0]) is completed, the explanation of the output principle is similar to that of the test data (Scan _ out [ n:0]) after the test is completed, and the description thereof is omitted.

In summary, when the chip is packaged on the PCB, the scan chain control circuit of the present invention can directly perform chip testing through the wiring (also called interface) on the test circuit board without external leads through the lead terminals. Meanwhile, the SCAN chain control circuit can select pin input data (SCAN _ IN [ n:0]) to be tested and also select register input data (Reg _ SCAN _ IN [ n:0]) to be tested. The method not only improves the accuracy of the test, but also improves the flexibility of test selection, and can greatly improve the accuracy and efficiency of the test.

The present invention has been described in terms of the preferred embodiments, so that those skilled in the art can better understand the present invention in various aspects, but various modifications and variations can be made to the present invention without departing from the spirit and scope of the present invention. Thus, it is intended that the present invention cover the modifications and variations of this invention provided they come within the scope of the appended claims and their equivalents.

Claims

1. A scan chain control circuit, characterized in that,

The chip test is performed through the interface on the test circuit board without the need to connect the lead through the lead terminal.

When the above-mentioned scan chain control circuit is under the action of the pin shift clock, the scan chain control circuit inputs the pin input data to the scan chain test circuit and outputs the test data after the test is completed;

When the above-mentioned scan chain control circuit is under the action of the register shift clock signal, the scan chain control circuit inputs the register input data to the scan chain test circuit and outputs the test data after the test is completed.

2 . The scan chain control circuit of claim 1 , wherein the scan chain control circuit can be applied to a joint test work group debug interface and/or a serial wire debug interface. 3 .

3 . The scan chain control circuit of claim 1 , wherein the input pins of the scan chain test circuit are uniformly coupled to the scan chain control circuit. 4 .

4 . The scan chain control circuit of claim 3 , wherein the pin input data is collectively transmitted from the scan chain test circuit pins to the scan chain control circuit and then to the scan chain test circuit. 5 .

5 . The scan chain control circuit of claim 3 , wherein the scan chain control circuit can generate the register input data through the scan chain control circuit and transmit the data to the scan chain test circuit. 6 .

6 . The scan chain control circuit of claim 1 , wherein output pins of the scan chain test circuit are collectively coupled to the scan chain control circuit. 7 .

7 . The scan chain control circuit of claim 4 , wherein the test data completed by the pin input data test transmitted by the scan chain test circuit pins are collectively transmitted to the scan chain control circuit through the test circuit. 8 . interface output on the board.

8. The scan chain control circuit as claimed in claim 5, wherein the test data generated by the scan chain control circuit and the completed test data of the register input data are transmitted to the scan chain control circuit through an interface on the test circuit board output.

9 . The scan chain control circuit of claim 1 , wherein the scan chain control circuit tests the pin input data transmitted from the scan chain test circuit pins under the action of a pin shift clock. 10 . Output the test data that has been tested.

10 . The scan chain control circuit according to claim 9 , wherein when the scan chain control circuit operates in an original test mode, the scan chain control circuit performs the scanning operation under the action of a pin shift clock. 11 . After the above-mentioned pin input data transmitted by the pins of the chain test circuit are tested, the test data that has been tested is output.

11. The scan chain control circuit according to claim 10, wherein the scan chain control circuit tests the register input data generated by the scan chain control circuit under the action of a register shift clock and then completes the test. Test data output.

12 . The scan chain control circuit of claim 11 , wherein when the scan chain control circuit operates in a scan mode, the scan chain control circuit controls the scan chain under the action of a register shift clock. 13 . After the above-mentioned register input data generated by the circuit is tested, the test data that has been tested is output.

13 . The scan chain control circuit of claim 12 , wherein when the scan chain control circuit operates in the original test mode, the scan chain control circuit can be switched to the scan mode by a reset operation and restarting the scan chain control circuit. 14 .

14. The scan chain control circuit of claim 12, wherein when the scan chain control circuit operates in the scan mode, the scan chain control circuit can be switched to the original test mode by a reset operation and restarting the scan chain control circuit.