CN118535516A - Car gauge microprocessor circuit - Google Patents
Car gauge microprocessor circuit Download PDFInfo
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- CN118535516A CN118535516A CN202411013655.2A CN202411013655A CN118535516A CN 118535516 A CN118535516 A CN 118535516A CN 202411013655 A CN202411013655 A CN 202411013655A CN 118535516 A CN118535516 A CN 118535516A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F15/00—Digital computers in general; Data processing equipment in general
- G06F15/16—Combinations of two or more digital computers each having at least an arithmetic unit, a program unit and a register, e.g. for a simultaneous processing of several programs
- G06F15/163—Interprocessor communication
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
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Abstract
The invention provides a vehicle-mounted microprocessor circuit, which comprises a first core, a second core and a reset module, wherein the first core and the second core respectively comprise a first register and a second register, a system reset signal and a power-on reset signal are generated in the reset module, the first output end directly outputs the system reset signal, a reset signal switching circuit is also arranged in the reset module, the reset signal switching circuit is connected with the second output end and is used for receiving the system reset signal and the power-on reset signal, the power-on reset signal is selectively output from the second output end when the vehicle-mounted microprocessor circuit is in a test mode, and the system reset signal is selectively output from the second output end when the vehicle-mounted microprocessor circuit is in a common working mode. The vehicle-mounted microprocessor circuit has good reliability and safety.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to a vehicle-mounted microprocessor circuit.
Background
Currently, car-gauge Microprocessors (MCUs) are beginning to employ Lockstep Core designs in order to improve the reliability and security of Core operation. The lock-step Core design is that two cores are arranged in the MCU, one is a Master Core (Master Core) and the other is a detection Core (Checker Core), the two cores execute the same instruction sequences, and the execution results are compared, which is also called lock-step checking. If the comparison conclusion is that the execution results of the MCU system and the MCU system are consistent, the MCU system is indicated to normally operate and can work continuously; if the comparison result shows that the execution results of the two are inconsistent, the MCU system is possibly failed, the MCU system sends out a fault report and can further take corresponding measures, such as system reset or other fault safety operation.
However, technicians find that false alarm sometimes occurs, namely, the MCU system sends out a fault report, but researches find that the MCU system has no problem. Further research and analysis show that the occurrence of false alarm is related to two factors, namely, delay execution of the detection core relative to the main core in lock step checking and a reset mechanism of a register.
The reset used by the current MCU can be broadly divided into two major categories, one major category is system reset (SYSTEM RESET) and the other major category is power-on reset (porreset). Of course, the general class of system resets also includes a number of different specific reset types, such as Core error resets, watchdog (WDOG) resets, software resets, and the like. In general, a system reset is performed when the MCU encounters some specific error. And the power-on reset is only carried out when the MCU is required to be powered on and powered off, and no matter what reset is carried out, a reset module in the MCU can generate a corresponding reset signal to be sent to the core to reset logic in the core. The registers used by the cores are reset by adopting the two main types correspondingly, wherein more registers are reset by adopting a system, namely, are reset by receiving a system reset signal, and the other registers are reset by adopting a power-on reset, namely, are reset by only receiving a power-on reset signal. Taking the Core exported by the ARM company, which is called as ARM Core for short, the registers for power-on reset include a Debug related register (Debug register for short) and a EPPB bus control related register (EPPB register for short). The purpose of the Debug registers using a power-on reset is that the system reset does not clear the values of these Debug registers during the Debug (i.e. in test mode at this time). The EPPB registers are registers for implementing some system control according to the design requirements of the MCU.
Based on the above-mentioned reset mechanism of the register, in addition to the lock-step check, although the two cores execute the same instruction sequence, the detecting core accepts the instruction delayed by one delay unit (the main core accepts the instruction without delay, but the execution result of the main core is delayed by one delay unit and then compared with the execution result of the detecting core, and at this time, the execution results of the two cores should be identical in theory). Therefore, in a special case, immediately after the main core executes an instruction (the detecting core does not execute the instruction yet, this period is also called a synchronization period), the MCU resets the system, so that the detecting core resets, the instruction just executed by the main core just before will be lost, that is, the detecting core will not execute the instruction and will not send out data update to the register, but at this time, the register of the main core has already updated data because the execution of the instruction has been completed, so that the lock step check will give a comparison conclusion that the execution results of the two are inconsistent, and then send out a fault report, but at this time, the MCU does not actually have a fault. Therefore, this problem is very much to be solved to perfect the reliability and safety of the MCU.
Disclosure of Invention
The invention aims to provide a vehicle-mounted microprocessor circuit which is good in reliability and safety.
In order to achieve the above purpose, the present invention provides the following technical scheme:
The invention provides a vehicle-mounted microprocessor circuit, which comprises a first core, a second core and a reset module, wherein the first core and the second core have the same structure, jointly form a lock step core, respectively comprise a first register and a second register, respectively have a first input end and a second input end, the first input end is connected with the first register, and the second input end is connected with the second register; the reset module is provided with a first output end and a second output end, the first output end of the reset module is connected with the first input end of the first core and the first input end of the second core, and the second output end of the reset module is connected with the second input end of the first core and the second input end of the second core; the system reset signal and the power-on reset signal are generated in the reset module, the first output end directly outputs the system reset signal, the reset module is internally provided with a reset signal switching circuit, the reset signal switching circuit is connected with the second output end and receives the system reset signal and the power-on reset signal, the power-on reset signal is selectively output from the second output end when the vehicle-mounted microprocessor circuit is in a test mode, and the system reset signal is selectively output from the second output end when the vehicle-mounted microprocessor circuit is in a normal working mode.
In an embodiment, the reset signal switching circuit includes a first selector, a first selection register, where the first selector has a first input end, a second input end, an output end, and a selection end, the first input end and the second input end of the first selector receive the system reset signal and the power-on reset signal respectively, the output end of the first selector is used as the second output end of the reset module, and the first selection register is connected with the selection end of the first selector and can be written into different values by the first core or the second core to send to the first selector.
In an embodiment, the reset signal switching circuit includes a first selector, a system state detection module, where the first selector has a first input end, a second input end, an output end and a selection end, the first input end and the second input end of the first selector receive the system reset signal and the power-on reset signal respectively, the output end of the first selector is used as the second output end of the reset module, the input end of the system state detection module receives a state signal representing the state of the microprocessor, and the output end of the system state detection module is connected with the selection end of the first selector and generates different values according to the state signal and sends the different values to the first selector.
In an embodiment, the reset signal switching circuit includes a first selector, a second selector, a first selection register, a second selection register, and a system state detection module, where the first selector and the second selector each have a first input end, a second input end, an output end, and a selection end, the first input end and the second input end of the first selector respectively receive the system reset signal and the power-on reset signal, the output end of the first selector is used as a second output end of the reset module, the first selection register is connected with the first input end of the second selector, and can be written with different values by the first core or the second core and sent to the second selector, the input end of the system state detection module receives a state signal representing a state of the microprocessor, the output end of the system state detection module is connected with the second input end of the second selector, generates different values according to the state signal and sends the second core to the second selector, and the second core is connected with the second selector and can not send different values to the second core or the second selector.
In one embodiment, the status signal includes a field phase signal that characterizes a life cycle of the chip in a field use phase.
In an embodiment, the status signal includes a field stage signal that characterizes a life cycle of the chip in a field use stage and a development stage signal that characterizes a life cycle of the chip in a development stage, or the status signal includes a field stage signal that characterizes a life cycle of the chip in a field use stage and a failure stage signal that characterizes a life cycle of the chip in a failure analysis stage; the system state detection module comprises an NOT gate and an OR gate, wherein the development stage signal or the failure stage signal is sent to the NOT gate, the NOT gate output and the field stage signal are both sent to the OR gate, and the output end of the OR gate is used as the output end of the system state detection module.
In an embodiment, the status signal includes a test request signal indicating a test request status and a test request response signal indicating a test request response status, the system status detection module includes a nand gate, the test request signal and the test request response signal are both sent to the nand gate, and an output end of the nand gate is used as an output end of the system status detection module.
In an embodiment, the status signals include a field phase signal representing a life cycle of a chip in a field use phase, a test request signal representing a test request state, and a test request response signal representing a test request response state, the system status detection module includes a nand gate and an and gate, the test request signal and the test request response signal are both sent to the nand gate, the output of the nand gate and the field phase signal are both sent to the and gate, and the output end of the and gate is used as the output end of the system status detection module.
In an embodiment, the vehicle microprocessor circuit has only the first core or the second core.
In an embodiment, the second register includes a Debug register, EPPB registers, DSCHR registers.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
The reset module is internally provided with the reset signal switching circuit, and when the microprocessor is in a test mode, a power-on reset signal is sent out through the second output end of the reset module, namely the second register receives power-on reset and does not receive system reset, so that the test is not influenced; when the vehicle-mounted microprocessor circuit is in the normal working mode, the system reset signal is sent out through the second output end of the reset module, namely the second register receives the system reset and does not receive the power-on reset, so that when the lock step inspection is performed, even if the system reset occurs in the synchronous period, the second registers of the two cores are reset, the data of the two cores are kept consistent, the comparison conclusion of the lock step inspection is that the two cores are consistent, a fault report cannot be mistakenly sent out, the reliability and the safety of the work of the microprocessor (core) are perfected, and the reliability and the safety are good.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a vehicle microprocessor circuit according to a first embodiment of the present invention;
FIG. 2 is a schematic diagram of a first embodiment of the reset signal switching circuit of FIG. 1;
FIG. 3 is a schematic diagram of a second embodiment of the reset signal switching circuit of FIG. 1;
FIG. 4 is a schematic diagram of a third embodiment of the reset signal switching circuit of FIG. 1;
FIG. 5 is a schematic diagram of a first embodiment of the system status detection module shown in FIGS. 3 and 4;
FIG. 6 is a schematic diagram of a second embodiment of the system status detection module of FIGS. 3 and 4;
fig. 7 is a schematic diagram of a third embodiment of the system status detection module in fig. 3 and 4.
Detailed Description
The following description of the technical solutions in the embodiments of the present invention will be clear and complete, and it is obvious that the described embodiments are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention. It should be noted that the following description order of the embodiments is not intended to limit the preferred order of the embodiments of the present invention. In the following embodiments, the descriptions of the embodiments are focused on, and for the part that is not described in detail in a certain embodiment, reference may be made to the related descriptions of other embodiments.
Referring to fig. 1, a first embodiment of the present invention provides a vehicle-mounted microprocessor circuit, which includes a first core, a second core and a reset module, wherein the first core and the second core have the same structure, together form a lock step core, and each of the first core and the second core includes a first register and a second register, each of the first register and the second register has a first input end and a second input end, the first input end is connected with the first register, and the second input end is connected with the second register; the reset module is provided with a first output end and a second output end, the first output end of the reset module is connected with the first input end of the first core and the first input end of the second core, and the second output end of the reset module is connected with the second input end of the first core and the second input end of the second core; the system reset signal and the power-on reset signal are generated in the reset module, the first output end directly outputs the system reset signal, the reset module is internally provided with a reset signal switching circuit, the reset signal switching circuit is connected with the second output end and receives the system reset signal and the power-on reset signal, the power-on reset signal is selectively output from the second output end when the vehicle-mounted microprocessor circuit is in a test mode, and the system reset signal is selectively output from the second output end when the vehicle-mounted microprocessor circuit is in a normal working mode.
First, the first register and the second register of the present invention are not intended to limit the number of each to one. In practice, the first register and the second register are each a plurality of registers, or referred to as two general-purpose registers, and the two registers are separated from each other mainly by that the first register needs to be reset by a system, and the second register needs to be reset by a power-on reset, which is not equivalent to the prior art, and the present inventors will easily understand this. For example, in the ARM core, the second register mainly includes a Debug register, a EPPB register, and a DSCHR register (this register is described in detail later), and other registers used in the core are the first registers of the present invention. Further, in order to perform lock-step checking, the vehicle-mounted microprocessor circuit further includes a first delay unit, an inverter, a second delay unit, and a comparison module, where the first core, the inverter, and the second delay unit are sequentially connected in series, a data input is directly sent to the first core for processing and then output through the inverter and the second delay unit, the data input is delayed by the first delay unit and then sent to the second core for processing and then output, and both the output of the second delay unit and the output of the second core are sent to the comparison module for comparison.
The reset module of the vehicle-mounted microprocessor circuit can generate a system reset signal and a power-on reset signal as in the prior art, wherein the system reset signal is directly sent to the first registers of the two cores through the first output end. In addition, a reset signal switching circuit is also arranged in the reset module, and a power-on reset signal is selectively sent out through a second output end of the reset module when the microprocessor is in a test mode, namely the second register receives power-on reset and does not receive system reset, so that the test is not influenced; when the vehicle-mounted microprocessor circuit is in the normal working mode, the system reset signal is sent out through the second output end of the reset module, namely the second register receives the system reset and does not receive the power-on reset, so that when the lock step inspection is carried out, even if the system reset occurs in the synchronous period, the second registers of the two cores are reset, the data of the two cores are kept consistent, the comparison conclusion of the lock step inspection is that the two cores are consistent, a fault report cannot be sent out by mistake, and the working reliability and safety of the microprocessor (core) are improved. Of course, it should be further noted that, although the Debug register is not normally used in the normal operation mode, the EPPB register is normally used in the normal operation mode. Therefore, in the normal working mode, if the first core just writes new data into the EPPB registers and then just happens to reset the system, the invention can reset the EPPB registers of the two cores, so that error fault reports are not caused, and error fault reports are generated in the prior art. As for how the reset signal switching circuit selectively outputs the system reset signal and the power-on reset signal, there are various embodiments thereof, which will be described in detail below.
Referring to fig. 2, in a first embodiment of the reset signal switching circuit, the reset signal switching circuit includes a first selector and a first selection register, where the first selector has a first input end, a second input end, an output end and a selection end, the first input end and the second input end of the first selector respectively receive the system reset signal and the power-on reset signal, the output end of the first selector is used as the second output end of the reset module, and the first selection register is connected with the selection end of the first selector and can be written into different values by the first core or the second core to send to the first selector. This approach may be referred to as software approach selection. The first core or the second core writes a value into the first selection register through software (generally, which core is used as a main core to write with which core), for example, when the micro processor is in a test mode, 0 is written into the first selection register, and the first selector selects a power-on reset signal to output; when the microprocessor is in the normal operation mode, 1 is written into the first selection register, and the first selector selects the system reset signal output. The microprocessor is in a test mode or a normal working mode, and a user knows before using the microprocessor, so that the user writes corresponding numerical values into the first selection register through software before using the microprocessor. And then, when the microprocessor works, the microprocessor realizes the selective output of a system reset signal or a power-on reset signal according to the numerical value in the first selection register.
Referring to fig. 3, in a second embodiment of the reset signal switching circuit, the reset signal switching circuit includes a first selector and a system state detection module, where the first selector has a first input end, a second input end, an output end and a selection end, the first input end and the second input end of the first selector respectively receive the system reset signal and the power-on reset signal, the output end of the first selector is used as the second output end of the reset module, the input end of the system state detection module receives a state signal representing a state of the microprocessor, and the output end of the system state detection module is connected with the selection end of the first selector and generates different values according to the state signal and sends the different values to the first selector. This approach may be referred to as hardware approach selection. The hardware module of the system state detection module generates different values according to different information contained in the state signal by acquiring the state signal of the microprocessor and sends the different values to the first selector (how to perform the following specifically), so that the first selector selects the system reset signal or the power-on reset signal to output.
Referring to fig. 4, in a third embodiment of the reset signal switching circuit, the reset signal switching circuit includes a first selector, a second selector, a first selection register, a second selection register, and a system status detection module, where the first selector and the second selector each have a first input terminal, a second input terminal, an output terminal, and a selection terminal, the first input terminal and the second input terminal of the first selector respectively receive the system reset signal and the power-on reset signal, the output terminal of the first selector is used as the second output terminal of the reset module, the first selection register is connected to the first input terminal of the second selector, and can be written with different values by the first core or the second core and sent to the second selector, the input terminal of the system status detection module receives a status signal representing a state of the microprocessor, the output terminal of the system status detection module is connected to the second input terminal of the second selector, and generates different values according to the status signal and sends the different values to the second core or the second core and the second selector, and the first selector is connected to the second selector and the second selector. Based on the foregoing description of the embodiments of fig. 2 and 3, it will be readily appreciated that the embodiment of fig. 4 may be referred to as a software and hardware compatible option. If a 0 is written in the second selection register, the second selector selects the value in the first selection register and sends the value to the first selector for selection, and the method is the same as the embodiment of the foregoing figure 2; if 1 is written in the second selection register, the value generated by the second selector selection system state detection module is sent to the first selector for selection, and the same is the same as the embodiment of fig. 3.
Next, a system status detection module in the embodiments shown in fig. 3 and fig. 4 will be described. Referring to fig. 5, in a first embodiment of the system state detection module, the state signals include a field stage signal indicating a life cycle of a chip in a field use stage and a development stage signal indicating a life cycle of a chip in a development stage, or the state signals include a field stage signal indicating a life cycle of a chip in a field use stage and a failure stage signal indicating a life cycle of a chip in a failure analysis stage; the system state detection module comprises an NOT gate and an OR gate, wherein the development stage signal or the failure stage signal is sent to the NOT gate, the NOT gate output and the field stage signal are both sent to the OR gate, and the output end of the OR gate is used as the output end of the system state detection module. The chip is referred to herein as a microprocessor, which is also referred to as a microprocessor chip, for short. This is controlled according to the different stages of the life cycle (lifecycle) in which the microprocessor chip is located. When the chip is in the field use phase lifecycle (chip_is_in_field_ lifecycle), i.e., in use at the client, no test (Debug) is typically performed. Therefore, the microprocessor can select the power-on reset signal output (to the second register) in the test mode and select the system reset signal output (to the second register) in the normal operation mode by combining the field stage signal and any other stage signal (such as the development stage signal or the failure stage signal) and performing the NOT AND OR operation. For example, when the microprocessor is used at the client, the field stage signal is 1, the field stage signal is sent to the or gate, the other stage signals (development stage signal or failure stage signal) are 0,0 are sent to the or gate through the not gate, the operation result of the or gate is 1, and the system reset signal is selected to be output (to the second register). When the microprocessor is not used at the client, the on-site stage signal is 0, the on-site stage signal is sent to the OR gate, other stage signals (development stage signals or failure stage signals) are 1,1 are sent to the OR gate through the NOT gate, the operation result of the OR gate is 0 at the moment, and the power-on reset signal is selected to be output (for the second register), so that the normal operation of the test is not influenced. Note that this method may be simplified by selecting only the field phase signal, and the other phase signals and the nor gate or gate are not required, and the same object may be achieved.
Referring to fig. 6, in a second embodiment of the system state detection module, the state signal includes a test request signal indicating a test request state and a test request response signal indicating a test request response state, the system state detection module includes a nand gate, the test request signal and the test request response signal are both sent to the nand gate, and an output end of the nand gate is used as an output end of the system state detection module. The test request signal and the test request response signal are test mode related signals, and the method is controlled by directly identifying a test mode. When the test request signal and the test request response signal are both 1, the test is actually performed at the moment, that is to say, the test is performed in a test mode, the NAND gate outputs 0, and a power-on reset signal is selected to be output (to the second register), so that the normal operation of the test is ensured; and at other times, the NAND gate outputs 1, and a system reset signal is selected to output (to the second register), so that the lock step check is ensured not to falsely send out a fault report.
Referring to fig. 7, in a third embodiment of the system state detection module, the state signals include a field stage signal representing a life cycle of a chip in a field use stage, a test request signal representing a test request state, and a test request response signal representing a test request response state, the system state detection module includes a nand gate and an and gate, both the test request signal and the test request response signal are sent to the nand gate, both the output of the nand gate and the field stage signal are sent to the and gate, and an output terminal of the and gate is used as an output terminal of the system state detection module. Based on the foregoing description of the embodiment of fig. 5 and 6, it can be readily appreciated that the embodiment of fig. 7 combines lifecycle and modes of operation. In this embodiment, it may be realized that the system reset signal is always selected to be output (to the second register) for as long as no test is performed during the life cycle of the field use phase.
In addition, the technical staff further researches that the reset module in the vehicle-mounted microprocessor circuit can be applied to a single-core system to improve the reliability and the safety of the system, namely, the vehicle-mounted microprocessor circuit can be simply understood to have only the first core or the second core. Taking an ARM core as an example, DSCHR registers therein are also reset by power-on. If DSCHR registers change their values due to soft errors (environmental reasons such as electromagnetic radiation), it may cause the core to enter an error state and no longer execute instructions, at which time the error cannot be cleared by a system reset. The reset module of the invention can send the system reset signal to DSCHR registers (i.e. adopts system reset at this time) under the normal working mode through the reset signal switching module, so that the system reset signal can clear errors.
Compared with the prior art, the technical scheme of the invention has the following beneficial effects:
The reset module is internally provided with the reset signal switching circuit, and when the microprocessor is in a test mode, a power-on reset signal is sent out through the second output end of the reset module, namely the second register receives power-on reset and does not receive system reset, so that the test is not influenced; when the vehicle-mounted microprocessor circuit is in the normal working mode, the system reset signal is sent out through the second output end of the reset module, namely the second register receives the system reset and does not receive the power-on reset, so that when the lock step inspection is performed, even if the system reset occurs in the synchronous period, the second registers of the two cores are reset, the data of the two cores are kept consistent, the comparison conclusion of the lock step inspection is that the two cores are consistent, a fault report cannot be mistakenly sent out, the reliability and the safety of the work of the microprocessor (core) are perfected, and the reliability and the safety are good.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims. Furthermore, the foregoing description of the principles and embodiments of the invention has been provided for the purpose of illustrating the principles and embodiments of the invention and for the purpose of providing a further understanding of the principles and embodiments of the invention, and is not to be construed as limiting the invention.
Claims (10)
1. The vehicle-mounted microprocessor circuit is characterized by comprising a first core, a second core and a reset module, wherein the first core and the second core have the same structure, jointly form a lock step core, and comprise a first register and a second register, and are respectively provided with a first input end and a second input end, the first input end is connected with the first register, and the second input end is connected with the second register; the reset module is provided with a first output end and a second output end, the first output end of the reset module is connected with the first input end of the first core and the first input end of the second core, and the second output end of the reset module is connected with the second input end of the first core and the second input end of the second core; the system reset signal and the power-on reset signal are generated in the reset module, the first output end directly outputs the system reset signal, the reset module is internally provided with a reset signal switching circuit, the reset signal switching circuit is connected with the second output end and receives the system reset signal and the power-on reset signal, the power-on reset signal is selectively output from the second output end when the vehicle-mounted microprocessor circuit is in a test mode, and the system reset signal is selectively output from the second output end when the vehicle-mounted microprocessor circuit is in a normal working mode.
2. The vehicle-mounted microprocessor circuit according to claim 1, wherein the reset signal switching circuit comprises a first selector and a first selection register, the first selector has a first input end, a second input end, an output end and a selection end, the first input end and the second input end of the first selector respectively receive the system reset signal and the power-on reset signal, the output end of the first selector is used as the second output end of the reset module, and the first selection register is connected with the selection end of the first selector and can be written into different values by the first core or the second core to be sent to the first selector.
3. The vehicle-mounted microprocessor circuit according to claim 1, wherein the reset signal switching circuit comprises a first selector and a system state detection module, the first selector is provided with a first input end, a second input end, an output end and a selection end, the first input end and the second input end of the first selector respectively receive the system reset signal and the power-on reset signal, the output end of the first selector is used as the second output end of the reset module, the input end of the system state detection module receives a state signal representing the state of the microprocessor, the output end of the system state detection module is connected with the selection end of the first selector, and different values are generated according to the state signal and sent to the first selector.
4. The vehicle-mounted microprocessor circuit according to claim 1, wherein the reset signal switching circuit comprises a first selector, a second selector, a first selection register, a second selection register, and a system state detection module, wherein the first selector and the second selector each have a first input terminal, a second input terminal, an output terminal, and a selection terminal, the first input terminal and the second input terminal of the first selector respectively receive the system reset signal and the power-on reset signal, the output terminal of the first selector is used as the second output terminal of the reset module, the first selection register is connected with the first input terminal of the second selector, the first selection register is capable of being written with different values by the first core or the second core and is connected with the second selector, the input terminal of the system state detection module receives a state signal representing the state of the microprocessor, the output terminal of the system state detection module is connected with the second input terminal of the second selector, the output terminal of the system state detection module generates different values according to the state signal and is capable of being written with different values by the first core or the second core and is connected with the second selector, and the first selector and the second selector is capable of being written with the second core or the second core and is connected with the second selector.
5. The vehicle-mounted microprocessor circuit of claim 3 or 4, wherein the status signal comprises a field phase signal that characterizes a life cycle of a chip in a field use phase.
6. The vehicle-mounted microprocessor circuit according to claim 3 or 4, wherein the status signals comprise a field phase signal characterizing a chip in-field use phase lifecycle and a development phase signal characterizing a chip in development phase lifecycle, or the status signals comprise a field phase signal characterizing a chip in-field use phase lifecycle and a failure phase signal characterizing a chip in failure analysis phase lifecycle; the system state detection module comprises an NOT gate and an OR gate, wherein the development stage signal or the failure stage signal is sent to the NOT gate, the NOT gate output and the field stage signal are both sent to the OR gate, and the output end of the OR gate is used as the output end of the system state detection module.
7. The vehicle-mounted microprocessor circuit according to claim 3 or 4, wherein the status signals include a test request signal indicating a test request status and a test request response signal indicating a test request response status, the system status detection module includes a nand gate to which the test request signal and the test request response signal are both sent, and an output of the nand gate is used as an output of the system status detection module.
8. The vehicle-mounted microprocessor circuit according to claim 3 or 4, wherein the status signals include a field stage signal indicating a life cycle of a chip in a field use stage, a test request signal indicating a test request state, and a test request response signal indicating a test request response state, the system status detection module includes a nand gate and an and gate, the test request signal and the test request response signal are both sent to the nand gate, the output of the nand gate and the field stage signal are both sent to the and gate, and an output of the and gate is used as an output of the system status detection module.
9. The vehicle microprocessor circuit according to claim 1, wherein the vehicle microprocessor circuit has only the first core or the second core.
10. The vehicle microprocessor circuit according to claim 1, wherein the second register comprises a Debug register, EPPB registers, DSCHR registers.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102970013A (en) * | 2012-11-28 | 2013-03-13 | 中国人民解放军国防科学技术大学 | Resetting method and resetting control device of register inside chip based on scanning chain |
| CN113841123A (en) * | 2019-04-01 | 2021-12-24 | 德州仪器公司 | Scan chain self-test of lockstep core at reset |
| CN118363667A (en) * | 2024-06-20 | 2024-07-19 | 苏州旗芯微半导体有限公司 | Lock step core circuit supporting unlocking |
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102970013A (en) * | 2012-11-28 | 2013-03-13 | 中国人民解放军国防科学技术大学 | Resetting method and resetting control device of register inside chip based on scanning chain |
| CN113841123A (en) * | 2019-04-01 | 2021-12-24 | 德州仪器公司 | Scan chain self-test of lockstep core at reset |
| CN118363667A (en) * | 2024-06-20 | 2024-07-19 | 苏州旗芯微半导体有限公司 | Lock step core circuit supporting unlocking |
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