CN100541385C - Device and method for generating synchronous frequency division clock in digital TV modulator chip - Google Patents

Abstract

The invention provides a synchronous frequency-division clock generation device and method in a digital TV modulator chip, which is used in the national standard GB20600 terrestrial digital TV multimedia broadcasting baseband modulator chip, and can perform power-of-two frequency division on the main frequency clock signal. The device includes a main frequency clock signal input end, a test enable signal input end, three basic frequency division units connected in series and three selectors, especially two latches. The device and its method use registers and inverters to divide the main frequency clock signal by 2, 4 and 8 respectively, and at the same time use the main frequency clock signal to latch the frequency division signal. The final divided clock signal. The main advantage is that it can average the transmission delay of each frequency-divided clock signal with respect to the main frequency clock signal to reduce the skew of the synchronous clock signal, thereby reducing the clock skew of the entire integrated circuit chip and improving the frequency and performance of the chip.

Description

Device and method for generating synchronous frequency division clock in digital TV modulator chip

technical field

The invention belongs to the field of integrated circuit design, and relates to the field of digital integrated circuits. Specifically, it relates to a device and a method for generating a synchronous frequency-division clock in the chip design of a baseband modulator for terrestrial digital TV multimedia broadcasting according to the national standard GB20600.

Background technique

As another leap forward of the TV industry, digital TV integrates the world's most advanced image coding processing technology, digital processing technology and digital communication technology, and is one of the focuses of technological competition in the world today. The national standard for terrestrial digital TV GB20600-2006 "Digital TV Terrestrial Broadcasting Transmission System Frame Structure, Channel Coding and Modulation" has been officially promulgated, but there is no baseband modulator chip that fully complies with the national standard GB20600 for terrestrial digital TV multimedia broadcasting.

Since the 1980s, the integrated circuit industry has been developing at the speed of Moore's Law. At present, the digital application specific integrated circuit (Application Specific Integrated Circuit, referred to as ASIC) process is developing in two different directions, one is system on chip (System on Chip, referred to as SOC) technology, multi-IP core complex system design, and the other is Smaller line width, larger scale, lower low power consumption design. In the development of these two aspects, the structural design and synthesis of chip clock tree are one of the key technologies. Generally speaking, in SOC design, the clock relationship between IP cores is more complicated. There are few cases of a single clock frequency. In most cases, it is composed of multiple different clocks. The complexity of clock signals continues to increase. How to design complex The clock tree structure, which can not only meet the needs of system design, but also can be quickly synthesized in Electronic Design Automation (EDA) tools is one of the problems that must be solved in SOC design. At the same time, in the design of low power consumption, since the network wiring resources of the clock signal of the chip account for more than 50% of the entire chip signal network, a reasonable clock tree structure can reduce a large number of wiring resources and reduce the area and power consumption of the chip. All have great significance. The gating clock is the most common method to achieve low power consumption, which undoubtedly further increases the complexity of the clock tree. At the same time, the testability design requires adding a test clock that has nothing to do with the system clock frequency in the current complex situation, so that the design of the clock tree involves at least two clocks with no frequency. Therefore, the quality of the clock tree directly affects the frequency performance and power consumption of the chip. Although the current EDA tools provide automated clock tree analysis and design programs, an overly complex clock tree structure not only increases the area and power consumption of the chip, but also increases the calculation load of the EDA tool and prolongs the design cycle. Therefore, designers need to take into account the distribution and connection methods of the clock tree in the chip at the beginning of system design.

Usually, a system will integrate tens of thousands or even millions of registers. These registers are controlled by a clock source. These registers are called register files. Register files controlled by the same clock are considered to belong to the same clock network; and The topology of a clock network in a chip is called a clock tree. The design of the clock tree needs to consider the following factors:

First, the maximum power, since the clock signal determines the data transmission rate, it determines the maximum power that the design can achieve;

Second, power consumption. Since the scale of the clock network is relatively large and the flipping speed is relatively fast, it has a great impact on power consumption;

Third, noise, because every time the clock signal flips, a large current will pass through the power supply and ground, so it will generate large noise interference to other signals.

In the design of the clock tree, the usual practice is to specify the maximum delay target value from the clock source to the leaf node of the clock tree in the EDA tool, and EDA will automatically plan the clock tree according to the target value. The leaf nodes of the clock tree refer to the output ports of the chip and the clock input terminals of the latches, registers or IP blocks. The skew of the clock signal (clock skew) is the most important factor in determining the timing of the circuit. In the clock network, due to the different paths of the clock to different registers, the trigger clock of each register does not jump at the same time, and there is always a time difference; therefore, the skew of the clock signal refers to the relative maximum value of the delay between the registers . If the maximum delay of the clock in the chip is TL, and the minimum delay is TS, then the clock skew is SKEW=TL-TS.

The main goal of clock routing design is to minimize the skew and phase delay of the clock signal, that is, zero clock signal skew. The main clock topology adopted is a balanced clock (balance-tree) structure, as shown in Figure 1, using a top-down design method, the clock path is divided into multi-pole H-shaped distribution, and by inserting buffers and increasing the line width A method to realize the data structure of the balanced clock tree and realize the zero-skew circuit.

As shown in Figure 1, the EDA tool analyzes the clock structure of the chip, inserts buffers of different sizes, and plans the clock network into a balanced clock tree structure as shown in Figure 1, so as to ensure the clock signal reaching each register as much as possible same phase. The H-shaped tree structure graph of the clock tree is constructed in such a way that the main frequency clock signal input terminal is the starting point S of the H-shaped tree structure. Each node N is the output of the frequency division register or the output of the drive buffer, and the end point F of the H-shaped tree structure is the clock input end of the data register.

As shown in Figure 2, it is a structural diagram of an existing synchronous frequency-division clock generation device. The main frequency clock signal M is obtained by the basic frequency division unit formed by the register 1 and the inverter 2, and the frequency-division signal by two is obtained. A frequency-divided-by-four signal is obtained through the basic frequency-division unit formed by the register 3 and the inverter 4, and a frequency-divided signal by eight is obtained by the basic frequency-divided unit formed by the register 5 and the inverter 6. The second, fourth and eighth frequency division signals are respectively connected to one end of the three selectors 7-9, and the other ends of the three selectors 7-9 are connected to the main frequency clock signal M, and the output of the selector is controlled by the test enable signal T.

As shown in Figure 3, it is a clock tree structure diagram constructed by using the existing synchronous frequency-divided clock generation device and its method, wherein the frequency-divided clock signal C2 is at the second-level clock node, relative to the main frequency clock signal M The phase delay is the hold time of one register. The frequency-divided clock signal C4 is at the third-level clock node, and the phase delay relative to the main frequency clock signal M is the holding time of the two registers. Wherein, the frequency-divided-by-eight clock signal C8 is at the fourth-level clock node, and the phase delay relative to the main frequency clock signal M is the delay holding time of the three registers. The current EDA tool's processing mode for the clock tree network is mainly this H-shaped balanced clock tree structure. In order to ensure the balance of the clock tree, the EDA tool has to insert a large number of buffers on the non-clock generation path to ensure the third-level nodes. The delay is consistent. This is usually difficult, and by inserting a large number of buffers, the clock signal will prolong its transition time, thereby affecting the increase in the delay of the clock signal in the chip; increase in area.

The national standard GB20600 terrestrial digital TV multimedia broadcasting baseband modulator chip has more than 1.8 million standard unit gate circuits, 45 large memory macro modules, 201 input and output pads, and includes an integrated analog PLL, with an area of 6324.16×6320.24 (um ² ), that is, 40 square millimeters. The chip contains four synchronous clock signals of 60.48MHz, 30.24MHz, 15.12MHz, and 7.48MHz. Based on the consideration of area and power consumption optimization, there is frequent data exchange between each clock domain; at the same time, because the chip has a large number of macro Unit, and the scale is also large, the clock path is long and complex, so the design of the clock signal in the chip puts forward higher requirements. The device and method for generating a synchronous frequency-divided clock using the existing synchronous clock frequency division technology will place the frequency-divided clock at different levels of the clock tree. Therefore, the clock phase delay will increase step by step, and the skew of the clock signal will increase. It causes the phase inconsistency of the synchronous clock signal inside the chip, which leads to the decrease of the working frequency of the chip, and the excessive skew of the clock signal even affects the normal operation of the chip.

Contents of the invention

The present invention aims at the problem that the existing synchronous frequency-division clock generation device and its method in digital integrated circuit design will increase the delay of the internal synchronous clock in the chip, and provides an improved baseband for national standard GB20600 terrestrial digital TV multimedia broadcasting A device and method for generating a synchronous frequency division clock in modulator chip design, the device and method can reduce the skew of the internal clock signal of the chip and increase the operating frequency of the chip.

The device provided by the present invention includes a main frequency clock signal input end, a test enable signal input end, three basic frequency division units in series and three selectors, and the device also includes two latches; wherein,

Each frequency division unit is composed of a register and an inverter. Inside each frequency division unit, the output of the register is connected to the input of the inverter, the output of the inverter is connected to the input of the register, and the output of the inverter It is the frequency division clock output of the frequency division unit.

The main frequency clock signal input end is connected with the clock input end of the register in the first frequency division unit, and the output end of the inverter in the first frequency division unit and the main frequency clock signal input end are respectively connected with two selectors of the first selector. The input terminal is connected; the output terminal of the inverter in the first frequency division unit is connected with the clock input terminal of the register in the second frequency division unit at the same time, and the output terminal of the inverter in the second frequency division unit is connected with the first The data input end of the latch is connected, the clock input end of the first latch is connected with the main frequency clock signal, the output end of the first latch and the main frequency clock signal input end are respectively connected with the second selector The two inputs are connected;

The output terminal of the inverter in the second frequency division unit is connected with the clock input terminal of the register in the third frequency division unit at the same time, and the output terminal of the inverter in the third frequency division unit is connected with the second latch , the clock input end of the second latch is connected to the main frequency clock signal input end, and the output end of the second latch and the main frequency clock signal input end are respectively connected to the two input ends of the third selector;

The selection control terminals of the three selectors are all connected to the input terminal of the test enable signal, and the output terminals of the three selectors are used as the output terminals of the synchronous clock generating device.

The present invention also provides a method for generating a synchronous frequency-divided clock by utilizing the above-mentioned device, the method comprising the following steps:

a) divide the frequency of the main frequency clock of the system by using a frequency divider and an inverter;

b) Latching the frequency-divided clock obtained after the frequency division with a register;

c) Selecting the output clock signal after frequency division and latching with the main frequency clock signal input selector to obtain the final frequency division clock.

The method introduced in the present invention is to reform the unbalanced clock tree structure through the circuit, input the frequency division clock obtained by the frequency division unit into the register, and use the main frequency clock to perform secondary latching, and the output of the register is used as the Synchronous clock usage. Due to the use of the latch of the main frequency clock signal, the delays of each divided clock signal for the main frequency clock signal are the same, which is the hold time of the register; therefore, in the obtained reconstructed clock tree structure, all divided clock signals The frequency clocks are all in the second-level nodes, so as to construct a relatively balanced clock tree structure, so that the clock phases of different frequency clock signals in the chip are consistent, reducing the skew of the chip clock signal, thereby increasing the clock frequency.

Description of drawings

Fig. 1 is the H-shaped structural diagram of existing clock tree;

Fig. 2 is the structure diagram of the generation device of existing synchronous frequency division clock;

Fig. 3 is the clock tree structural diagram that utilizes existing synchronous frequency division clock generation device and method thereof to construct;

Fig. 4 is the structural diagram of the generating device for the synchronous frequency division clock in the national standard GB20600 terrestrial digital TV multimedia broadcasting baseband modulator chip provided by the present invention;

Fig. 5 is used for the generation method flowchart of the synchronous frequency division clock in the national standard GB20600 terrestrial digital TV multimedia broadcasting baseband modulator chip provided by the present invention;

Fig. 6 is a clock tree structure diagram constructed by using the synchronous frequency-divided clock generation device and method used in the national standard GB20600 terrestrial digital TV multimedia broadcasting baseband modulator chip provided by the present invention.

Detailed ways

The present invention will be further described below in combination with specific embodiments.

As shown in Figure 4, it is a structural diagram of the generation device for the synchronous frequency division clock in the national standard GB20600 terrestrial digital TV multimedia broadcasting baseband modulator chip provided by the present invention, the device includes a main frequency clock signal input terminal, a test enable Signal input terminal, three basic frequency division units in series and three selectors, in particular, the device also includes two latches; wherein,

The register 10 and the inverter 11 form the first basic frequency division unit, the register 12 and the inverter 13 form the second frequency division unit, and the register 14 and the inverter 15 form the third frequency division unit. The connection mode of the three frequency division units is the same, taking the first frequency division unit as an example: the output of the register 10 is connected with the input of the inverter 11, the output of the inverter is connected with the input of the register 10, and the output of the inverter is the output of the frequency division unit, which is the frequency-divided signal of the clock signal input to the clock input terminal of the middle register 10 of the frequency division unit.

The main frequency clock signal M input end is connected with the clock input end of the register 10 in the first frequency division unit, and the output end of the inverter 11 in the first frequency division unit and the main frequency clock signal M input end are respectively connected with the first selection The two inputs of the device 18 are connected. The output terminal of the inverter 11 in the first frequency division unit is connected with the clock input terminal of the register 12 in the second frequency division unit simultaneously, and the second register 12 and the second inverter 13 constitute the second basic division The frequency unit is connected in the same way as the first register 10 and the first inverter 11 above. The output end of the second inverter 13 is connected with the data input end of the first latch 16, and the clock input end of the first latch 16 is connected with the main frequency clock signal M input end, and the first latch The output terminal of the device 16 and the input terminal of the main frequency clock signal M are respectively connected with the two input terminals of the second selector 19. The output terminal of the inverter 13 in the second frequency division unit is connected with the clock input terminal of the register 14 in the third frequency division unit simultaneously, and the third register 14 and the third inverter 15 form the third basic frequency division unit, the connection mode is the same as that of the first register 10 and the first inverter 11; the output terminal of the inverter 15 in the third frequency division unit is connected with the second latch 17, and the second latch 17 The clock input end of the second latch 17 is connected to the input end of the main frequency clock signal M, and the output end of the second latch 17 and the input end of the main frequency clock signal M are connected to the two input ends of the third selector 20 respectively. The selection control terminals of the three selectors 18-20 are all connected to the test enable signal T, and the output terminals of the three selectors 18-20 are used as the output terminals of the synchronous clock generating device.

The device performs three-level frequency division on the input main frequency clock signal, and the three-level frequency division is all power-of-two frequency division, that is, two, four, and eight frequency divisions are performed. The specific workflow is as follows:

First, a frequency-divided signal is generated from the main frequency clock signal M. The main frequency clock signal M drives the first register 10, and the obtained data signal passes through the first inverter 11, and is connected back to the data terminal of the register to obtain a frequency-divided signal by two; the frequency-divided signal is triggered by the main frequency clock signal M Therefore, the delay of the frequency-divided signal by two relative to the main frequency clock signal M is the holding time of a register.

Then, a frequency-divided-by-four signal is generated from the divided-by-two signal. The second frequency-division signal drives the second register 12, and the output signal obtained is passed through the second inverter 13 and then connected back to the data end of the second register 12 to obtain the original four-frequency division signal; the four-frequency division signal is divided by two Frequency signal trigger generation, then the delay of the four-frequency signal relative to the two-frequency signal is the hold time of the register, and the delay of the two-frequency signal relative to the main frequency clock signal M is also the register hold time, so the original four-point The delay of the frequency signal relative to the main frequency clock signal M is the holding time of the two registers.

Next, a frequency-divided signal by eight is generated from the clock signal divided by four. The frequency-divided-by-four signal drives the third register 14, and the output signal obtained passes through the third inverter 15 and then is connected back to the data terminal of the third register 14 to obtain the original frequency-divided eighth signal. The eighth frequency division signal is triggered by the four frequency division signal, then the delay of the eighth frequency division signal relative to the four frequency division signal is the holding time of one register, and the delay of the four frequency division signal relative to the main frequency clock signal M is two The hold time of three registers, so the delay of the original eight-frequency signal relative to the main frequency clock signal M is the hold time of three registers.

Subsequently, the main frequency clock signal M is used to latch the original frequency-divided-by-four signal and the divided-by-eight signal. The original frequency-divided-by-four signal is input from the data terminal of the first latch 16 driven by the main frequency clock signal M, and the frequency-divided signal by four is obtained from the output terminal of the first latch 16 . The original frequency-divided signal by eight is input from the data terminal of the second latch 17 driven by the main frequency clock signal M, and the frequency-divided signal by eight is obtained at the output terminal of the second latch 17 . The frequency-divided-by-four signal and the divided-by-eight signal obtained in this step are produced by the latch triggered by the main frequency clock signal M, therefore, the phase difference between the divided-by-four signal and the divided-by-eight signal relative to the main frequency clock signal M Time is kept for only one register.

Finally, according to the input test enable signal T, it is selected to output the main frequency clock signal M or the frequency-divided clock signal. The obtained two-frequency signal and the main frequency clock signal M are selected by the first selector 18 to obtain the output two-frequency clock signal C2; the obtained four-frequency signal and the main frequency clock signal M are passed through the second selector 19 Select to obtain the output divided-by-four clock signal C4; the obtained divided-by-eight signal and the main frequency clock signal M are selected by the third selector 20 to obtain the output divided-by-eight clock signal C8. The three selectors 18-20 are controlled by the test enable signal T, select the frequency division clock signal output in the working state, and select the main frequency clock signal output in the test state.

As shown in Figure 4, it is a structural diagram of the generation device used for the synchronous frequency division clock in the national standard GB20600 terrestrial digital TV multimedia broadcasting baseband modulator chip provided by the present invention, the device comprises three basic frequency division units altogether, two The number of latches, that is, the number of latches is one less than that of the basic frequency division unit. The frequency-divided signal by four and the frequency-divided signal by eight are respectively generated by the second and three basic frequency division units, and the delay relative to the main frequency clock signal M is the holding time of two and three registers. After passing through a latch respectively, the delay relative to the main frequency clock signal M is the holding time of a register. The frequency-divided-by-two signal is generated by the first basic frequency-dividing unit, and the delay relative to the main frequency clock signal M is the holding time of one register. Therefore, in order to ensure that the phases of the synchronous frequency division clock signal are consistent, the device needs three series-connected basic frequency division units and two latches, that is, the number of latches is one less than that of the basic frequency division unit.

As shown in Figure 4, it is a structural diagram of the generation device used for the synchronous frequency division clock in the national standard GB20600 terrestrial digital TV multimedia broadcasting baseband modulator chip provided by the present invention, which includes three devices for testability design The selector is respectively connected with the 2-, 4-, 8-frequency division signal and the main frequency clock signal M, and the output of the selector is controlled by connecting the test enable signal T with the selection signal. When the test enable signal is "0", the device is in the working state, and the output signals are the clock signal C2, the clock signal C4, and the clock signal C8; when the test enable signal is "1 ", the device is in the test state, and the output signal is the main frequency clock signal M. This ensures that in the test state, the clocks connected to all registers are the same clock signal.

As shown in Figure 5, for the generation method flowchart of the synchronous frequency division clock in the national standard GB20600 terrestrial digital TV multimedia broadcasting baseband modulator chip provided by the present invention, the concrete flow process of this method can be:

Step1: Generate a two-frequency synchronous clock signal from the main frequency clock signal. The main frequency clock signal drives the register 10, and the obtained data signal passes through the inverter 11, and is connected back to the data terminal of the register to obtain a clock signal divided by two. The delay between the frequency-divided signal by two and the main frequency clock signal is a register delay.

Step2: Generate a four-frequency synchronous clock signal from the two-frequency clock signal. The frequency-divided signal drives the register 12, and the output signal obtained passes through the inverter 13 and is connected back to the data terminal of the register 12 to obtain a frequency-divided signal by four. The delay between the four-frequency division signal and the main frequency clock signal is two register delays.

Step3: Generate an eight-frequency synchronous clock signal from the four-frequency clock signal. The frequency-divided-by-four signal drives the register 14, and the obtained output signal passes through the inverter 15 and then is connected back to the data terminal of the register 14 to obtain the divided-by-eight signal. The delay between the frequency-divided-by-eight signal and the main frequency clock signal is three register delays.

Step4: Use the main frequency clock signal to latch the frequency-divided by four and eight signals. The frequency-divided signal obtained in Step 2 passes through the latch 16 driven by the main frequency clock signal, and the frequency-divided signal is obtained at the output terminal of the latch 16 . The frequency-divided-by-eight signal obtained in Step3 passes through the latch 17 driven by the main frequency clock signal, and the frequency-divided signal by eight is obtained at the output terminal of the latch 17 . The phase difference between the frequency-divided by four and eight signals obtained in this step and the main frequency clock signal is one register delay.

Step5: Choose to output the main frequency clock signal or the frequency division clock signal according to the input test signal. The frequency-divided clock signal obtained in Step1 and the main frequency clock are selected by the selector 18 to obtain the output clock signal divided by two. The frequency-divided clock signal obtained in Step4 and the main frequency clock are selected by the selector 19 to obtain the output frequency-divided clock signal by 4. The divided-by-eight clock signal obtained in Step4 and the main frequency clock are selected by the selector 20 to obtain the output divided-by-eight clock signal. The three selectors 18-20 are controlled by the test enable signal, select the original frequency division signal output in the working state, and select the main frequency clock frequency division signal output in the test state.

As shown in Figure 6, it is a clock tree structure diagram constructed for the generation device and method thereof for the synchronous frequency division clock used in the national standard GB20600 terrestrial digital TV multimedia broadcasting baseband modulator chip provided by the present invention, which is the same as that in Figure 3 Compared with the clock tree structure formed by the existing method, using the main frequency clock signal M to latch the original four-frequency signal and the original eight-frequency signal, the two-frequency clock signal C2, the four-frequency clock signal C4, The eight-frequency clock signal C8 can be regarded as a frequency-division signal generated by the main frequency clock signal M through a register, and the delay relative to the main frequency clock signal M is the same, while the clock generated by the three series-connected basic register units is It is considered that the data path is not considered in the topology of the clock tree, so the two-frequency clock signal C2, the four-frequency clock signal C4, and the eight-frequency clock signal C8 are all in the second-level clock tree structure, which is logically guaranteed Balanced clock tree structure. It is not necessary to insert a large number of buffers in the clock tree synthesis (CTS) process to ensure that the skew of the clock signal is minimized. Therefore, a large number of winding resources are saved, which greatly contributes to reducing the chip area. At the same time, the time used by the EDA tool for calculating the CTS structure is saved, and the design cycle of the chip is shortened.

Claims (7)

1. The generation device of synchronous frequency division clock in the digital television modulator chip, this device comprises a main frequency clock signal input end, a test enable signal input end, three basic frequency division units in series and three selectors, its It is characterized in that the device also includes two latches; wherein, The main frequency clock signal (M) is input into three basic frequency division units connected in series to obtain the two frequency division signal, the original four frequency division signal and the original eighth frequency division signal. The specific connection method is: the main frequency clock signal (M) input terminal and The register input terminals of the first basic frequency division unit are connected to generate a frequency-division signal by two, and the frequency-division signal is input from the register input terminal of the second basic frequency division unit to generate the original frequency-division signal by four, and the original frequency-division signal by four is obtained from The register input terminal of the third basic frequency division unit is input to generate the original eighth frequency division signal; The original four-divided signal and the original eight-divided signal are respectively input from the data terminals of the two latches, and the main frequency clock signal is input at the clock terminals of the two latches, and the output terminals of the two latches are obtained Four-frequency signal and eight-frequency signal; The two-frequency signal obtained from the output terminal of the first basic frequency division unit and the four-frequency signal and eight-frequency signal obtained from the output terminals of the two latches are respectively input from one of the input terminals of the three selectors, and the three The other ends of the selectors all input the main frequency clock signal (M), the selection signal ends of the three selectors are connected with the test enable signal (T) input end, and the output ends of the three selectors are the output ends of the device. 2. the generation device of synchronous frequency-division clock in the digital television modulator chip according to claim 1, is characterized in that, this device also comprises the selection signal terminal of test enable signal (T) input end and each selector respectively connected, When the test enable signal (T) is 1, the selector outputs the main frequency clock signal (M); When the test enable signal (T) is 0, the selector outputs frequency-divided clock signals (C2, C4, C8). 3. the generation device of synchronous frequency division clock in the digital television modulator chip according to claim 1, is characterized in that, the number of selector is equal to the number of basic frequency division unit, and the number ratio of latch is basically The number of frequency division units is one less. 4, apply the generation method of synchronous frequency division clock in the digital television modulator chip of the described device of claim 1, it is characterized in that, the method comprises the following steps: a) Carry out three-level frequency division to the main frequency clock signal of the circuit; b) Latching the original four-frequency division clock signal obtained after frequency division and the original eighth frequency division clock signal; c) Selecting one of the latched frequency-divided clock signal and the main frequency clock signal as the final frequency-divided clock signal. 5. The method for generating a synchronous frequency-division clock in a digital TV modulator chip according to claim 4, wherein the three-level frequency division performed in step a) is a power-of-two frequency division. 6. The method for generating a synchronous frequency-division clock in a digital TV modulator chip according to claim 5, wherein said power-of-two frequency division includes frequency division by two, frequency division by four, and frequency division by eight. 7. the generation method of synchronous frequency-division clock in the digital television modulator chip according to claim 4, is characterized in that, step c) is to select final frequency-division clock signal according to whether said circuit is in working state or test state , When the circuit is in the working state, select the frequency-divided clock signal after latching; When the circuit is in the test state, the main frequency clock signal is selected.

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