CN109815619B

CN109815619B - Method for converting synchronous circuit into asynchronous circuit

Info

Publication number: CN109815619B
Application number: CN201910123501.1A
Authority: CN
Inventors: 陈虹; 吴辉
Original assignee: Tsinghua University
Current assignee: Tsinghua University
Priority date: 2019-02-18
Filing date: 2019-02-18
Publication date: 2021-02-09
Anticipated expiration: 2039-02-18
Also published as: CN109815619A

Abstract

The invention can realize the automatic conversion of the synchronous pipeline circuit into the bundled data asynchronous circuit based on the Click unit. Firstly, this method converts the synchronous Verilog code into the Verilog code of the Click unit-based asynchronous circuit based on the bundled data by comparing the difference between the synchronous pipeline and the asynchronous circuit based on the bundled data of the Click unit. The asynchronous circuit is then synthesized using the Synopsys Design Compiler (DC) tool. The invention can quickly realize the conversion of the synchronous pipeline circuit into the asynchronous circuit based on the bundled data of Click, which greatly shortens the design cycle of the asynchronous circuit and reduces the difficulty of the asynchronous circuit design.

Description

Method for converting synchronous circuit into asynchronous circuit

Technical Field

The invention belongs to the technical field of integrated circuit design, and particularly relates to a method for converting a synchronous circuit into an asynchronous circuit.

Background

With the continuous improvement of the manufacturing process of the integrated circuit, the asynchronous circuit has the following remarkable characteristics compared with a synchronous circuit.

1. Low power consumption: asynchronous circuits consume power only when and where it is needed

2. High speed: the delay of an asynchronous circuit depends on the local delay rather than the longest delay path of the overall circuit

3. No clock distribution problem: asynchronous circuits have no global clock, so do not require clock tree synthesis

However, asynchronous circuits are difficult to design. Since asynchronous circuits are not widely adopted by the industry, no mature commercial EDA tool supports the design of asynchronous circuits. In addition, since many integrated circuit digital engineers accept training of synchronous circuit design, there is a problem of conversion from synchronous circuit design thinking to asynchronous circuit design thinking in design, which increases the difficulty of asynchronous circuit design. Finally, the types of asynchronous circuits are more, and different types of asynchronous circuits also have differences in design methods, which also improves the threshold of asynchronous circuit design to a certain extent.

Disclosure of Invention

In order to overcome the above-mentioned drawbacks of the prior art and to reduce the difficulties in designing asynchronous circuits, it is an object of the present invention to provide a method for converting synchronous circuits into asynchronous circuits, which can be designed with sophisticated EDA tools, using a Click cell based bundled data asynchronous circuit architecture closest to the synchronous circuits.

In order to achieve the purpose, the invention adopts the technical scheme that:

a method of converting a synchronous circuit to an asynchronous circuit, comprising the steps of:

step 1, comparing the difference between a synchronous pipeline circuit and a binding data asynchronous circuit based on a Click unit;

step 2, converting Verilog codes of the synchronous pipeline circuit into Verilog codes of a binding data asynchronous circuit based on a Click unit through a Tcl script;

and 3, synthesizing the asynchronous circuit by using a Synopsys Design Compiler (DC) tool.

The synchronous pipeline circuit is different from a binding data asynchronous circuit based on a Click unit in that:

1) the synchronous pipeline circuit drives the D flip-flop by using a global clock clk, and the bundled data asynchronous circuit based on a Click unit drives the D flip-flop by using a pulse signal generated by the Click unit;

2) the tied data asynchronous circuit based on the Click cell requires an additional Click cell to generate a pulse that can drive the D flip-flop, while the synchronous pipeline circuit does not.

3. The method of converting a synchronous circuit into an asynchronous circuit as claimed in claim 1, wherein the Click cells are instantiated and the netlist is as follows:

the instantiated Click cell, using the set _ dot _ touch command, prevents it from being changed during the synthesis.

The step 2 specifically comprises:

step 2.1: finding the pipeline stage number of the synchronous pipeline circuit;

step 2.2: replacing the posededge clk in the synchronous pipeline circuit code with the posededge fire, and adding instantiation of a Click unit in the code;

step 2.3: the clock port in the synchronous pipeline circuit code is replaced with in _ req and the other ports of the Click unit are added to the code.

In the step 2.1, the synchronous pipeline circuit code is labeled in the following manner, and then the number of labels is found through the Tcl script so as to find the stage number of the pipeline:

in the step 2.2, the number of the Click units is added according to the number of stages of the pipeline, and the posegdge clk of each stage is sequentially replaced by the posegdge fire1 and the posegdge fire2, and so on, that is, the posegdge clk of the first stage is replaced by the posegdge fire1, the posegge clk of the second stage is replaced by the posegge fire2, and the posegge clk of the nth stage is replaced by the posegge fire N. Wherein the number of stages of the pipeline is equal to the number of Click units.

In said step 2.3, the in _ req, in _ ack, out _ req, out _ ack ports of the Click unit are added in the code port declaration section.

In the step 3, synthesizing the asynchronous circuit through a Synopsys Design Compiler (DC) tool is to convert the synchronous pipeline code into the asynchronous pipeline code, then set _ dot _ touch of the Click unit, and then create a clock for the fire signal, thereby realizing circuit synthesis.

Compared with the prior art, the invention can directly convert the synchronous pipeline circuit into a binding data asynchronous circuit based on Click, thereby greatly reducing the difficulty of asynchronous circuit design.

Drawings

FIG. 1 is a Click cell used in the present invention.

Fig. 2 is a waveform diagram of a Click cell used in the present invention.

FIG. 3 is a basic architecture diagram of a bundled data asynchronous circuit based on Click cells.

FIG. 4 is a circuit diagram of the synchronous pipeline to be inverted in the present invention.

FIG. 5 is a schematic diagram of a bundled data asynchronous circuit based on a Click cell converted by the synchronous pipeline circuit of FIG. 4.

Detailed Description

The embodiments of the present invention will be described in detail below with reference to the drawings and examples.

The circuit diagram of the Click cell is shown in fig. 1:

it can be seen that the Click cell contains a D flip-flop and there is a loop in the circuit, so it is not a combinational logic circuit. Such circuits cannot be synthesized by DC tools if their logical relationships are described only by Verilog. Therefore, there is a need to solve this problem by directly instantiating the Click cell. The netlist instantiating the Click cell is shown in table 1. The instantiated Click cell needs to use commands to prevent it from being changed during synthesis.

TABLE 1 Click netlist

The waveform diagram of the Click cell is shown in fig. 2. The Click cell uses a two-phase handshake protocol, i.e., each flip of the request signal represents a request, and the Click cell generates a pulse. This pulse can be considered a clock to capture and store data. Thus, the pulse signals generated by the Click control unit of the asynchronous circuit can be effectively treated as a clock, so that the clock can be created for the pulse signals in a synthesis script and then the DC tool can be used for synthesis.

The basic architecture of the bundled data asynchronous circuit based on the Click cell is shown in fig. 3, and according to the structure of the Click, a fire signal is generated for data capture or storage whenever the request signal (i _ r1) of the Click flips. And the request signal passes to the next stage to serve as the next stage's request signal (i _ r 2). "binding data" means that the data signal takes a boolean value, and the request (request) and acknowledge (acknowledge) lines are separate from each other and bound together with the data.

A schematic diagram of the conversion of the synchronous pipeline circuit of fig. 4 into a Click cell based bundled data asynchronous circuit is shown in fig. 5. As can be seen from fig. 4 and 5, the difference between the synchronous pipeline circuit and the bundled data asynchronous circuit based on the Click cell is that:

1. the synchronous circuit drives the D flip-flops using the global clock clk, while the asynchronous circuit drives the D flip-flops using the pulse signals generated by the Click cells.

2. Asynchronous circuits require additional Click cells to generate pulses that can drive the D flip-flops, while synchronous circuits do not.

Based on the above differences, the synchronous pipeline circuit described by Verilog can be converted into a bundled data asynchronous circuit based on a Click unit through the following steps.

Step 1: the number of stages of the pipeline is found. This can be noted by noting in the synchronization code in the manner shown in Table 2, and then the number of pipeline stages can be found by the Tcl script.

TABLE 2 pipeline stage number labeling

Step 2: the posededge clk in the synchronization code is replaced with posededge fire and the instantiation of the Click cell is added to the code. In step 1, the number of pipeline stages can be found, the number of Click units is added according to the number of pipeline stages, and the posedge clk of each stage is replaced by posedge fire1, posedge fire2 and so on.

And step 3: replace the clock port in the synchronization code with in _ req and add some other ports of the Click in the code.

The synchronous pipeline circuit can be converted into a Click-based bundled data asynchronous circuit in the above way.

Claims

1. A method of converting a synchronous circuit to an asynchronous circuit, comprising the steps of:

step 2, converting the Verilog code of the synchronous pipeline circuit into the Verilog code of the binding data asynchronous circuit based on the Click unit through the Tcl script, and the specific steps are as follows:

step 2.3: replacing a clock port in the synchronous pipeline circuit code with in _ req, and adding other ports of a Click unit in the code;

2. The method of converting a synchronous circuit to an asynchronous circuit according to claim 1, wherein said synchronous pipeline circuit is distinguished from a Click cell based bundled data asynchronous circuit by:

3. The method of claim 1, wherein in step 2.2, the number of Click units is added according to the number of stages of the pipeline, and the posedge clk of each stage is sequentially replaced by posedge fire1, posedge fire2, and so on, wherein the number of stages of the pipeline is equal to the number of Click units.

4. A method for converting a synchronous circuit into an asynchronous circuit according to claim 1, characterized in that in step 2.3, in _ req, in _ ack, out _ req, out _ ack ports of a Click unit are added in the code port declaration section.

5. The method of claim 1, wherein in step 3, the synthesis of the asynchronous circuit by the Synopsys Design Compiler (DC) tool is to convert the synchronous pipeline code into the asynchronous pipeline code, and then clock the Click unit set _ dot _ touch and then the fire signal, thereby realizing the circuit synthesis.