CN113407239B - Pipeline processor based on asynchronous monorail - Google Patents

Abstract

The application relates to a pipeline processor based on asynchronous monorail, comprising: the system comprises an asynchronous control module, an instruction fetching module, a decoding module, an executing module, a self-adaptive selection module, a memory access module, a write-back module, a storage module, a control and status register and a general register, wherein data communication is completed among the modules through asynchronous single-rail handshake, the asynchronous control module comprises a plurality of control units, the plurality of control units are a plurality of phase decoupling Click units, and the plurality of phase decoupling Click units are mutually cascaded through handshake and are respectively connected with corresponding pipelines. According to the method and the device, the problems of high power consumption, serious global clock offset and low clock frequency limiting speed of the pipeline processor in the related technology are solved, and the pipeline is operated at a higher speed without a clock under low power consumption.

Description

A Pipelined Processor Based on Asynchronous Single Rail

technical field

The application relates to the fields of electronic information, processors and asynchronous circuits, in particular to an asynchronous monorail-based pipeline processor.

Background technique

With the rapid development of the Internet of Things and artificial intelligence, SOC technology continues to mature. Most chips now integrate their own processors. It can be seen that processors play an important role in electronic technology, so the design of processors has received extensive attention. The processor structure is roughly divided into arithmetic logic unit, register unit and control unit. These units are composed of a large number of registers, and data processing instructions only operate on registers. Due to the existence of the global clock, although the operation speed and execution efficiency are high, the registers are always flipped with the clock, which consumes more energy and increases additional power consumption. In addition, because most processors are designed with synchronous circuits, the problem of global clock skew is serious, and there is a complex clock tree network, which is difficult to design, and the clock tree will seriously occupy the chip design area and power consumption. At the same time, in a synchronous circuit, all paths work under the same clock. In order to ensure that all logic operations can be completed in one clock cycle, the clock frequency will be limited by the delay of the critical path in the circuit and affect other paths at the same time, and the critical path Optimization is difficult, so the clock frequency is difficult to increase, limiting the performance of the entire processor. Therefore, the existing technology has the problems of high power consumption of the pipeline processor, severe global clock skew, limited clock frequency and slow speed.

Contents of the invention

In this embodiment, an asynchronous single-rail-based pipeline processor is provided to solve the problems of high power consumption, severe global clock skew, and limited clock frequency and slow speed of pipeline processors in the related art.

An asynchronous monorail-based pipeline processor of the present application includes: an asynchronous control module, an instruction fetch module, a decoding module, an execution module, an adaptive selection module, a memory access module, a write-back module, a storage module, and a control and status register , general-purpose registers, complete data communication between each module through asynchronous monorail handshake, wherein the asynchronous control module includes a plurality of control units, the plurality of control units are multiple phase decoupling Click units, and the multiple phase decoupling The Click units are cascaded with each other through handshaking, and are respectively connected to the corresponding pipelines.

Wherein, after the handshake between the phase decoupling Click units succeeds, a click signal for controlling the pipeline of the current stage is generated.

Wherein, the first-stage pipeline includes the instruction fetch module, the second-stage pipeline includes the decoding module, the third-stage pipeline includes the execution module, the fourth-stage pipeline includes the memory access module, and the fifth-stage pipeline includes The writeback module.

Wherein, the phase decoupling Click unit generates a click signal, so that the program counter calculates an instruction address according to the control signal, transmits the instruction address to the instruction fetch module, and simultaneously sends a request signal to the next-level phase decoupling Click unit, Wherein, the control signal is an electrical signal including jump, abnormality, and interruption, and the request signal is a request sent by the upper-level phase decoupling Click unit to the next-level phase decoupling Click unit. The electrical signal that the unit works on.

Wherein, the fetching module reads an instruction from the storage module according to the instruction address, and transmits the instruction to the decoding module.

Wherein, the decoding module performs a decoding operation on the instruction, and reads the data to be processed related to the instruction from the control and status register and the general register, and transmits the data to be processed to The execution module.

Wherein, the execution module executes a corresponding operation according to the data to be processed, and transmits the operation result to the memory access module after obtaining the operation result.

Wherein, the memory access module performs read and write operations on the storage module according to the operation result.

Wherein, the execution module includes a prediction flushing module, a jump module, and a bypass module, the prediction flushing module flushes incorrect prediction instructions, and the jump module generates a jump address according to a jump signal and an operation result to return For the program counter, the bypass module obtains the required data from the post module in advance according to the register address.

Wherein, the self-adaptive selection module acquires a calculation result from the execution module, and transmits the calculation result to the memory access module and the write-back module according to the control signal. The write-back module receives the operation result transmitted by the execution module and the memory access module, and writes the operation result back to the register. The storage module includes an instruction storage module for storing received instructions and a data storage module for storing received data.

Compared with related technologies, this embodiment provides an asynchronous single-rail-based pipeline processor, which solves the problems of high power consumption of pipeline processors, severe global clock skew, and limited clock speed in related technologies. , which realizes that the pipeline runs at a higher speed without a clock under low power consumption.

The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below, so as to make other features, objects, and advantages of the application more comprehensible.

Description of drawings

The drawings described here are used to provide a further understanding of the application and constitute a part of the application. The schematic embodiments and descriptions of the application are used to explain the application and do not constitute an improper limitation to the application. In the attached picture:

Fig. 1 is the structural representation of a kind of pipeline processor based on asynchronous monorail of the present application;

Fig. 2 is the logic diagram of the phase decoupling Click unit of the embodiment of the present application;

Fig. 3 is a logical schematic diagram of the control unit C_EX2MEM of the embodiment of the present application;

Fig. 4 is a logical schematic diagram of the control unit C_MEM2WB of the embodiment of the present application;

Fig. 5 is a logical schematic diagram of the first-level control unit of the asynchronous control module in the embodiment of the present application.

Detailed ways

In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application. Based on the embodiments provided in the present application, all other embodiments obtained by persons of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

Obviously, the accompanying drawings in the following description are only some examples or embodiments of the present application, and those skilled in the art can also apply the present application to other similar scenarios. In addition, it can also be understood that although such development efforts may be complex and lengthy, for those of ordinary skill in the art relevant to the content disclosed in this application, the technology disclosed in this application Some design, manufacturing or production changes based on the content are just conventional technical means, and should not be understood as insufficient content disclosed in this application.

Reference in this application to an "embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment can be included in at least one embodiment of the present application. The occurrences of this phrase in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. It is understood explicitly and implicitly by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

Unless otherwise defined, the technical terms or scientific terms involved in the application shall have the usual meanings understood by those with ordinary skill in the technical field to which the application belongs. Words such as "a", "an", "an" and "the" involved in this application do not indicate a limitation on quantity, and may indicate singular or plural numbers. The terms "comprising", "comprising", "having" and any variations thereof involved in this application are intended to cover non-exclusive inclusion; for example, a process, method, system, product or process that includes a series of steps or modules (units). The apparatus is not limited to the listed steps or units, but may further include steps or units not listed, or may further include other steps or units inherent to the process, method, product or apparatus. The words "connected", "connected", "coupled" and similar words mentioned in this application are not limited to physical or mechanical connection, but may include electrical connection, no matter it is direct or indirect. The "plurality" involved in this application refers to two or more than two. "And/or" describes the association relationship of associated objects, indicating that there may be three types of relationships. For example, "A and/or B" may indicate: A exists alone, A and B exist simultaneously, and B exists independently. The character "/" generally indicates that the contextual objects are an "or" relationship. The terms "first", "second", "third" and the like involved in this application are only used to distinguish similar objects, and do not represent a specific ordering of objects.

In this embodiment, an asynchronous single-rail-based pipeline processor is provided. Fig. 1 is a schematic structural diagram of an asynchronous monorail-based pipeline processor of the present application. The asynchronous monorail-based pipeline processor shown in Fig. 1 includes: an asynchronous control module, an instruction fetch module, a decoding module, and an execution module , self-adaptive selection module, memory access module, write-back module, storage module, control and status registers, and general-purpose registers. The data communication between each module is completed through asynchronous single-track handshake. The asynchronous control module includes multiple control units, multiple control The unit is a plurality of phase decoupling Click units, and the multiple phase decoupling Click units are cascaded with each other through handshaking, and are respectively connected to the corresponding pipelines. In the above embodiment, the fetching module corresponds to the first-stage pipeline 20 in the figure, the decoding module corresponds to the second-stage pipeline 30, the execution module corresponds to the third-stage pipeline 40, the memory access module corresponds to the fourth-stage pipeline 50, and the write-back The modules correspond to the fifth stage of the pipeline 60 .

In this embodiment, the click signal for controlling the pipeline at the current stage is generated after the handshake between the phase decoupling Click units succeeds. Phase decoupling Click units generate a click signal by handshaking with "request" and "response" signals, and use the click signal instead of the global clock of the synchronous circuit to control the click signal of the current stage of the pipeline. It is driven by events and belongs to a circuit without a global clock. As shown in the connection between the first control unit 101 and the first-stage pipeline 20 in Figure 1, the specific working process of the first control unit 101 and the first-stage pipeline 20 is: the first control unit 101 operates according to the enable signal of the processor The click signal of the program counter is generated to make the program counter operate once, and the address of the next instruction is calculated according to control signals such as jump, exception, and interrupt, and transmitted to the first-stage pipeline 20 . The control unit generates the request signal of the control unit of the next stage while generating the click signal of the current stage. Among them, the control signal is an electrical signal including jump, abnormality, and interruption, and the request signal is an electrical signal sent by the upper-stage phase decoupling Click unit to the next-stage phase decoupling Click unit to request the next-stage phase decoupling Click unit to work. Signal. The request signal is transmitted between the upper and lower levels of the adjacent control units, specifically summarized as: the upper control unit (such as the first control unit) sends a request signal to the adjacent lower control unit (such as the second control unit), wherein The request signal is an electrical signal that enables the lower-level control unit to control the operation of its corresponding pipeline. After the lower-level control unit receives the request signal sent by the upper-level control unit, the pipeline connected to it starts to work. At the same time, the upper-level control unit The level control unit sends a response signal to inform the upper level control unit that the control unit of this level has completed the control task. This embodiment only demonstrates a simple five-stage pipeline structure, and the content included in the pipeline can be changed if required by practical applications. Compared with the existing technology, this circuit replaces the global clock in the synchronous circuit by using the click signal generated by the Click module (control unit) in the asynchronous monorail circuit according to the state of the "request" and "response" signals. No external Clock signal input, so there is no complex clock network, which avoids the clock tree network occupying a large amount of chip area and increasing power consumption, and has the advantage of simple design, which can increase the operating speed of the processor and reduce power consumption.

It should be noted that before the processor starts to work, the initialization signal is required to initialize the processor. After initialization, the data inside the processor is in the initial state, and the asynchronous pipeline is in a stagnant state. When the enable signal level of the processor is high, the asynchronous single-rail pipeline processor starts to work. Therefore, each time the processor is used to process data, an initialization signal is required to initialize the processor to ensure that the data of each internal module, memory, and register are in an initial state.

In this embodiment, the first to fifth control units refer to different phase decoupling Click units, and the naming rules and corresponding relationship are: the first control unit is the phase decoupling Click unit C_PC, and the second control unit is the phase decoupling Click unit Unit C_IF2ID, the third control unit is a phase decoupling Click unit C_ID2EX, the fourth control unit is a phase decoupling Click unit C_EX2ME, and the fifth control unit is a phase decoupling Click unit C_MEM2WB. Correspondingly, the five control units respectively control five major registers, specifically: the first control unit C_PC controls the PC register, the second control unit C_IF2ID controls the IF2ID register, the third control unit C_ID2EX controls the ID2EX register, and the fourth control unit C_EX2ME controls The EX2ME register, the fifth control unit C_MEM2WB controls the CSR status register and the general register. The above corresponding relationship is only one of the specific embodiments, and does not mean that it can only have the above corresponding relationship. In the above-described embodiment, after the instruction fetching module (the first-stage pipeline 20) receives the instruction address, the work content and working mode of each module of the subsequent processor are as follows: the instruction fetching module reads the instruction from the storage module according to the instruction address, The instruction is transmitted to the decoding module. At the same time, the control unit C_IF2ID receives the request signal generated by the C_PC unit and the response signal returned by the C_ID2EX unit. After the handshake is successful, it generates a click signal to control the work of the current-level pipeline, generates a request signal for the next-level pipeline and returns a response signal to the upper-level pipeline. . The decoding module (the second-stage pipeline 30 ) decodes the instruction, reads the data to be processed related to the instruction from the control and status register and the general register, and transmits the data to be processed to the execution module. At the same time, the control unit C_ID2EX receives the request signal generated by the C_IF2ID unit and the response signal returned by the C_EX2ME unit. After the handshake is successful, it generates a click signal to control the work of the current-level pipeline, generates a request signal for the next-level pipeline and returns a response signal to the upper-level pipeline. . The execution module (the third-stage pipeline 40 ) executes corresponding operations according to the data to be processed, and transmits the operation results to the memory access module after obtaining the operation results. At the same time, the control unit C_EX2MEM receives the request signal generated by the C_ID2EX unit and the response signal returned by the C_MEM2WB unit. After the handshake is successful, it generates a click signal to control the work of the current pipeline, generates a request signal for the next pipeline and returns a response signal to the upper pipeline. . The memory access module (the fourth-stage pipeline 50 ) performs read and write operations on the storage module according to the calculation result. The adaptive selection module obtains the operation result from the execution module, and transmits the operation result to the memory access module and the write-back module according to the control signal. The write-back module (fifth-stage pipeline 60 ) receives the operation result transmitted by the execution module and the memory access module, and writes the operation result back to the register. The control units C_Wreg and C_Wcsr generate click signals for writing back to the CSR status register and the general register, which belong to the write-back control unit. At the same time, the control unit C_MEM2WB receives the two request signals generated by the C_EX2MEM unit and the response signals returned by the C_Wreg and C_Wcsr units. After the handshake is successful, it generates a click signal to control the work of the current pipeline, and at the same time generates a request signal for the next pipeline and returns it to the upper First stage pipeline acknowledge signal. Specifically, the control units C_Wreg and C_Wcsr are control units that control the CSR and REGISTER registers, and use phase decoupling Click units. The storage module includes an instruction storage module for storing received instructions and a data storage module for storing received data. In the above working mode and connection relationship, each level of pipeline is driven by the pulse signal generated by the completion of the event, and the frequency of the pulse signal of each level of pipeline is different, and the frequency is only limited by the longest path of the pipeline at this level, so the processor’s The processing speed is faster than synchronous circuits.

What needs to be added is that the above-mentioned execution module includes a prediction flushing module, a jump module, and a bypass module. The prediction flushing module flushes incorrect prediction instructions, and the jump module generates a jump address according to the jump signal and the operation result and returns it to The program counter and the bypass module obtain the required data from the post module in advance according to the register address, which can avoid the conflict between data and data.

For the register IF2ID used in the present invention, it is the second control unit C_IF2ID that controls the second control unit, which is equivalent to a data transmission switch. When the Click pulse generated by the second control unit C_IF2ID arrives, the switch is opened, and the upper-level pipeline is transmitted. data, otherwise closed. This relatively closed design can effectively prevent the data in the register from being disturbed or damaged when the corresponding control unit does not send out the Click pulse signal. It should be noted that the other registers used in the present invention have the same effect as the above-mentioned register IF2ID, that is, the switch is turned on when the click pulse arrives, and turned off for the rest of the time.

FIG. 2 is a logical schematic diagram of a phase decoupling Click unit according to an embodiment of the present application. First of all, the naming rules in the figure are: D is the module controlled by the phase decoupling Click unit, In_Data and Out_Data respectively represent the data input to the module and the data output by the module, In_Req and Out_Req represent the input request signal and the external output request respectively Signals, In_Ack and Out_Ack respectively represent the input acknowledgment signal and the output acknowledgment signal. Therefore, for the first control unit C_PC, there are only two signals, Out_Req and In_Ack, because the first control unit is not connected to the control unit before, so there is no need to output the response signal and the reception request signal. As shown in Figure 2, the working process of the phase decoupling Click unit is: Assume that In_Req=1, In_Ack=0, Out_Ack=1, Out_Req=0, the In_Req signal and the In_Ack signal are XORed, and the Out_Req signal and the Out_Ack signal are XORed together, then output The results are all 1, and then through the AND gate, a Click pulse is generated to trigger Pi and Po, In_Ack and Out_Req are flipped, and the values become 1. That is, the value of returning the response signal and generating the request signal is 1, that is, a handshake is completed. Through the above-mentioned phase decoupling Click unit, the Click pulse signal can be generated at the required time to drive the connected pipeline, and the generated Click signal can replace the global clock in the synchronous circuit, avoiding the clock tree network occupying a large amount of chip area and increasing power. consumption, and has the advantages of simple design, which can increase the operating speed of the processor and reduce power consumption.

It should be explained in detail that the control unit C_EX2MEM and the control unit C_MEM2WB are a pair of control units used in conjunction with each other. The combination of the two realizes the selection function of the handshake signal. Next, the working principle of the two is introduced.

Fig. 3 is a logical schematic diagram of the control unit C_EX2MEM of the embodiment of the present application. As shown in Figure 3, the C_EX2MEM control unit is a pre-handshake selector, which selects and outputs different handshake request signals according to the control signal. The Sel signal is XORed and XORed with the request signal generated last time, and the request signal is obtained through a register triggered by the click signal. When Sel is 1, the handshake generated request signal req2 is 1, and req1 is 0; when Sel is 0, the handshake generated request signal req1 is 1, and req2 is 0 at this time. Through the above design, the control unit C_EX2MEM can output different request signals according to different Sel values to control the corresponding pipeline to perform corresponding operations.

Fig. 4 is a logical schematic diagram of the control unit C_MEM2WB of the embodiment of the present application. As shown in Figure 4, the C_MEM2WB control unit is a post-handshake selector, which selects different request response signals for handshaking according to the control signal. The Sel signal and the response signal generated by the upper-level control unit are XOR and XOR respectively, and then the response signal is obtained through a register triggered by the Click signal, and the response signal is XORed with the request signal from the upper level, and the Click is obtained through combinational logic. Signal, the Click signal triggers the register to invert the request signal to the next stage of the pipeline. As shown in Figure 4, the C_MEM2WB control unit can realize the handshake function of two pairs of request response signals. Among them, the Sel signal is the same signal as the Sel of the above-mentioned C_EX2MEM unit, and the two control units are used together to realize the selection function of the handshake signal.

Fig. 5 is a logical schematic diagram of the first-level control unit of the asynchronous control module in the embodiment of the present application. As shown in Fig. 5, the control unit C_PC generates the click signal of the program counter according to the enable signal of the processor operation, so that the program counter performs one operation , calculate the address of the next instruction according to control signals such as jump, exception, and interrupt, and transmit it to the value-taking module. The first-level control unit generates the request signal of the next-stage control module C_IF2ID while generating the click signal of this stage. The C_PC unit is the first-level control unit of the pipeline, so it does not need the input of the request signal and the output of the response signal. D in the figure is the first-stage pipeline, which corresponds to the instruction fetch module. The first-stage pipeline D starts to work after receiving the click signal generated by the first control unit, and transmits the output data Out_Data to the next-stage pipeline.

It can be seen from the description of the above embodiments that the present invention has at least the following beneficial effects: the global clock in the synchronous circuit is replaced by the click signal by using an asynchronous monorail circuit, so the present invention does not need to design a clock tree network, and the power consumption of the clock tree network Therefore, the present invention can greatly reduce the power consumption of the processor circuit, save the designable area in the circuit at the same time, and provide a larger space for circuit modification and optimization. For the problem of critical path delay limitation in the circuit, the critical paths of each module are independent, which can better optimize the critical path.

The above examples only express several implementation modes of the present application, and the description thereof is relatively specific and detailed, but should not be construed as limiting the protection scope of the patent. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be determined by the appended claims.

Claims (7)

1. An asynchronous monorail-based pipelined processor, comprising: the system comprises an asynchronous control module, an instruction taking module, a decoding module, an executing module, a self-adaptive selection module, a memory access module, a write-back module, a storage module, a control and status register and a general register, wherein data communication is completed among the modules through asynchronous single-rail handshake, the asynchronous control module comprises a plurality of control units, the plurality of control units are a plurality of phase decoupling Click units, and the plurality of phase decoupling Click units are mutually cascaded through handshake and are respectively connected with corresponding pipelines;

after handshake between the phase decoupling Click units is successful, a Click signal for controlling the pipeline of the stage is generated;

the phase decoupling Click unit generates a Click signal, so that a program counter calculates an instruction address according to a control signal, the instruction address is transmitted to the instruction fetch module, and meanwhile, a request signal is sent to a next-stage phase decoupling Click unit, wherein the control signal is an electric signal comprising skip, abnormality and interruption, and the request signal is an electric signal which is sent by a previous-stage phase decoupling Click unit to the next-stage phase decoupling Click unit and requests the next-stage phase decoupling Click unit to work;

the self-adaptive selection module acquires an operation result from the execution module, transmits the operation result to the access module and the write-back module according to a control signal, and the write-back module receives the operation result transmitted by the execution module and the access module and writes the operation result back to a register; the data storage module is used for storing the received data;

wherein an initialization signal is required to initialize the processor before the processor begins operation.

2. The asynchronous monorail-based pipeline processor of claim 1, wherein a first stage pipeline comprises the finger fetch module, a second stage pipeline comprises the decode module, a third stage pipeline comprises the execute module, a fourth stage pipeline comprises the memory module, and a fifth stage pipeline comprises the write back module.

3. An asynchronous monorail-based pipeline processor according to claim 1, wherein the instruction fetch module reads instructions from the memory module based on the instruction address and transfers the instructions to the decode module.

4. A pipeline processor based on asynchronous monorail according to claim 3, wherein said decode module decodes said instruction and reads the data to be processed associated with said instruction from said control and status register, said general purpose register, and transfers said data to be processed to said execution module.

5. The pipeline processor based on asynchronous monorail of claim 4, wherein the execution module performs corresponding operations according to the data to be processed, and transmits the operation result to the memory module after obtaining the operation result.

6. The asynchronous monorail-based pipeline processor of claim 5, wherein the memory module performs read-write operations on the memory module according to the operation result.

7. The asynchronous monorail-based pipeline processor of claim 1, wherein the execution module comprises a predictive flush module, a skip module, and a bypass module, the predictive flush module flushing incorrect predicted instructions, the skip module generating a skip address based on a skip signal and an operation result and returning the skip address to the program counter, the bypass module obtaining the required data from the post module in advance based on the register address.

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