CN112272084B - Anti-attack and self-checking characteristic key generation system and method based on composite PUF - Google Patents

Abstract

The invention discloses a key generation system based on a compound PUF (physical unclonable function) with anti-attack and self-checking characteristics, which comprises a first-level PUF circuit module, an excitation generation module, a second-level PUF circuit module and a result output module, wherein: the first-level PUF circuit module receives original excitation and generates an output response with N bits, and registers the response in a register group; the excitation generation module receives the output response of the first-level PUF circuit module as a reset signal, and generates pseudo-random output according to the configured primitive polynomial after the reset is completed; the second-level PUF circuit module comprises two D trigger-based arbiter type PUF circuits with self-checking circuits, receives the pseudo-random output from the m-sequence generator as input excitation, and respectively and independently generates a response and a reliable mark; and the result output module uses the last bit signal from the m-sequence generator as a selection control signal to selectively output the response of the output result of the second-level PUF circuit module and the reliable mark.

Description

Composite PUF-based key generation system and method with anti-attack and self-inspection characteristics

technical field

The invention relates to the technical field of communication, in particular to a compound PUF-based key generation method with the characteristics of anti-attack and self-inspection.

Background technique

In recent years, with the rapid development of the Internet of Things and smart terminals, the issue of information security has gradually attracted more and more users' attention. Generally, information security issues are inseparable from encryption and decryption algorithms in cryptography. For most encryption applications, an essential premise is that keys can be safely generated, stored, and retrieved. Regardless of whether it is based on software or an encryption operation system based on software, the key is the core of the entire encryption operation system. In general embedded devices with encryption functions, the keys are stored in non-volatile memory, which is easily threatened by intrusive attacks or semi-intrusive attacks, resulting in the leakage and tampering of the keys. and other security issues.

Physical Unclonable Function PUF is a hardware function implementation circuit that depends on the physical characteristics of the chip itself. It is unclonable and unpredictable and can be used for key generation. However, with the introduction of the concept of PUF, attack methods against PUF have been emerging in an endless stream, such as channel measurement attack and machine learning modeling attack. Many attack technologies have been proved to be able to crack the PUF structure. In order to improve the anti-attack performance of a single PUF structure, in this scheme, PicoPUF and arbiter-type PUF based on D flip-flops are used to form a two-stage composite PUF as the key generation structure. At the same time, in order to make the generation of incentives also have randomness and further improve security, an easy-to-implement m-sequence generator is used instead of a state machine to control the generation of incentives.

Although the use of PUF to generate keys has the advantages of no need to save, easy to obtain, determined by process deviation, unique and unpredictable stimulus response pairs, but due to the special structure of the circuit itself, its output will inevitably be affected by the working conditions around the chip. (Voltage, temperature, etc.) are affected by changes, so the output of the PUF circuit contains noise. In traditional cryptography, based on the consideration of the security of the cryptographic algorithm, it is necessary to ensure that the key of the algorithm is reliable, stable, and random, so the output of the PUF circuit cannot meet the requirement of being directly used as the key. Existing solutions are usually by introducing output error correction technology, but new problems will arise: error correction technology will bring huge execution overhead and resource occupation, which is not suitable for small and medium-sized embedded devices with limited hardware and software resources.

Contents of the invention

The present invention proposes a compound PUF-based key generation method with anti-attack and self-inspection characteristics. In order to take into account the reliability of PUF output and reduce the use of resources, in this solution, the self-inspection mechanism is introduced to judge the current PUF Whether the output is reliable, if it is unreliable, give up using the current response output as the key of the encryption algorithm.

In order to achieve the above tasks, the present invention adopts the following technical solutions:

A composite PUF-based key generation system with anti-attack and self-inspection features, including a first-level PUF circuit module, an excitation generation module, a second-level PUF circuit module, and a result output module, wherein:

The first-level PUF circuit module includes N PicoPUF circuits arranged in parallel, the PicoPUF circuit is used to receive the original stimulus and generate an N-bit output response, and store the response in the register group;

The excitation generation module includes an m-sequence generator, and the m-sequence generator is used to receive the output response of the first-stage PUF circuit module as a reset signal, and after the reset is completed, a pseudo-random output is generated according to the configured primitive polynomial;

The second-stage PUF circuit module includes two D flip-flop-based arbiter-type PUF circuits, and a self-test circuit is set in the D flip-flop-based arbiter PUF circuit; the two D flip-flop-based The arbiter-type PUF circuit receives the pseudo-random output from the m-sequence generator as an input stimulus, and generates a response and a reliable flag independently;

The result output module includes two selectors, which use the last bit signal from the m-sequence generator as a selection control signal to select and output the response and reliability flag of the output result of the second-stage PUF circuit module.

Further, the PicoPUF circuit in the first-level PUF circuit module includes a D flip-flop ①, a D flip-flop ②, an SR latch ③, and a data selector ④, wherein:

When the D flip-flop ①② receives the reset signal clear, the Q port is reset to 0; then, the D flip-flop ①② flips under the action of the start signal, and the SR latch ③ connected to it will distinguish the two flip-flops Reverse the order of arrival of the signals, so as to stably output 0 or 1; under the selection of the data selector ④ through the original excitation, the signals at the upper and lower ends of the SR latch ④ can be selected and output.

Further, the m-sequence generator in the excitation generating module includes a circuit structure composed of a linear feedback shift register, and the circuit structure includes a linear feedback shift register composed of N D flip-flops and N feedback coefficient g configurations A register; wherein, the output of the Q port of the i (i=1...N) D flip-flop and the i-th g are XORed and used as the input of the D port of the i+1 D flip-flop.

Further, the output response from the first-stage PUF circuit module is used as a set signal to initialize the m-sequence generator; driven by the clock CLK, the Q port triggered by each clock cycle D changes, forming a pseudo-random as an m-sequence The output of the controller; the feedback coefficient g needs to be valued according to the primitive polynomial. When the value is 1, it means that the feedback of the path exists, otherwise, it means that it does not exist.

Further, in the second-stage PUF circuit module, the self-inspection circuit in the D flip-flop-based arbiter-type PUF circuit includes a delay module and a self-inspection module, and the delay module includes a data selector ①②③ and a delay unit ⑨, The self-test module includes 1-2 data distributor ④ ⑤, data selector ⑥, register ⑦ ⑧;

For the delay module, the delay data from path 1 are respectively connected to port 1 of data selector ①②, and the delay data from path 2 are respectively connected to port 0 and port 1 of data selector ①③; the output of data selector ① After passing through the delay unit ⑨, they are respectively connected to the 0 port of the data selector ②③;

For the self-test module, the output response of the arbiter D flip-flop is connected to the register ⑦ and the input of the 1-2 data distributor ⑤ after the 1-2 data distributor ④, and the 1 output and 0 output are respectively connected; The 1 output of the distributor ⑤ is connected to the 1 port of the data selector ⑥, and the 0 output and the output of the register ⑧ are connected to the 0 port of the data selector ⑥; the output of the data selector ⑥ is connected to the register ⑧ input port.

Further, the working process of the reliability self-inspection mechanism composed of the delay module and the self-inspection module is:

a) When K1=1, K2=1, the system is in the normal working state. At this time, the delay of path 1 and path 2 reaches the data port and clock port of the D flip-flop respectively through the data selector ②③, and the output response of the flip-flop Stored in the register REG1 after the 1-2 data distributor ④;

b) When K1=0, K2=1, S=1, the system is in the self-checking working state, the delay of path 1 plus the delay value _Tc of delay unit ⑨ passes through the data selector ② and reaches the data of the D flip-flop Port, path 2 remains unchanged; at this time, the output response of the flip-flop is stored in the register REG2 after passing through the 1-2 data distributor ④ and the data selector ⑥;

c) When K1=1, K2=0, S=0, the system is in the self-test working state, the delay of path 2 plus the delay value T _c of the delay unit ⑨ passes through the data selector ③ to the clock of the D flip-flop Port, path 1 remains unchanged; at this time, the output response of the flip-flop is ORed with the value from register REG2 after passing through 1-2 data distributor ④, and the result of the operation is stored in register REG2 after passing through data selector ⑥;

d) The result in register REG1 is the output response of the original input stimulus, and the result in register REG1 is a reliable flag; when the reliable flag is 1, it means that the input stimulus-output response is reliable, otherwise it is unreliable;

Among them, S is the input signal of data selector ①, data distributor ⑤, data selector ⑥, K1 is the input signal of data selector ② and data distributor ④, K2 is the input signal of data selector ③ and data distributor ④ .

A compound PUF key generation method based on anti-attack and self-inspection characteristics, comprising the following steps:

(1) select the original polynomial to configure the register of the feedback coefficient g of the m-sequence generator;

(2) The original input excitation is used as the input excitation of the first-stage PUF circuit module of the composite PUF, and each 1-bit original input excitation corresponds to the input excitation of each PicoPUF; first reset each PicoPUF through the clear signal, and then pass the start The rising edge of the signal gives each PicoPUF input signal. Under the selection of the input excitation, the output of the SR latch is selected and output;

(3) The first-stage PUF circuit module outputs a response of 64bit data length, in order to maintain the stability of the data, the output response result of the first-stage PUF is stored in the register REG;

(4) Use the result in the register REG as the set value of the m-sequence generator to initialize the excitation generation module; the m-sequence generator generates a pseudo-random number output under the drive of the clock signal, and the changed output is used as the second-stage PUF Input excitation of the circuit module;

(5) The two arbiter-type PUF circuits based on D flip-flops of the second-stage PUF circuit module receive the same input excitation, and output results of pseudo-random numbers generated by the m-sequence generator;

(6) The output response and the reliability sign of the second-stage PUF circuit module are used as the input of the result output module, and the output response and the reliability sign of the second-stage PUF circuit module are selectively output according to the output of the m-sequence generator;

(7) If the reliability flag F of the result output module is 1, it means that the currently selected output response R is reliable, and it can be used as 1-bit data of the key; if the reliability flag F of the result output module is 0, It shows that the current selected output response R is unreliable, give up the current output response R, and wait for the next input excitation signal from the m-sequence generator.

Compared with the prior art, the present invention has the following technical characteristics:

1. Use the physical unclonable function PUF to use the deviation of the process to generate the key, avoiding the information security problems of key leakage and tampering caused by storing the key in the memory.

2. In order to prevent a single PUF from being easily attacked by means of side channel attacks and machine learning attacks, and to improve the anti-attack performance of the system, a composite PUF structure is used instead of a single structure PUF, which makes the PUF structure more complex and can be used in a smaller Hardware resource consumption for higher security performance.

3. Use the m-sequence generator as the controller for excitation generation to meet the requirements of matching keys of different lengths.

4. In order to take into account that small and medium-sized embedded devices need to obtain high-reliability keys and reduce resource consumption, a self-test mechanism is introduced in the hardware circuit, and high-reliability keys can also be obtained without using error correction technology. Algorithm key, suitable for use needs of small and medium-sized embedded devices.

Description of drawings

Fig. 1 is the structural representation of the key generation system based on composite PUF of anti-attack and self-inspection characteristic that the present invention proposes;

Figure 2 is a schematic diagram of a single PicoPUF circuit structure;

Fig. 3 is a schematic diagram of the circuit structure of the m-sequence generator;

4 is a schematic structural diagram of an arbiter-type PUF circuit based on a D flip-flop;

FIG. 5 is a schematic structural diagram of an arbiter-type PUF circuit based on a D trigger with a self-checking structure.

Detailed ways

Please refer to Fig. 1, the present invention proposes a key generation system based on composite PUF with anti-attack and self-inspection characteristics, the system can be divided into 4 parts, which are respectively: 1. Consists of 64 PicoPUF+64bit triggers 2. An excitation generation module composed of an m-sequence generator; 3. A second-stage PUF circuit module composed of two D-triggered arbiter-type PUFs with a self-test structure; 4. The result output module is composed of two selectors.

The structure of PicoPUF is simple, with good reliability and uniqueness. 64 PicoPUF circuits are used in parallel to form the first-level PUF circuit module of the composite PUF key generation system, which generates a 64-bit output response after receiving the 64-bit original stimulus; in order to maintain The output response is stable, and the result is stored in the register group REG.

The m-sequence generator is composed of a linear feedback shift register, and receives the output response of the first-stage PUF circuit as a reset signal. After the reset is completed, a pseudo-random output is generated according to the configured primitive polynomial; the m-sequence generator can generate a random output The data can also generate regular output according to the reset signal. This structure is used in the scheme to avoid key storage and at the same time meet the demand for keys to be retrieved at any time.

The D-trigger-based arbiter-type PUF with a self-test structure introduces a self-test circuit structure into the traditional D-trigger-based arbiter PUF circuit structure, providing a simple method for reliability testing. Two D-trigger-based arbiter-type PUFs with self-checking structure are used to form the second-stage PUF circuit module, which receives the same pseudo-random output from the m-sequence generator as input excitation, and generates responses and reliable signs independently.

The result output module composed of two selectors uses the last bit signal from the m-sequence generator as a selection control signal to select and output the response and reliability flag of the second-stage PUF circuit module. For machine learning modeling attacks, using this simple structure increases the complexity of the system and increases the difficulty of cracking to obtain higher security performance.

Each part of the present invention will be described in detail below in conjunction with the accompanying drawings.

1. The first stage PUF circuit module

The first-level PUF circuit module mainly includes 64 PicoPUFs. The structure of a single PicoPUF circuit is shown in Figure 2. The structure includes:

D flip-flop ①, D flip-flop ②, SR latch ③, data selector ④. Among them, the Q' ports of the two D triggers are connected to their own D ports, the Q ports are respectively connected to the S port and the R port of the SR latch ③, and the outputs of the SR latch are respectively connected to the 1 port of the data selector ④ and 0 ports.

The design principle of this part is that the D flip-flop ①② flips under the trigger of the start signal, and the SR latch latches the result after the flip of the D flip-flop. After the original signal is used as the selection signal of the data selector ④ selection Under the action, the output responds to R'.

The detailed working process of this part of the circuit is as follows: first, when the D flip-flop ①② receives the reset signal clear, the Q port is reset to 0; then, the D flip-flop ①② flips under the action of the start signal, due to the difference in the manufacturing process , resulting in a slight difference in the flipping speeds of the two D flip-flops ①②, and the SR latch ③ connected to it will distinguish the order in which the flip-flop signals of the two flip-flops arrive, thus stably outputting 0 or 1. Finally, under the selection of the data selector ④ through the original excitation, the signals at the upper and lower ends of the SR latch ④ can be selected and output.

Since the PicoPUF circuit is a weak PUF, it only receives one stimulus signal and generates one output response, consuming less resources. At the same time, because of its good reliability and uniqueness, it is used as the first-level PUF circuit structure of the composite PUF structure in this solution.

2. Excitation generation module

The core of the excitation generation module based on the m-sequence generator is a circuit structure composed of a linear feedback shift register, as shown in Figure 3.

According to the key generation system based on composite PUF in Figure 1, the coefficient N in Figure 3 is 64. The circuit includes a linear feedback shift register composed of 64 D flip-flops and 64 feedback coefficient g configuration registers. Wherein, the output of the Q port of the i-th (i=1...N) D flip-flop and gi are XORed and used as the input of the D port of the i+1-th D flip-flop.

The design principle of this part is that the output response from the first-stage PUF circuit module is used as a set signal to initialize the m-sequence generator. Driven by the clock CLK, the Q port triggered by each clock cycle D changes, and the pseudo-random composed of {Q1, Q2, ... Q64} is the output of the m-sequence generator. g is the feedback coefficient, which needs to be valued according to the original polynomial. When the value is 1, it means that there is feedback on this path, otherwise, it means that it does not exist.

Since the D flip-flop-based arbiter-type PUF requires multi-bit input stimulus responses to obtain a 1-bit output response, a strategy needs to be introduced to automatically generate multiple sets of input stimulus for the D-trigger-based arbiter-type PUF to obtain different lengths The output response of the program uses the m-sequence generator instead of manual input. For the same value of N, corresponding to different primitive polynomials, the feedback coefficient g is configured according to different primitive polynomials, which further increases the complexity of the system and obtains higher security performance.

3. The second stage PUF circuit module

The circuit structure of a traditional D flip-flop-based arbiter-type PUF is shown in Figure 4. It mainly utilizes the characteristics that the line delay in the circuit inevitably has differences in the manufacturing process.

The design principle of this part is that the circuit forms two completely symmetrical delay paths by cascading multiple switch delay modules. Each switch delay model contains two symmetrical delay units. According to the selection signal, the two input signals pass through different The delay unit reaches the output. Due to the process deviation in the manufacturing process of the chip, there is a certain deviation in the delay time of the two paths that should be symmetrical in an ideal state, resulting in a difference in the time to reach the D flip-flop. When the path to the data port of the D flip-flop is later than the path to the clock port, a 0 signal is output; when the path to the data port of the D flip-flop is earlier than the path to the clock port, a 1 signal is output.

The arbiter-type PUF based on D flip-flop realizes the physical unclonable function by extracting the delay deviation of two symmetrical paths. Suppose the path delay to the data port of the D flip-flop is T ₁ , the path delay to the clock port is T ₂ , when the delay deviation ΔT=T ₁ -T ₂ >0, the response is a digital 0, and when ΔT<0, the response is a digital 1 . But there are two problems in practical application:

(1) When the delay deviation ΔT is small, its polarity is likely to change when the temperature and voltage change, resulting in a change in response. Only when the delay deviation ΔT is large, the output response will not be easily affected, that is, it will be reliable.

(2) For the D flip-flop, when ΔT>0, the hold timing needs to be satisfied, and when ΔT<0, the setup timing needs to be satisfied. Therefore, the output result is reliable only when the absolute value of the delay deviation is greater than a certain value.

Therefore, by introducing a threshold and judging the relative size of ΔT and the threshold to judge whether the output response of the circuit is reliable.

The D-trigger-based arbiter-type PUF with a self-test structure is shown in Figure 5:

On the basis of the structure in Figure 4, a delay module and a self-test module are added before and after the D flip-flop of the arbiter to form a reliability self-test mechanism. The delay module includes a data selector ①②③ and a delay unit ⑨. The self-test The module includes 1-2 data distributor ④ ⑤, data selector ⑥, register ⑦ ⑧.

Among them, for the delay module, the delay data from path 1 are respectively connected to port 1 of data selector ①②, and the delay data from path 2 are respectively connected to port 0 and port 1 of data selector ①③; data selector ① The outputs of are respectively connected to the 0 port of the data selector ②③ after passing through the delay unit ⑨. For the self-test module, the output response of the arbiter D flip-flop is connected to the register ⑦ and the input of the 1-2 data distributor ⑤ after the 1-2 data distributor ④, and the 1 output and 0 output are respectively connected; The 1 output of the distributor ⑤ is connected to the 1 port of the data selector ⑥, and the 0 output and the output of the register ⑧ are connected to the 0 port of the data selector ⑥; the output of the data selector ⑥ is connected to the register ⑧ input port.

The detailed working process of the reliability self-check mechanism is as follows:

a) When K1=1, K2=1, the system is in the normal working state. At this time, the delay of path 1 and path 2 reaches the data port and clock port of the D flip-flop respectively through the data selector ②③, and the output response of the flip-flop Stored in the register REG1 after passing through the 1-2 data distributor ④.

b) When K1=0, K2=1, S=1, the system is in the self-checking working state, the delay of path 1 plus the delay value _Tc of delay unit ⑨ passes through the data selector ② and reaches the data of the D flip-flop port, path 2 remains unchanged. At this time, the output response of the flip-flop is stored in the register REG2 after passing through the 1-2 data distributor ④ and the data selector ⑥.

c) When K1=1, K2=0, S=0, the system is in the self-test working state, the delay of path 2 plus the delay value T _c of the delay unit ⑨ passes through the data selector ③ to the clock of the D flip-flop port, path 1 remains unchanged. At this time, the output response of the flip-flop is processed with the value from the register REG2 through the 1-2 data distributor ④, and the operation result is stored in the register REG2 after passing through the data selector ⑥.

d) At this time, the result in the register REG1 is the output response of the original input stimulus, and the result in the register REG1 is the reliable flag. When the reliable flag is 1, it means that the input stimulus-output response is reliable, otherwise it is unreliable;

Among them, S is the input signal of data selector ①, data distributor ⑤, data selector ⑥, K1 is the input signal of data selector ② and data distributor ④, K2 is the input signal of data selector ③ and data distributor ④ .

The design principle of the reliability self-inspection mechanism is:

In operation b), the delay deviation changes from ΔT to ΔT ₁ =(T ₁ +T _c )-T ₂ ; in operation c), the delay deviation changes from ΔT to ΔT ₂ =T ₁ -(T ₂ +T _c ). have:

(1) When the result of the same OR operation is 1, it means that the output response of introducing the same delay into different paths is the same, and the polarity of ΔT ₁ and ΔT ₂ is the same, that is, ΔT ₁ ≥ 0, ΔT ₂ ≥ 0, or ΔT ₁ ≤ 0, ΔT ₂ ≤ 0. Since T _c is always a positive value, it can be judged that |ΔT|=|T ₁ -T ₂ |≥T _c is always established, and the original output response is considered reliable.

(2) When the result of the exclusive OR operation is 0, it means that the output responses of introducing the same delay into different paths are different, and the polarities of ΔT ₁ and ΔT ₂ are different, that is, ΔT ₁ >0, ΔT ₂ <0, or ΔT ₁ <0, ΔT ₂ >0. Since T _c is always a positive value, it can be judged that |ΔT|=|T ₁ -T ₂ |<T _c is always established, and the original output response is unreliable.

According to the technological requirements of the integrated circuit, we can easily know the requirements of the hold timing and setup timing of the D flip-flop, and the threshold value can be set as: T _c =nax{T _hold , T _setup } according to the technological requirements.

Since n-level delay modules can generate 2 ⁿ CRPs (Challenge Reponse Pairs, incentive-response pairs), higher security performance can be obtained by increasing the number of delay modules, and it is a strong PUF. In this scheme, it is used as the second-level circuit structure of the composite PUF structure. According to Figure 1 and Figure 4, the value of n is 64.

Based on the above technical solution, in order to reduce the chip cost of small and medium-sized embedded devices and reduce the use of hardware circuit resources, according to the key generation system based on composite PUF in Figure 1, the 64bit data length is used as the original incentive of this solution. The present invention further provides a method for generating a key based on a composite PUF with anti-attack and self-inspection characteristics, comprising the following steps:

(1) According to N=64, select an appropriate primitive polynomial to configure the register of the feedback coefficient g of the m-sequence generator. By selecting different primitive polynomials, different excitation generation modules can be constructed.

(2) The 64bit original input excitation is used as the input excitation of the first-stage PUF circuit module of the composite PUF, and each 1-bit original input excitation corresponds to the input excitation of each PicoPUF; first reset each PicoPUF through the clear signal, and then pass The rising edge of the start signal gives each PicoPUF input signal. Under the selection of the input stimulus, the output of the SR latch is selected for output.

(3) The first-stage PUF circuit outputs a response with a data length of 64 bits. In order to maintain data stability, the output response result of the first-stage PUF is stored in the register REG.

(4) Use the result in the register REG as the setting value of the m-sequence generator to initialize the excitation generation module. The m-sequencer generates a 64-bit pseudo-random number output driven by a clock signal. The output of this change is used as the input excitation of the second stage PUF circuit.

(5) The second-level structure of the composite PUF is composed of two arbiter-type PUFs based on D flip-flops with a self-checking structure, which accept the same input stimulus (pseudo-random number output result generated by the m-sequence generator).

(6) The output response and reliability flag of the second-stage PUF circuit module are used as the input of the result output module, and Q64 (the last bit signal of the m sequence generator) is used as the selection signal for the output response and reliability of the second-stage PUF circuit module The sex flag is used to select the output.

(7) If the reliability flag F of the result output module is 1, it means that the currently selected output response R is reliable, and it can be used as 1-bit data of the key; if the reliability flag F of the result output module is 0, It shows that the current selected output response R is unreliable, give up the current output response R, and wait for the next input excitation signal from the m-sequence generator.

In order to meet the needs of different encryption algorithms for algorithm keys of different lengths, this scheme achieves this goal by controlling the m-sequence generator to generate different times of excitation signals.

In the key generation scheme based on composite PUF, through the combination of PicoPUF and D-trigger-based arbiter PUF, plus the control of excitation generation by m-sequence generator, the structure of PUF becomes more complex, and can be Higher security performance at lower hardware cost.

The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them; although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: it can still apply to the foregoing embodiments Modifications to the technical solutions recorded, or equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of each embodiment of the application, and should be included in this application. within the scope of protection.

Claims (6)

1. A key generation system based on composite PUF of anti-attack and self-inspection characteristics, is characterized in that, comprises first-level PUF circuit module, excitation generation module, second-level PUF circuit module and result output module, wherein: The first-level PUF circuit module includes N PicoPUF circuits arranged in parallel, the PicoPUF circuit is used to receive the original stimulus and generate an N-bit output response, and store the response in the register group; The excitation generation module includes an m-sequence generator, and the m-sequence generator is used to receive the output response of the first-stage PUF circuit module as a reset signal, and after the reset is completed, a pseudo-random output is generated according to the configured primitive polynomial; The second-stage PUF circuit module includes two D flip-flop-based arbiter-type PUF circuits, and a self-test circuit is set in the D flip-flop-based arbiter PUF circuit; the two D flip-flop-based The arbiter-type PUF circuit receives the pseudo-random output from the m-sequence generator as an input stimulus, and generates a response and a reliable flag independently; The result output module includes two selectors, which use the last bit signal from the m-sequence generator as a selection control signal to select and output the response and reliability flag of the output result of the second-stage PUF circuit module. 2. The anti-attack and self-checking characteristic based on composite PUF key generation system according to claim 1, it is characterized in that, the PicoPUF circuit in the described first level PUF circuit module comprises D flip-flop 1., D triggers Device ②, SR latch ③, data selector ④, where: When the D flip-flop ①② receives the reset signal clear, the Q port is reset to 0; then, the D flip-flop ①② flips under the action of the start signal, and the SR latch ③ connected to it will distinguish the two flip-flops Reverse the order of arrival of the signals, so as to stably output 0 or 1; under the selection of the data selector ④ through the original excitation, the signals at the upper and lower ends of the SR latch ④ can be selected and output. 3. the anti-attack according to claim 1 and the key generation system based on the compound type PUF of self-inspection characteristic, it is characterized in that, the m-sequence generator in the described excitation generation module comprises a linear feedback shift register made of The circuit structure includes a linear feedback shift register composed of N D flip-flops and N feedback coefficient g configuration registers; wherein, the output of the Q port of the i-th D flip-flop and the i-th g are XORed As the input of the D port of the i+1th D flip-flop, i=1...N. 4. The key generation system based on composite PUF of anti-attack and self-inspection characteristics according to claim 1, characterized in that, in the second-level PUF circuit module, the arbiter type PUF circuit based on D flip-flop The self-inspection circuit includes a delay module and a self-inspection module. The delay module includes a data selector ①②③ and a delay unit ⑨. The self-inspection module includes a 1-2 data distributor ④⑤, a data selector ⑥, a register ⑦⑧; For the delay module, the delay data from path 1 are respectively connected to port 1 of data selector ①②, and the delay data from path 2 are respectively connected to port 0 and port 1 of data selector ①③; the output of data selector ① After passing through the delay unit ⑨, they are respectively connected to the 0 port of the data selector ②③; For the self-test module, the output response of the arbiter D flip-flop is connected to the register ⑦ and the input of the 1-2 data distributor ⑤ after the 1-2 data distributor ④, and the 1 output and 0 output are respectively connected; The 1 output of the distributor ⑤ is connected to the 1 port of the data selector ⑥, and the 0 output and the output of the register ⑧ are connected to the 0 port of the data selector ⑥; the output of the data selector ⑥ is connected to the register ⑧ input port. 5. the key generation system based on composite PUF of anti-attack and self-inspection characteristic according to claim 4, it is characterized in that, the work of the reliability self-inspection mechanism that is formed jointly by described delay module and self-inspection module The process is: a) When K1=1, K2=1, the system is in the normal working state. At this time, the delay of path 1 and path 2 reaches the data port and clock port of the D flip-flop respectively through the data selector ②③, and the output response of the flip-flop Stored in the register REG1 after the 1-2 data distributor ④; b) When K1=0, K2=1, S=1, the system is in the self-checking working state, the delay of path 1 plus the delay value _Tc of delay unit ⑨ passes through the data selector ② and reaches the data of the D flip-flop Port, path 2 remains unchanged; at this time, the output response of the flip-flop is stored in the register REG2 after passing through the 1-2 data distributor ④ and the data selector ⑥; c) When K1=1, K2=0, S=0, the system is in the self-test working state, the delay of path 2 plus the delay value T _c of the delay unit ⑨ passes through the data selector ③ to the clock of the D flip-flop Port, path 1 remains unchanged; at this time, the output response of the flip-flop is ORed with the value from register REG2 after passing through 1-2 data distributor ④, and the result of the operation is stored in register REG2 after passing through data selector ⑥; d) The result in register REG1 is the output response of the original input stimulus, and the result in register REG1 is a reliable flag; when the reliable flag is 1, it means that the input stimulus-output response is reliable, otherwise it is unreliable; Among them, S is the input signal of data selector ①, data distributor ⑤, data selector ⑥, K1 is the input signal of data selector ② and data distributor ④, K2 is the input signal of data selector ③ and data distributor ④ . 6. A key generation method based on composite PUF of anti-attack and self-inspection characteristics, it is characterized in that, comprising the following steps: (1) select the original polynomial to configure the register of the feedback coefficient g of the m-sequence generator; (2) The original input excitation is used as the input excitation of the first-stage PUF circuit module of the composite PUF, and each 1-bit original input excitation corresponds to the input excitation of each PicoPUF; first reset each PicoPUF through the clear signal, and then pass the start The rising edge of the signal is given to each PicoPUF input signal; under the selection of the input excitation, the output of the SR latch is selected and output; (3) The first-stage PUF circuit module outputs a response of 64bit data length, in order to maintain the stability of the data, the output response result of the first-stage PUF is stored in the register REG; (4) Use the result in the register REG as the set value of the m-sequence generator to initialize the excitation generation module; the m-sequence generator generates a pseudo-random number output under the drive of the clock signal, and the changed output is used as the second-stage PUF Input excitation of the circuit module; (5) The two arbiter-type PUF circuits based on D flip-flops of the second-stage PUF circuit module receive the same input excitation, and output results of pseudo-random numbers generated by the m-sequence generator; (6) The output response and reliability flag of the second-stage PUF circuit module are used as the input of the result output module, and the output response and reliability flag of the second-stage PUF circuit module are selected and output according to the last bit signal of the m-sequence generator ; (7) If the reliability flag F of the result output module is 1, it means that the currently selected output response R is reliable, and it can be used as 1-bit data of the key; if the reliability flag F of the result output module is 0, It shows that the current selected output response R is unreliable, give up the current output response R, and wait for the next input excitation signal from the m-sequence generator.

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