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TWI594344B - Semiconductor device manufacturing method and flip chip mounting adhesive - Google Patents

Semiconductor device manufacturing method and flip chip mounting adhesive Download PDF

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Publication number
TWI594344B
TWI594344B TW102128059A TW102128059A TWI594344B TW I594344 B TWI594344 B TW I594344B TW 102128059 A TW102128059 A TW 102128059A TW 102128059 A TW102128059 A TW 102128059A TW I594344 B TWI594344 B TW I594344B
Authority
TW
Taiwan
Prior art keywords
adhesive
semiconductor device
reaction rate
less
resin
Prior art date
Application number
TW102128059A
Other languages
English (en)
Other versions
TW201413840A (zh
Inventor
Sayaka Wakioka
Hiroaki Nakagawa
Yoshio Nishimura
Shujiro Sadanaga
Original Assignee
Sekisui Chemical Co Ltd
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Filing date
Publication date
Application filed by Sekisui Chemical Co Ltd filed Critical Sekisui Chemical Co Ltd
Publication of TW201413840A publication Critical patent/TW201413840A/zh
Application granted granted Critical
Publication of TWI594344B publication Critical patent/TWI594344B/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
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    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/482—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of lead-in layers inseparably applied to the semiconductor body (electrodes)
    • H01L23/4827—Materials
    • H01L23/4828—Conductive organic material or pastes, e.g. conductive adhesives, inks
    • C—CHEMISTRY; METALLURGY
    • C08—ORGANIC MACROMOLECULAR COMPOUNDS; THEIR PREPARATION OR CHEMICAL WORKING-UP; COMPOSITIONS BASED THEREON
    • C08K—Use of inorganic or non-macromolecular organic substances as compounding ingredients
    • C08K9/00—Use of pretreated ingredients
    • C08K9/04—Ingredients treated with organic substances
    • C08K9/06—Ingredients treated with organic substances with silicon-containing compounds
    • C—CHEMISTRY; METALLURGY
    • C09—DYES; PAINTS; POLISHES; NATURAL RESINS; ADHESIVES; COMPOSITIONS NOT OTHERWISE PROVIDED FOR; APPLICATIONS OF MATERIALS NOT OTHERWISE PROVIDED FOR
    • C09J—ADHESIVES; NON-MECHANICAL ASPECTS OF ADHESIVE PROCESSES IN GENERAL; ADHESIVE PROCESSES NOT PROVIDED FOR ELSEWHERE; USE OF MATERIALS AS ADHESIVES
    • C09J163/00—Adhesives based on epoxy resins; Adhesives based on derivatives of epoxy resins
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/563—Encapsulation of active face of flip-chip device, e.g. underfilling or underencapsulation of flip-chip, encapsulation preform on chip or mounting substrate
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Description

半導體裝置之製造方法及覆晶構裝用接著劑
本發明係關於一種可抑制空隙而實現高可靠性之半導體裝置之製造方法。又，本發明係關於一種用於該半導體裝置之製造方法之覆晶構裝用接著劑。
隨著半導體裝置之小型化及高密度化，使用在表面形成有多個突起電極之半導體晶片之覆晶構裝來作為將半導體晶片構裝於基板之方法受到關注並迅速擴展開來。
對於覆晶構裝，作為用以確保接合部分之連接可靠性之方法，一般採用如下方法：將半導體晶片之突起電極與基板之電極部接合之後，於半導體晶片與基板之間隙注入液狀密封接著劑(底膠，underfill)並使其硬化。然而，使用底膠之覆晶構裝存在製造成本較高，底膠填充需要花費時間，縮小電極間之距離及半導體晶片與基板之距離時存在極限等問題。
因此，近年來，揭示有於基板上塗佈糊狀接著劑之後，搭載半導體晶片之方法；於半導體晶圓或半導體晶片上供給膜狀或糊狀接著劑之後，將附有接著劑之半導體晶片搭載於基板上之方法等所謂先塗佈型之覆晶構裝。尤其是將附有接著劑之半導體晶片搭載於基板上時，可於半導體晶圓上一次供給接著劑，並且藉由切割而可一次且大量地生產附有接著劑之半導體晶片，因此可期待大幅之製程縮短。
然而，先塗佈型之覆晶構裝存在以下情形，即，於使半導體晶片之突起電極與基板之電極部接觸時，半導體晶片或基板與接著劑之間夾入空氣而產生空隙，或於將半導體晶片搭載於基板上時之熱壓接步驟中，由於來自接著劑之揮發成分而產生空隙。此種空隙會導致電極間之短路，或成為於接著劑中產生裂痕之要因。又，對於先塗佈型之覆晶構裝，由於在熱壓接步驟中同時進行突起電極之接合與接著劑之熱硬化，故而難以同時進行精度高之突起電極之接合與空隙之抑制。
為了抑制空隙，揭示有藉由在加壓環境下進行接著劑之熱硬化而使空隙收縮之方法；將半導體晶片與基板暫時接合之後，藉由將暫時接合體於加壓環境下加熱而縮小空隙之方法等(例如專利文獻1~3)。然而，即便為該等方法，尤其是於將附有接著劑之半導體晶片搭載於基板上之情形時，由於基板之凹凸而容易夾入空氣，因此仍未達到充分地抑制空隙之程度。
專利文獻1：日本特開2004-311709號公報
專利文獻2：日本特開2009-004462號公報
專利文獻3：日本專利第4640380號公報
本發明之目的在於提供一種可抑制空隙而實現高可靠性之半導體裝置之製造方法。又，本發明之目的在於提供一種用於該半導體裝置之製造方法之覆晶構裝用接著劑。
本發明係一種半導體裝置之製造方法，係具有步驟1~3：步驟1：將形成有具有由焊料構成之前端部之突起電極之半導體晶片經由接著劑於基板上進行位置對準；步驟2：將上述半導體晶片加熱至焊料熔融點以上之溫度，使上述半導體晶片之突起電極與上述基板之電極部熔融接合，並使上述接著劑暫時接著；及步驟3：將上述接著劑於加壓環境下加熱而去除空隙；且上述接著劑藉由示差掃描熱量測定及小澤法求出之活化能△E為100 kJ/mol以下，於260℃2秒後之反應率為20%以下，於260℃4秒後之反應率為40%以下。
以下，詳述本發明。
本發明人為了同時實現精度高之突起電極之接合與空隙之抑制，而研究如下方法：將半導體晶片加熱至焊料熔融點以上之溫度，使半導體晶片之突起電極與基板之電極部確實地接合，其後，將接著劑於加壓環境下加熱而去除空隙。然而，於此種方法中，即便於加壓環境下進行加熱，在接合突起電極時接著劑之硬化過度進行之情況時，亦無法充分地去除空隙。
本發明者亦考慮藉由調整接合突起電極時之條件來抑制接著劑之硬化，但為了接合突起電極必須保持在焊料熔融點以上之溫度(240~280℃左右)，因此僅藉由條件之調整對於抑制接著劑之硬化而言存在極限。
因此，必須使用即便經過接合突起電極時之熱歷程亦可儘量抑制硬化之接著劑，即硬化速度(反應速度)相對較慢之接著劑作為接著劑。然而，先前，接著劑之反應速度之評價方法缺乏客觀性或定量性。
另一方面，於熱分析、反應速度分析等領域中，已知有根據試樣之利用示差掃描熱量測定(DSC測定，Differential scanning calorimetry)所獲得之資料而求出活化能△E、及固定溫度下到達固定之反應率之時間即所謂「小澤法」之分析方法。
本發明人研究對半導體裝置之製造方法中所使用之接著劑應用小澤法。結果本發明人發現：利用示差掃描熱量測定及小澤法，可對將接著劑於一定溫度下保持一定時間時之反應率進行更客觀且定量地評價，藉由使用利用此種方法求出之活化能△E、於260℃2秒後之反應率及260℃4秒後之反應率滿足特定範圍之接著劑，可同時實現精度高之突起電極之接合與空隙之抑制，從而完成本發明。
於本發明之半導體裝置之製造方法中，首先進行步驟1，即，將形成有具有由焊料構成之前端部之突起電極之半導體晶片經由接著劑於基板上進行位置對準。
於上述進行位置對準之步驟1中，一般而言，使用覆晶接合機等構裝用裝置，使相機識別半導體晶片之突起電極、基板之電極部、及設置於半導體晶片及基板上之對準標記之位置，藉此於X、Y方向及旋轉方向(θ方向)上自動進行位置對準。
作為上述半導體晶片，例如可列舉由矽、鎵砷等半導體構成，且表面形成有具有由焊料構成之前端部之突起電極之半導體晶片。再者，具有由焊料構成之前端部之突起電極只要前端部由焊料構成，可使突起電極之一部分由焊料構成，亦可使突起電極整體由焊料構成。
供給上述接著劑之方法並無特別限定，例如可列舉將膜狀之接著劑貼附於基板上或半導體晶片上之方法；將糊狀之接著劑填充於注射器中，並於注射器前端安裝精密噴嘴，使用分滴器(dispenser)裝置噴出至基板上之方法等。
又，亦可使用以下方法，即，藉由常壓層壓、真空層壓等預先於晶圓貼附膜狀之接著劑，或藉由旋轉塗佈法等塗佈或印刷糊狀之接著劑來形成塗膜之後，藉由刀片切割、雷射切割等單片化為半導體晶片。於常壓層壓中存在夾入空氣之情形，但亦可使用與去除空隙之步驟3同樣之加壓烘箱 (例如PCO-083TA(NTT Advanced Technology公司製造))等，將接著劑於加壓環境下加熱而去除空隙。
上述接著劑藉由示差掃描熱量測定及小澤法求出之活化能△E為100 kJ/mol以下，於260℃2秒後之反應率為20%以下，於260℃4秒後之反應率為40%以下。
藉由示差掃描熱量測定及小澤法求出之活化能△E、於260℃2秒後之反應率及260℃4秒後之反應率滿足上述範圍之接著劑可稱為以下接著劑，即，由於硬化速度(反應速度)相對較慢且反應速度之溫度依賴性較小，故而於使接著劑暫時接著之步驟2中即便經過接合突起電極時之熱歷程亦可儘量抑制硬化，且硬化之不均較少。藉由使用此種接著劑，於使接著劑暫時接著之步驟2中使突起電極確實地接合，其後，進行去除空隙之步驟3，藉此可同時實現精度高之突起電極之接合與空隙之抑制。
再者，示差掃描熱量測定可使用DSC裝置(例如DSC6220(SII NanoTechnology公司製造))進行。又，小澤法可使用反應速度分析軟體(例如SII NanoTechnology公司製造)進行，意指下述所示之分析方法。
首先，對試樣進行3次以上升溫速度不同之示差掃描熱量測定，對溫度T之倒數與升溫速度B之對數(logB)進行繪圖。根據下述式(1)，由所獲得之直線之斜率算出活化能△E。其次，根據下述式(2)之定溫劣化式，由活化能△E算出於260℃保持2秒或於260℃保持4秒之情形時之反應率。(參照小澤丈夫，熱測定1、2(1974)及T.Ozawa,Bull.Chem.Soc.Japan 38,1881(1965))
logB-0.4567△E/RT=const. (1)
式(2)中，τ表示定溫劣化時間。
若上述活化能△E超過100 kJ/mol，則接著劑之反應速度之溫度依賴性變大，容易受到使接著劑暫時接著之步驟2中之溫度之不均、面內之溫度分佈等之影響。結果使得空隙之控制或接著劑向上下電極間之咬入之控制變得困難。上述活化能△E較佳為90 kJ/mol以下，更佳為80 kJ/mol以下。
上述活化能△E之下限並無特別限定，較佳之下限為50 kJ/mol。若上述活化能△E未達50 kJ/mol，則有即便於相對較低之溫度下接著劑之硬化亦容易進行，而接著劑之儲存穩定性降低之情形。
若上述於260℃2秒後之反應率超過20%，或上述於260℃4秒後之反應率超過40%，則於暫時接著接著劑之步驟2中會導致接著劑之硬化進行，即便進行去除空隙之步驟3亦無法充分地去除空隙，或於暫時接著接著劑之步驟2中在突起電極熔融接合之前接著劑之硬化進行，於上下電極間發生接著劑之咬入而接合不良。上述於260℃2秒後之反應率較佳為15%以下，更佳為12%以下。上述於260℃4秒後之反應率較佳為30%以下，更佳為25%以下。
上述於260℃2秒後之反應率之下限並無特別限定，較佳之下限為3%。上述於260℃4秒後之反應率之下限並無特別限定，較佳之下限為10%。若上述於260℃2秒後之反應率未達3%，或上述於260℃4秒後之反應率未達10%，則有接著劑之硬化需要花費時間，無法於短時間製造半導體裝置之情形。
上述接著劑可為膜狀，亦可為糊狀，特佳為膜狀接著劑。於上述接著劑為糊狀之情形時，必須對每1個半導體晶片供給上述接著劑。相對於此，於上述接著劑為膜狀之情形時，於基板或晶圓上一次供給上述接著劑，藉由切割可一次且大量地生產附有接著劑之半導體晶片， 因此期待大幅之製程縮短。
又，一般膜狀之接著劑之熔融黏度高，因此使用膜狀之接著劑難以同時實現精度高之突起電極之接合與空隙之抑制，但於本發明之半導體裝置之製造方法中，藉由使用利用示差掃描熱量測定及小澤法求出之活化能△E、於260℃2秒後之反應率及260℃4秒後之反應率滿足上述範圍之接著劑，即便上述接著劑為膜狀亦可同時實現精度高之突起電極之接合與空隙之抑制。
上述接著劑較佳為至少含有熱硬化性樹脂與熱硬化劑，較佳為進而含有硬化促進劑。
活化能△E係反應系統所固有，故而例如藉由選擇組合之熱硬化性樹脂、熱硬化劑、硬化促進劑等之種類，可將接著劑之活化能△E調整為上述範圍。另一方面，反應速度亦依賴於反應系統之濃度，故而例如藉由調整各成分之含量，尤其是硬化促進劑之添加量，可將接著劑之反應率調整為上述範圍。具體而言，有硬化促進劑之添加量越多，反應速度越上升，越少反應速度越降低之傾向。然而，適宜之硬化促進劑之添加量根據各個反應系統而異，因此為了將接著劑之反應率調整為上述範圍，必須適當調整各成分之含量。
上述熱硬化性樹脂並無特別限定，例如可列舉藉由加成聚合、聚縮合、聚加成、加成縮合、開環聚合等反應而硬化之化合物。作為上述熱硬化性樹脂，具體而言，例如可列舉：脲樹脂、三聚氰胺樹脂、酚系樹脂、間苯二酚樹脂、環氧樹脂、丙烯酸系樹脂、聚酯樹脂、聚醯胺樹脂、聚苯并咪唑樹脂、鄰苯二甲酸二烯丙酯樹脂(diallyl phthalateresin)、二甲苯樹脂、烷基-苯樹脂、環氧丙烯酸酯樹脂、矽樹脂、胺基甲酸酯樹脂等。其中，就容易將接著劑之活化能△E及反應率調整為上述範圍之觀點而言，又，就硬化物之物性等觀點而言，較佳為環氧樹脂。
上述環氧樹脂較佳為官能基濃度較低，即環氧當量較高。由於環氧當量較高之環氧樹脂與熱硬化劑之反應機率較低而反應性較低，故而藉由使用此種環氧樹脂，容易將接著劑之反應率調整為上述範圍。上述環氧樹脂之環氧當量更佳為200以上，進而較佳為250以上。
上述環氧樹脂並無特別限定，例如可列舉：雙酚A型、雙酚F型、雙酚AD型、雙酚S型等雙酚型環氧樹脂、苯酚酚醛清漆型、甲酚酚醛清漆型等酚醛清漆型環氧樹脂、間苯二酚型環氧樹脂、三苯酚甲烷三縮水甘油醚等芳香族環氧樹脂、萘型環氧樹脂、茀型環氧樹脂、環戊二烯型或二環戊二烯型環氧樹脂、聚醚改質環氧樹脂、NBR改質環氧樹脂、CTBN改質環氧樹脂、及該等之氫化物等。其中，較佳為具有大體積結構之環戊二烯型或二環戊二烯型環氧樹脂。由於環戊二烯型或二環戊二烯型環氧樹脂之立體阻礙較大而反應性較低，故而藉由使用此種環氧樹脂，容易將接著劑之反應率調整為上述範圍。該等環氧樹脂可單獨使用，亦可併用2種以上。
上述環氧樹脂可為常溫下液狀之環氧樹脂，可為常溫下固體之環氧樹脂，亦可適當組合該等而使用。
上述常溫下液狀之環氧樹脂中，作為市售品，例如可列舉：EPICLON 840、840-S、850、850-S、EXA-850CRP(以上均為DIC公司製造)等雙酚A型環氧樹脂，EPICLON 830、830-S、EXA-830CRP(以上均為DIC公司製造)等雙酚F型環氧樹脂，EPICLON HP-4032、HP-4032D(以上均為DIC公司製造)等萘型環氧樹脂，EPICLON EXA-7015(DIC公司製造)、EX-252(Nagase chemteX公司製造)等氫化雙酚A型環氧樹脂，EX-201(Nagase chemteX公司製造)等間苯二酚型環氧樹脂等。
上述常溫下固體之環氧樹脂中，作為市售品，例如可列舉：EPICLON 860、10550、1055(以上均為DIC公司製造)等雙酚A型環氧樹 脂，EPICLON EXA-1514(DIC公司製造)等雙酚S型環氧樹脂，EPICLON HP-4700、HP-4710、HP-4770(以上均為DIC公司製造)等萘型環氧樹脂，EPICLON HP-7200系列(DIC公司製造)等二環戊二烯型環氧樹脂，EPICLON HP-5000、EXA-9900(以上均為DIC公司製造)等甲酚酚醛清漆型環氧樹脂等。
上述熱硬化劑並無特別限定，可配合上述熱硬化性樹脂適當選擇先前公知之熱硬化劑。於使用環氧樹脂作為上述熱硬化性樹脂之情形時，作為上述熱硬化劑，例如可列舉：酸酐系硬化劑、酚系硬化劑、胺系硬化劑、雙氰胺等潛伏性硬化劑、陽離子系觸媒型硬化劑等。該等熱硬化劑可單獨使用，亦可併用2種以上。其中，就硬化物之物性等優異之觀點而言，較佳為酸酐系硬化劑。
上述酸酐系硬化劑中，作為市售品，例如可列舉YH-306、YH-307(以上均為三菱化學公司製造，常溫(25℃)下液狀)、YH-309(三菱化學公司製造，酸酐系硬化劑，常溫(25℃)下固體)等。
上述熱硬化劑之含量並無特別限定，於使用環氧樹脂作為上述熱硬化性樹脂，且使用與環氧基等量反應之熱硬化劑之情形時，上述熱硬化劑之含量相對於接著劑中所含有之環氧基之總量之較佳之下限為60當量，較佳之上限為110當量。若含量未達60當量，則有無法使接著劑充分地硬化之情形。即便含量超過110當量亦未特別有助於接著劑之硬化性，且有因過剩之熱硬化劑揮發而成為空隙之原因之情形。含量之更佳之下限為70當量，更佳之上限為100當量。
上述硬化促進劑並無特別限定，例如可列舉咪唑系硬化促進劑、三級胺系硬化促進劑等。其中，就容易將接著劑之反應率調整為上述範圍之觀點而言，又，就容易進行用以調整硬化物之物性等之反應系統之控制之觀點而言，較佳為咪唑系硬化促進劑。
上述咪唑系硬化促進劑並無特別限定，例如可列舉FUJICURE 7000(T&K TOKA公司製造，常溫(25℃)下液狀)、利用氰基乙基保護咪唑之1位之1-氰基乙基-2-苯基咪唑、經異三聚氰酸保護鹼性之咪唑系硬化促進劑(商品名「2MA-OK」，四國化成工業公司製造，常溫(25℃)下固體)、2MZ、2MZ-P、2PZ、2PZ-PW、2P4MZ、C11Z-CNS、2PZ-CNS、2PZCNS-PW、2MZ-A、2MZA-PW、C11Z-A、2E4MZ-A、2MAOK-PW、2PZ-OK、2MZ-OK、2PHZ、2PHZ-PW、2P4MHZ、2P4MHZ-PW、2E4MZ‧BIS、VT、VT-OK、MAVT、MAVT-OK(以上均為四國化成工業公司製造)等。該等咪唑系硬化促進劑可單獨使用，亦可併用2種以上。
上述硬化促進劑之含量並無特別限定，相對於熱硬化劑100重量份之較佳之下限為0.5重量份，較佳之上限為50重量份。若含量未達0.5重量份，則有為了接著劑之熱硬化而必須於高溫下進行長時間之加熱之情形。若含量超過50重量份，則有接著劑之儲存穩定性不充分，或因過剩之硬化促進劑揮發而成為空隙之原因之情形。含量之更佳之下限為1重量份，更佳之上限為30重量份。
於上述接著劑為膜狀之接著劑之情形時，較佳為進而含有高分子量化合物。藉由使用上述高分子量化合物，可對接著劑賦予製膜性、可撓性等，並且可使接著劑之硬化物具有強韌性，確保較高之接合可靠性。
上述高分子量化合物並無特別限定，例如可列舉：脲樹脂、三聚氰胺樹脂、酚系樹脂、間苯二酚樹脂、環氧樹脂、丙烯酸系樹脂、聚酯樹脂、聚醯胺樹脂、聚苯并咪唑樹脂、鄰苯二甲酸二烯丙酯樹脂、二甲苯樹脂、烷基-苯樹脂、環氧丙烯酸酯樹脂、矽樹脂、胺基甲酸酯樹脂等公知之高分子量化合物。其中，較佳為具有環氧基之高分子量化合物。
藉由添加上述具有環氧基之高分子量化合物，可使接著劑之硬化物表現優異之可撓性。即，上述接著劑之硬化物兼備源自作為上述熱 硬化性樹脂之環氧樹脂之優異之機械強度、耐熱性及耐濕性與源自上述具有環氧基之高分子量化合物之優異之可撓性，因此成為耐冷熱循環性、耐回流焊性、尺寸穩定性等優異者，且表現較高之接合可靠性及較高之導通可靠性。
上述具有環氧基之高分子量化合物只要為末端及/或側鏈(側鏈位)具有環氧基之高分子量化合物，則並無特別限定，例如可列舉：含環氧基之丙烯酸系橡膠、含環氧基之丁二烯橡膠、雙酚型高分子量環氧樹脂、含環氧基之苯氧基樹脂、含環氧基之丙烯酸系樹脂、含環氧基之胺基甲酸酯樹脂、含環氧基之聚酯樹脂等。其中，就可獲得含有大量環氧基之高分子化合物，且硬化物之機械強度及耐熱性成為更優異者之觀點而言，較佳為含環氧基之丙烯酸系樹脂。該等具有環氧基之高分子量化合物可單獨使用，亦可併用2種以上。
於使用上述具有環氧基之高分子量化合物，尤其是含環氧基之丙烯酸系樹脂作為上述高分子量化合物之情形時，上述具有環氧基之高分子量化合物之重量平均分子量之較佳之下限為1萬，較佳之上限為100萬。若重量平均分子量未達1萬，則有接著劑之製膜性不充分，或無法充分地提高接著劑之硬化物之可撓性之情形。若重量平均分子量超過100萬，則有於進行位置對準之步驟1中難以將接著劑供給為一定厚度，或於去除空隙之步驟3中接著劑之熔融黏度變得過高而流動性降低，無法充分地去除空隙之情形。
於使用上述具有環氧基之高分子量化合物，尤其是含環氧基之丙烯酸系樹脂作為上述高分子量化合物之情形時，上述具有環氧基之高分子量化合物較佳為官能基濃度較低，即環氧當量較高。環氧當量較高之高分子量化合物之反應性較低，因此藉由使用此種高分子量化合物，容易將接著劑之反應率調整為上述範圍。上述具有環氧基之高分子量化合物之環氧當量更佳為200以上，進而較佳為250以上。
上述接著劑中之上述高分子量化合物之含量並無特別限定，較佳之下限為3重量%，較佳之上限為30重量%。若含量未達3重量%， 則有無法獲得對於熱應變之充分之可靠性之情形。若含量超過30重量%，則有接著劑之耐熱性降低之情形。
上述接著劑較佳為進而含有無機填料。上述無機填料之含量較佳為60重量%以下。若含量超過60重量%，則有於去除空隙之步驟3中接著劑之流動性降低，無法充分地去除空隙之情形。
上述接著劑中之上述無機填料之含量之下限並無特別限定，就確保接著劑之硬化物之強度及接合可靠性之觀點而言，較佳之下限為10重量%。
上述無機填料並無特別限定，例如可列舉二氧化矽、氧化鋁、氮化鋁、氮化硼、氮化矽、碳化矽、氧化鎂、氧化鋅等。其中，就流動性優異之觀點而言，較佳為球狀二氧化矽，更佳為利用甲基矽烷偶合劑、苯基矽烷偶合劑等進行表面處理之球狀二氧化矽。藉由使用經表面處理之球狀二氧化矽，可抑制接著劑之增黏，且可於去除空隙之步驟3中極有效地去除空隙。
上述無機填料之平均粒徑並無特別限定，就接著劑之透明性、流動性、接合可靠性等觀點而言，較佳為0.01~1 μm左右。
上述接著劑視需要亦可進而含有稀釋劑、觸變(thixotropy)賦予劑、溶劑、無機離子交換體、滲出防止劑、咪唑矽烷偶合劑等接著性賦予劑、密合性賦予劑、橡膠粒子等應力緩和劑等其他添加劑。
製造上述接著劑之方法並無特別限定，例如可列舉於熱硬化性樹脂及熱硬化劑中，視需要調配規定量之硬化促進劑、高分子量化合物、無機填料及其他添加劑並進行混合之方法。上述混合之方法並無特別限定，例如可列舉使用勻相分散機、萬能混合機、班布里混合機、捏合機、珠磨機、均質機等之方法。
上述接著劑之自常溫至焊料熔融點之溫度區域中之最低熔融黏度之較佳之下限為10 Pa‧s，較佳之上限為104 Pa‧s。若最低熔融黏度未達10 Pa‧s，則有圓角(fillet)之伸出過多，而污染其他元件之情形。若最低熔融黏度超過104 Pa‧s，則有無法充分地去除空隙之情形。
再者，自常溫至焊料熔融點之溫度區域中之最低熔融黏度可使用流變 計進行測定。
於本發明之半導體裝置之製造方法中，繼而進行步驟2，即，將上述半導體晶片加熱至焊料熔融點以上之溫度，使上述半導體晶片之突起電極與上述基板之電極部熔融接合，並使上述接著劑暫時接著。
又，使上述接著劑暫時接著之步驟2一般亦使用覆晶接合機等構裝用裝置進行。
焊料熔融點通常為215~235℃左右。上述焊料熔融點以上之溫度之較佳之下限為240℃，較佳之上限為300℃。若溫度未達240℃，則有突起電極未充分地熔融，而無法形成電極接合之情形。若溫度超過300℃，則有自接著劑產生揮發成分而使空隙增加之情形。又，有接著劑之硬化進行，於去除空隙之步驟3中接著劑之流動性降低，而無法充分地去除空隙之情形。
關於將附有上述接著劑之半導體晶片加熱至焊料熔融點以上之溫度之時間(保持時間)，較佳之下限為0.1秒，較佳之上限為5秒。若保持時間未達0.1秒，則有突起電極未充分地熔融，而無法形成電極接合之情形。若保持時間超過5秒，則有自接著劑產生揮發成分而使空隙增加之情形。又，有接著劑之硬化進行，於去除空隙之步驟3中接著劑之流動性降低，而無法充分地去除空隙之情形。
於使上述接著劑暫時接著之步驟2中，較佳為對上述半導體晶片施加壓力。關於壓力，只要為可形成電極接合之壓力，則並無特別限定，較佳為0.3~3 MPa。
於本發明之半導體裝置之製造方法中，繼而進行步驟3，即，將上述接著劑於加壓環境下加熱而去除空隙。
所謂加壓環境下，意指高於常壓(大氣壓)之壓力環境下。可認為，於上述去除空隙之步驟3中，不僅不使空隙成長，而且可積極地去除空隙，因此於本發明之半導體裝置之製造方法中，即便於接著劑中夾入空氣之情形亦可去除空隙。
作為將上述接著劑於加壓環境下加熱之方法，例如可列舉使 用加壓烘箱(例如PCO-083TA(NTT Advanced Technology公司製造))之方法等。
上述加壓烘箱之壓力之較佳之下限為0.2 MPa，較佳之上限為10 MPa。若壓力未達0.2 MPa，則有無法充分地去除空隙之情形。若壓力超過10 MPa，則有接著劑本身發生變形，對半導體裝置之可靠性造成不良影響之情形。壓力之更佳之下限為0.3 MPa，更佳之上限為1 MPa。
將上述接著劑於加壓環境下加熱時之加熱溫度之較佳下限為60℃，較佳上限為150℃。其中，將上述接著劑於加壓環境下加熱時，可保持於一定溫度及一定壓力，亦可一面升溫及/或升壓一面階段性地改變溫度及/或壓力。
又，為了更確實地去除空隙，將上述接著劑於加壓環境下加熱時之加熱時間較佳為10分鐘以上。
於本發明之半導體裝置之製造方法中，進行去除空隙之步驟3後，亦可進行使接著劑完全硬化之步驟4。
作為使上述接著劑完全硬化之方法，例如可列舉於進行去除空隙之步驟3後，於加壓環境下直接升高溫度而使接著劑完全硬化之方法；及於常壓下加熱接著劑而使其完全硬化之方法等。使上述接著劑完全硬化時之加熱溫度並無特別限定，較佳為150~200℃左右。
於本發明之半導體裝置之製造方法中，使用藉由示差掃描熱量測定及小澤法求出之活化能△E、於260℃2秒後之反應率及260℃4秒後之反應率滿足上述範圍之接著劑，於使接著劑暫時接著之步驟2中使突起電極確實地接合，其後，進行去除空隙之步驟3，藉此可同時實現精度高之突起電極之接合與空隙之抑制。又，用於本發明之半導體裝置之製造方法，且藉由示差掃描熱量測定及小澤法求出之活化能△E、於260℃2秒後之反應率及260℃4秒後之反應率滿足上述範圍之覆晶構裝用接著劑亦為本發明之一。
根據本發明，可提供一種可抑制空隙而實現較高之可靠性之 半導體裝置之製造方法。又，根據本發明，可提供一種用於該半導體裝置之製造方法之覆晶構裝用接著劑。
以下列舉實施例對本發明之態樣進行更詳細地說明，但本發明並不僅限定於該等實施例。
(實施例1~5及比較例1~5)
(1)接著劑之製造
將表1中記載之各材料按照表2中記載之調配組成添加於作為溶劑之MEK(methyl ethyl ketone，甲基乙基酮)中，使用勻相分散機進行攪拌混合，藉此製造接著劑溶液。將所獲得之接著劑溶液使用敷料器以乾燥後之厚度成為30 μm之方式塗佈於脫模PET膜上並進行乾燥，藉此製造膜狀之接著劑。利用脫模PET膜(保護膜)保護所獲得之接著劑層之表面直至使用時。
(2)示差掃描熱量測定及小澤法
對所獲得之接著劑於升溫速度1、2、5、10℃/min之4個條件下進行示差掃描熱量測定，並對溫度T之倒數與升溫速度B之對數(logB)進行繪圖。根據上述式(1)，由所獲得之直線之斜率算出活化能△E。其次，根據上述式(2)之定溫劣化式，由活化能△E算出於260℃保持2秒或260℃保持4秒之情形時之反應率。
再者，使用DSC6220(SII NanoTechnology公司製造)及反應速度分析軟體(SII NanoTechnology公司製造)。
(3)半導體裝置之製造
(3-1)進行位置對準之步驟1及使接著劑暫時接著之步驟2
準備形成有具有由焊料構成之前端部之突起電極之半導體晶片(WALTS MB50-0101JY，焊料熔融點235℃，厚度100 μm，WALTS公司製造)與具有Ni/Au電極之基板(WALTS-KIT MB50-0101JY，WALTS公司製造)。將接著劑之單面之保護膜剝離，使用真空貼合機(ATM-812M，Takatori公司製造)，以階段溫度80℃、真空度80 Pa貼附於半導體晶片上。使用覆晶接合機(FC-3000S，Toray Engineering公司製造)，將半導體晶片經由接著劑於基板上進行位置對準(步驟1)，於接合階段溫度120℃之條件下，在160℃接觸並升溫至260℃，以0.8 MPa施加負載2秒，使半導體晶片之突起電極與基板之電極部熔融接合，並使接著劑暫時接著(步驟2)。
(3-2)去除空隙之步驟3
將所獲得之暫時接著體投入至加壓烘箱(PCO-083TA，NTT Advanced Technology公司製造)中，根據以下之加壓、加熱條件將接著劑於加壓環境下加熱而去除空隙(步驟3)，並使接著劑完全硬化，獲得半導體裝置。
<加壓、加熱條件>
STEP1：以10分鐘自25℃固定升溫至80℃，0.5 MPa
STEP2：於80℃保持60分鐘，0.5 MPa
STEP3：自80℃固定升溫至170℃，0.5 MPa
STEP4：於170℃保持10分鐘，0.5 MPa
STEP5：以30分鐘自170℃降溫至25℃，0.5 MPa
STEP6：以60分鐘固定降溫至室溫，0.5 Mpa
<評價>
對實施例及比較例中所獲得之半導體裝置進行以下之評價。將結果示於表2。
(1)空隙之有無
使用超音波探查影像裝置(C-SAM D9500，日本Barnes公司製造)，觀察去除空隙之步驟3前後之半導體裝置之空隙，並對空隙之有無進行評價。將空隙產生部分之面積相對於半導體晶片面積未達1%之情形設為○，將1%以上且未達5%之情形設為△，將5%以上之情形設為×。
(2)電極接合狀態
使用研磨機對半導體裝置進行剖面研磨，並使用顯微鏡觀察電極接合部之電極接合狀態。將上下電極間無接著劑之咬入，且電極接合狀態良好之情形設為○，將上下電極間雖有少量接著劑之咬入，但上下電極已接合之情形設為△，將上下電極間有接著劑之咬入，且上下電極完全未接合之情形設為×。
(3)可靠性評價(TCT試驗(Temperature Cycle Test，溫度循環試驗))
對半導體裝置進行-55℃~125℃(30分鐘/循環)之冷熱循環試驗，每100個循環測定導通電阻值。將導通電阻值與冷熱循環試驗前之初期導通電阻值相比變化5%以上之時間點設為NG判定，對保持有未達5%之導通電阻值之循環數進行評價。將循環數為1000個循環以上之情形設為○，將300個循環以上且未達1000個循環之情形設為△，將未達300個循環之情形設為×。
[產業上之可利用性]
根據本發明，可提供一種可抑制空隙而實現高之可靠性之半導體裝置之製造方法。又，根據本發明，可提供一種用於該半導體裝置之製造方法之覆晶構裝用接著劑。

Claims (8)

  1. 一種半導體裝置之製造方法，係具有步驟1~3，步驟1：將形成有具有由焊料構成之前端部之突起電極之半導體晶片經由接著劑於基板上進行位置對準；步驟2：將上述半導體晶片加熱至焊料熔融點以上之溫度，使上述半導體晶片之突起電極與上述基板之電極部熔融接合，並使上述接著劑暫時接著；步驟3：將上述接著劑於加壓環境下加熱而去除空隙；且上述接著劑藉由示差掃描熱量測定及小澤法求出之活化能△E為100kJ/mol以下，於260℃2秒後之反應率為20%以下，於260℃4秒後之反應率為40%以下。
  2. 如申請專利範圍第1項之半導體裝置之製造方法，其中，接著劑至少含有熱硬化性樹脂及熱硬化劑，且上述熱硬化性樹脂為環氧樹脂。
  3. 如申請專利範圍第1項之半導體裝置之製造方法，其中，接著劑進而含有硬化促進劑。
  4. 如申請專利範圍第2項之半導體裝置之製造方法，其中，接著劑進而含有硬化促進劑。
  5. 如申請專利範圍第1、2、3或4項之半導體裝置之製造方法，其中，接著劑進而含有無機填料，且上述無機填料之含量為60重量%以下。
  6. 如申請專利範圍第1、2、3或4項之半導體裝置之製造方法，其中，接著劑為膜狀接著劑。
  7. 如申請專利範圍第5項之半導體裝置之製造方法，其中，接著劑為膜狀接著劑。
  8. 一種覆晶構裝用接著劑，係用於申請專利範圍第1、2、3、4、5、6或7項之半導體裝置之製造方法，且藉由示差掃描熱量測定及小澤法求出 之活化能△E為100kJ/mol以下，於260℃2秒後之反應率為20%以下，於260℃4秒後之反應率為40%以下。
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