TWI384630B - 製造電子部件封裝結構之方法 - Google Patents
製造電子部件封裝結構之方法 Download PDFInfo
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- TWI384630B TWI384630B TW094112389A TW94112389A TWI384630B TW I384630 B TWI384630 B TW I384630B TW 094112389 A TW094112389 A TW 094112389A TW 94112389 A TW94112389 A TW 94112389A TW I384630 B TWI384630 B TW I384630B
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- Prior art keywords
- electronic component
- uncured resin
- resin layer
- substrate
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- 238000004519 manufacturing process Methods 0.000 title claims description 36
- 238000004806 packaging method and process Methods 0.000 title description 2
- 239000011347 resin Substances 0.000 claims description 132
- 229920005989 resin Polymers 0.000 claims description 132
- 239000000758 substrate Substances 0.000 claims description 105
- 239000000463 material Substances 0.000 claims description 22
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 17
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 13
- 238000010438 heat treatment Methods 0.000 claims description 9
- 239000010949 copper Substances 0.000 claims description 8
- 229910052802 copper Inorganic materials 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 6
- 239000004065 semiconductor Substances 0.000 claims description 3
- 239000010935 stainless steel Substances 0.000 claims description 3
- 229910001220 stainless steel Inorganic materials 0.000 claims description 3
- 239000003822 epoxy resin Substances 0.000 claims description 2
- 229920000647 polyepoxide Polymers 0.000 claims description 2
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- 229920001955 polyphenylene ether Polymers 0.000 claims description 2
- 230000000149 penetrating effect Effects 0.000 claims 1
- 238000000034 method Methods 0.000 description 23
- 238000006243 chemical reaction Methods 0.000 description 11
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- 230000007547 defect Effects 0.000 description 8
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- 238000010586 diagram Methods 0.000 description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 6
- 239000010931 gold Substances 0.000 description 6
- 230000008646 thermal stress Effects 0.000 description 6
- 239000002184 metal Substances 0.000 description 5
- 229910052751 metal Inorganic materials 0.000 description 5
- 238000007747 plating Methods 0.000 description 4
- 239000000654 additive Substances 0.000 description 3
- ROOXNKNUYICQNP-UHFFFAOYSA-N ammonium persulfate Chemical compound [NH4+].[NH4+].[O-]S(=O)(=O)OOS([O-])(=O)=O ROOXNKNUYICQNP-UHFFFAOYSA-N 0.000 description 3
- 239000007864 aqueous solution Substances 0.000 description 3
- 238000009713 electroplating Methods 0.000 description 3
- 238000005530 etching Methods 0.000 description 3
- 239000011810 insulating material Substances 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- MHAJPDPJQMAIIY-UHFFFAOYSA-N Hydrogen peroxide Chemical compound OO MHAJPDPJQMAIIY-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 2
- 239000004020 conductor Substances 0.000 description 2
- ORTQZVOHEJQUHG-UHFFFAOYSA-L copper(II) chloride Chemical compound Cl[Cu]Cl ORTQZVOHEJQUHG-UHFFFAOYSA-L 0.000 description 2
- RBTARNINKXHZNM-UHFFFAOYSA-K iron trichloride Chemical compound Cl[Fe](Cl)Cl RBTARNINKXHZNM-UHFFFAOYSA-K 0.000 description 2
- 230000001141 propulsive effect Effects 0.000 description 2
- 229910021592 Copper(II) chloride Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- 229910021578 Iron(III) chloride Inorganic materials 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910001870 ammonium persulfate Inorganic materials 0.000 description 1
- 239000012935 ammoniumperoxodisulfate Substances 0.000 description 1
- KVBCYCWRDBDGBG-UHFFFAOYSA-N azane;dihydrofluoride Chemical compound [NH4+].F.[F-] KVBCYCWRDBDGBG-UHFFFAOYSA-N 0.000 description 1
- 238000005452 bending Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
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- 238000007772 electroless plating Methods 0.000 description 1
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- 229910052709 silver Inorganic materials 0.000 description 1
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- 238000004544 sputter deposition Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 238000005382 thermal cycling Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
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- A—HUMAN NECESSITIES
- A47—FURNITURE; DOMESTIC ARTICLES OR APPLIANCES; COFFEE MILLS; SPICE MILLS; SUCTION CLEANERS IN GENERAL
- A47J—KITCHEN EQUIPMENT; COFFEE MILLS; SPICE MILLS; APPARATUS FOR MAKING BEVERAGES
- A47J47/00—Kitchen containers, stands or the like, not provided for in other groups of this subclass; Cutting-boards, e.g. for bread
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07
- H01L21/4814—Conductive parts
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- H01L21/4857—Multilayer substrates
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the groups H01L21/18 - H01L21/326 or H10D48/04 - H10D48/07 e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/568—Temporary substrate used as encapsulation process aid
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49822—Multilayer substrates
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- H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
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- H01L25/04—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of semiconductor or other solid state devices all the devices being of a type provided for in a single subclass of subclasses H10B, H10F, H10H, H10K or H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H10D89/00
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- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
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- H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
- H05K1/186—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit manufactured by mounting on or connecting to patterned circuits before or during embedding
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- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68377—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support with parts of the auxiliary support remaining in the finished device
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Description
本發明係有關於製造電子部件封裝結構的方法,且更特別是,製造具有一電子部件埋入於一絕緣層之結構的電子部件封裝結構的方法。
於習知技術中,有具有電子部件埋入於絕緣層之結構的電子部件封裝結構。如製造此電子部件封裝結構的方法之一示例,如顯示於第1A圖的下部圖中,一電子部件200的第一凸塊202係反扣結合(flip-chip bonded)於一下部銅箔100之上,且之後,一未充填樹脂102係填充於在該電子部件200及該下部銅箔100之間的空隙中。
之後,如顯示於第1A圖的中間圖及上部圖中,一未固化樹脂膜106a(其中備置傳導柱104)及一上部銅箔110係配置於該電子部件200之上,且之後,這此元件係對著該電子部件200之側推進。因此,如顯示於第1B圖,該電子部件200係埋入於一樹脂膜106a,且該上部銅箔110亦黏附至該樹脂膜106a之上。於此時,該傳導柱104係分別電性連接至該下部銅箔100及該上部銅箔110。
之後,該內層絕緣層106(其中埋入該電子部件200)係藉由退火方式固化該未固化樹脂膜106a而獲得。之後,如顯示於第1C圖,經由該傳導柱104而彼此連接的線路圖案108係藉由圖案化該上部銅箔110及下部銅箔100而分別形成於該內層絕緣層106的兩個表面側上。之後,視情況,堆疊連接至該等線路圖案108的一預定增層線路。
此方法類似如專利文件1(專利申請公開案(KOKAI)2002-261449)所述的製造方法。
然而,從該內層絕緣層而由不同材料所形成的該未充填樹脂102係存在於該電子部件200之上。因此,當使用熱循環的信賴度測試執行時,由於這些元件的熱膨脹係數不同而產生熱應力。因此,存在有在該內層絕緣層106或是該電子部件及該等線路圖案108之間接觸失敗的產生之問題。同樣地,當該電子部件是面朝上設置時,該電子部件的背側必需藉由晶粒黏著材料而結合於該基板之上,該晶粒黏著材料之材料是不同於該內層絕緣材料。因此,類似的問題很容易發生。
此外,藉由對該未固化樹脂膜推進該電子部件,埋入該電子部件於該樹脂膜的方法係可使用。依據此方法,該未固化樹脂膜106a係具有某程度上的可撓性,雖然在某些例子中,因為該電子部件必需施加以一相對高壓力而推進,諸如裂痕等等的缺陷可能會產生於機械強度弱的該電子部件內。
本發明之目的係提供製造具有電子部件埋入絕緣層之結構的電子部件封裝結構之方法,其係能防止各種在使用熱循環之信賴度測試的缺陷,且亦減少該電子部件的損害。
本發明係有關於製造電子部件封裝結構的方法,其包含下列步驟:形成一第一未固化樹脂層於一基板上;配置一電子部件於該第一未固化樹脂層;形成一覆蓋該電子部件的第二未固化樹脂層,以及藉由退火來固化該第一未固化樹脂層及該第二未固化樹脂層,以獲得一絕緣層(其中埋入該電子部件)。
於本發明的較佳實施例中,首先,該第一未固化樹脂層係暫時地黏附於該基板之上,且之後,在加熱該第一未固化樹脂的狀態下,該電子部件係配置於該第一未固化樹脂之上。於此時,該電子部件係以該電子部件不會損傷的程度而推進,且因此,該電子部件係暫時地黏附於該第一未固化樹脂層之上。
之後,該未固化樹脂膜係配置於該電子部件之上,且之後,在真空狀態下加熱時,該未固化樹脂膜係被推至該電子部件側。因此,形成覆蓋該電子部件的該第二未固化樹脂層。於此時,由於藉由加熱,該第二未固化樹脂層在其流體化狀態下,覆蓋該電子部件,因此可能可防虛電子部件損傷的狀況。
之後,該第一及第二未固化樹脂層係藉由退火而固化,因而可獲得埋入該封裝結構之絕緣膜。因此,該電子部件係藉由該絕緣膜而黏附至該基板之上。
此外,由於可選擇與該第一及第二未固化樹脂層相同的絕緣材料,因此該電子部件係可埋入於由相同材料所製成的該第一內層絕緣層。因此,在施用熱循環的信賴度測試至該電子部件封裝結構時,可抑制由不同熱膨脹係數所產生的熱應力。因此,可克服產生於內層絕緣層的裂痕與該電子部件及該等線路圖案間所產生不良接觸等等的缺陷,而因此可改良該電子部件封裝結構的信賴度。換言之,在實際使用該電子部件封裝結構於該第一實施時,由於可防止由於熱應力所產生的裂痕及接觸缺陷。
同樣的,於本發明的較佳實施例中,該基板係一第一暫存基板,且製造電子部件封裝結構之方法又包含形成一基板的步驟,其中,備置通過該第一未固化樹脂層及該第二未固化樹脂層的傳導柱,且在形成該第二未固化樹脂層的步驟之前與獲得該絕緣層的步驟之後,一第二暫存基板係配置於該第二未固化樹脂層之上;以及又包含,在獲得該絕緣層的步驟之後,選擇性移除該第一暫存基板及該第二暫存基板。
於此模式中,首先,該第一未固化樹脂層係暫時地黏附於該第一暫存基板(如可移除金屬基板,如上述發明)之上,之後配置該電子部件於其上,且之後,形成用於覆蓋該電子部件的該第二未固化樹脂層。
之後,形成通過該第一及第二未固化樹脂層的傳導柱,且之後,該第二暫存基板係配置於該第二未固化樹脂層之上。除此之外,可推進垂直備置於該第二暫存基板上的該等傳導柱,而進入該第一及第二未固化樹脂層。
之後,藉由退火方式而固化該第一及第二未固化樹脂層,以獲得埋入該電子部件的該絕緣層,且之後,選擇性移除該第一及第二暫存基板。
於此實施例中,如同上述發明,由於該電子部件係可埋入於由相同材料所製成的絕緣層中,因而可改善該電子部件封裝結構的信賴度。此外,最後移除該暫存基板,且因此,埋入該電子部件的該絕緣膜係可作為核心基板(core substrate)。因此,可獲得在厚度下減少的電子部件封裝結構。
如上述,根據本發明,該電子部件可埋入於由相同材料所製成的絕緣層中,而不會遭受損害。因此,可改善該電子部件封裝結構的信賴度。
第1A圖至第1C圖係為顯示在習知技術中,製造電子部件封裝結構之方法的截面圖;第2A圖至第2J圖係顯示依據本發明第一實施例中,製造電子部件封裝結構的方法之截面圖;第3A圖至第3E圖係顯示依據本發明第二實施例中,製造電子部件封裝結構的方法之截面圖;第4A圖至第4K圖係顯示依據本發明第三實施例中,製造電子部件封裝結構的方法之截面圖;以及第5A圖至第5J圖係顯示依據本發明第四實施例中,製造電子部件封裝結構的方法之截面圖。
本發明之實施例將參考下文伴隨的圖式來解釋之。
第2A圖至第2J圖係顯示依據本發明第一實施例中,製造電子部件封裝結構之方法的截面圖。
在第一實施例中的製造電子部件封裝結構的方法中,如第2A圖所示,首先備置了一核心基板10,於該核心基板10的兩表面上分別備置了一第一線路圖案12。該核心基板10係由如玻璃環氧樹脂等等的絕緣體所製成。貫通孔10a係備置於該核心基板10中而貫穿該核心基板10。一傳導柱11係備置於該等貫通孔10a中,且在該核心基板10的兩表面上的該等第一線路圖案12係經由該等傳導柱11而彼此連接。
之後,如顯示於第2B圖,一未固化(B階(半固化狀態))樹脂膜係於真空狀態下鋪設於該核心基板的上表面側上。因此,形成例如具有膜厚為10-100骻厚度的一第一未固化樹脂層14。如適用來形成該第一未固化樹脂層14之狀況的一示例,可使用於該真空狀態下的壓力:133 Pa,溫度:120℃,推進力:1 MPa,以及加工時間:15秒。因此,該第一未固化樹脂係暫時黏附至該核心基板10之上。作為該第一未固化樹脂層14的材料,可以使用環氧樹脂、聚醯亞胺樹脂、聚苯醚樹脂等等。
之後,如第2C圖所示,備置一電子部件20及電子部件固定裝置40。於此實施例中,一半導體晶片是列為電子部件20。連接墊21a係備置於該電子部件20的一表面上,且該電子部件20的其餘面積是由鈍化膜21b所覆蓋。作為電子部件20,諸如電容部件等被動元件等等可被使用附加至該半導體晶片,且其厚度係設定至100骻或更少(50骻為較佳)。
同樣地,電子部件固定裝置40係具有一台面42及一轉換頭44,於該台面42係固定有固定主體,且該轉換頭係使用來轉換該電子部件。該台面42係具有一加熱功能且能夠加熱該固定主體。該轉換頭44係能以真空接觸舉起該電子部件並移動於x-y-z(水平/垂直)方向,且因此,能置該電子部件於該電子部件對準於一預定位置的狀態。此外,該轉換頭係具有一加熱功能與向下施加一壓力至該電子部件的功能。作為該電子部件固定裝置40,可以使用諸如一反扣結合器(flip-chip bonder)、一固定器等等的結合工具。
之後,如同樣顯示於第2C圖,該第一未固化樹脂層14所形成於其上的該核心基板10,係配置於該台面42之上。之後,該電子部件20係藉由該轉換頭44而舉起,使得該電子部件的連接墊21a係筆直向上(面朝上),且之後,該電子部件20係以該電子部件對準於一預定位置的狀態下,而配置於該第一未固化樹脂層14之上。
於此時,藉由該台面42及該轉換頭44,加熱該第一未固化樹脂層14,且同時,藉由該轉換頭44的一低壓,加壓該電子部件20朝向該第一未固化樹脂層14側。藉由該轉換頭44所施加至該電子部件20的壓力係設定至不會造成該電子部件20損害的最低最小壓力(0.01 to 1.0 MPa)。同樣的,一加熱溫度係設定於100至150℃,使得該第一未固化樹脂14係流體化而具有一黏著功能。因此,如顯示於第2D圖,該電子部件20係可不損害而暫時地黏附於該第一未固化樹脂層14之上。既然如此,於此階段,該第一未固化樹脂層14仍維持於未固化狀態。
之後,如顯示於第2E圖,一未固化樹脂膜係配置來覆蓋該電子部件20,且之後在真空狀態下加熱該未固化樹脂膜的同時,該未固化樹脂膜係被推至該電子部件側。因此,形成用於覆蓋該電子部件20的一第二未固化樹脂層16。作為此步驟中加工狀況的一示例,可使用於該真空狀態下的壓力:133 Pa,溫度:120℃,推進力:1 MPa,以及加工時間:15秒。作為該第二未固化層16的材料,可使用與該第一未固化樹脂層14相同的材料。同樣的,為了防止該核心基板10的彎曲的產生,該第二未固化樹脂層16係同樣形成於該核心基板10的較低表面側。
於此時,該第二未固化樹脂層16係藉由退火(annealing)而於其流體化狀態,而形成來覆蓋該電子部件20。因此,在推進該第二未固化樹脂層16於該電子部件20之上而損害該電子部件是沒有可能性的。
此外,該第二未固化樹脂層16係形成於真空狀態下。因此,即使氣泡嵌入於暫時黏附於上的該第一未固化樹脂層14與該電子部件20之間,該等氣泡會被移除,且之後,該電子部件20會以良好的可靠度而黏附於該第一未固化樹脂層14之上。換言之,該電子部件20係埋入於該第一及第二未固化樹脂層14及16之間,而不會產生空隙。
之後,如顯示於第2F圖,當退火係以一溫度:175℃加工時間:2小時,而施用至該第一及第二未固化樹脂層14及16來進行完全固化之時,例如,一第一內層絕緣層18係分別形成於該核心基板10的兩表面側上。
於此時,暫時黏附於該核心基板10之上的該第一未固化樹脂層14係完全地黏附於該核心基板10,且亦可獲得一結構,其中該電子部件20係埋入於該第一內層絕緣層18之中。換言之,該電子部件20係被置於該電子部件埋入於以相同材料製成的該第一內層絕緣層18之中的狀態下。同樣的,該第一未固化樹脂層14係藉由硬化而作為該黏附層,以黏附該核心基板10及該電子部件20。因此,不需使用由不同於該第一內層絕緣層18的材料所造成的晶粒黏著材料。
因此,由不同材料所造成的該絕緣層係不會出現於該電子部件20的周圍。因此,在藉由使用熱循環而執行可靠度測試時,可抑制由於熱膨脹係數的不同所產生的熱應力,且因此,可克服起因於該第一內層絕緣層18的裂痕等等的此等缺陷。
之後,如第2G圖所示,形成於該核心基板10之上方表面側上的該第一內層絕緣層18係以雷射加工。因此,分別形成各具有達到該電子部件20的連接墊21a及該第一線路圖案12的深度之第一導通孔18x。除此之外,該等第一導通孔18x係可藉由使用光微影術(photolithography)或蝕刻(RIE)代替雷射而形成。此外,各具有達到該第一線路圖案12之深度的該等第一導通孔18x係形成於形成在該核心基板10的下表面側上的該第一內層絕緣層18之中。
之後,如第2H圖所示,經由該等第一導通孔18x各連接至該電子部件20及該第一線路圖案12的第二線路圖案12a係形成於該核心基板10的上表面側上。之後,經由該第一導通孔18x各連接至該第一線路圖案12的該等第二線路圖案12a係形成於該核心基板10的下表面側。
例如,該等第二線路圖案12a係藉由半加成法而形成。詳言之,首先,一籽晶層(未顯示)係藉由噴濺法或無電鍍法(electroless plating)而形成於該第一內層絕緣層18之上及該等第一導通孔18x的內表面上。之後,形成了其中備置有開口部份而相當於該等第二線路圖案12a的一阻抗層(未顯示)。之後,使用該籽晶層作為電鍍能源輸送層而進行電鍍,而形成一金屬膜圖案(未顯示)於該阻抗層該該開口部份。之後,移除該阻抗層,且之後,在使用金屬膜圖案作為一罩的同時,藉由蝕刻該籽晶層而形成該等第二線路圖案12a。既然如此,除了半加成法之外,亦可使用減成法或全加成法。
之後,如第2I圖所顯示,第三線路圖案12b係藉由如上述製程的相同製程而分別形成於該核心基板10的兩表面側上。各個該等第三線路圖案12b係經由形成於一第二內層絕緣層18a中的一第二導通孔18y而連接至該等第二線路圖案12a。
於本實施例中,此一模式係說明了三層的線路圖案12、12a、12b分別形成於該核心基板12的兩表面側上。但是此一模式可能是使用n層(n係為1或更大的整數)分別堆疊於該核心基板10的兩表面側上的線路圖案。
之後,如第2J圖所示,其中開口部份22x備置於該等第三線路圖案12b的預定部份上的一防焊層22,係分別形成該核心基板10的兩表面側上。之後,鍍鎳/金係施用於該等第三線路圖案12b之上,該等第三線路圖案12b係由該防焊層22的開口部份22x而曝露。因此,一連接部份19係分別形成於該核心基板10的兩表面側上的該等開口部份22x。
之後,一上部電子部件20x的凸塊23x係反扣連接至該核心基板10的上表面側上的該等第三線路圖案12b的該等連接部份19。因此,獲得在第一實施例中的一電子部件封裝結構1。
之後,形成於該核心基板10之下表面側上的該等第三線路圖案12b中的該等連接部份19,係作為外部連接墊。當該封裝是BGA(球格陣列)型式時,諸如錫球、金凸塊等等的外部連接終端(未顯示)係備置來連接在該核心基板10之下表面側上的該等第三線路圖案12b中的該等連接部份19,且之後,該等外部連接終端係連接至母板(電路板)。同樣的,當該封裝是LGA(柵格陣列)型式時,則省略該等外部連接終端。
如上所述,依據該第一實施例,該第一未固化樹脂層14係形成於具有該等第一線路圖案12於其上的該核心基板10之上,且之後,該電子部件20係面朝上暫時地黏附於該第一未固化樹脂層14之上。於此時,該電子部件係藉由低推進力而暫時地黏附於該第一未固化樹脂層14之上,且因此,並無損害該電子部件20的可能性。
之後,該未固化樹脂膜係配置於該電子部件20之上,且之後,在真空狀態或低壓狀態下加熱的同時,該未固化樹脂膜係被推至該電子部件20側。因此,形成了用於覆蓋該電子部件20的該第二未固化樹脂層16。於此時,由於該第二未固化樹脂層16係藉由退火使其在流體化狀態而覆蓋該電子部件20,因此可克服產生在該電子部件20內的裂痕等等的缺陷。
此外,由於可選擇相同的絕緣材料作為該第一及第二未固化樹脂層14、16,因此該電子部件20係埋入於由相同材料所造成的該第一內層絕緣層18之中。因此,在藉由使用熱循環而對該電子部件封裝結構執行可靠度測試時,可抑制由於熱膨脹係數的不同所產生的熱應力。因此,可克服產生於該第一內層絕緣層18的裂痕、產生於該電子部件20的該等連接墊21a與該等二線路圖案12a之間的不良接觸等等的缺陷,因此,可改善該電子部件封裝結構的可靠度。
換言之,在實際使用該第一實施例的該電子部件封裝結構1之時,可防止由熱應力所造成的裂痕及不良接觸的產生。
第3A圖至第3E圖係顯示依據本發明第二實施例中,製造電子部件封裝結構的方法之截面圖。該第二實施例不同於第一實施例是在於:在第一實施例中,具有凸塊的該電子部件是面朝下固定的。
於第二實施中,與第一實施例中相同步驟的詳細說明將省略之。
在第二實施例的製造電子部件封裝結構的方法中,如第3A圖所顯示,如第一實施例一般,首先備置在兩表面上具有該等第一線路圖案12的該核心基板10。於此處,在第二實施例的該核心基板10中,相當於該電子部件的凸塊之連接墊12x係備置於:備置在上側上的該等第一線路圖案12中。之後,該第一未固化樹脂層14係藉由與第一實施例相同的製程,而暫時地黏附於該核心基板10的上表面之上方。
之後,如第3B圖所示,備置具有由銅或金製成的凸塊23於其上的一電子部件20a。之後,該核心基板10係載置於該電子部件固定裝置40的該台面42之上,之後,該電子部件20a係藉由該轉換頭44而舉起,使得該電子部件20a的該等凸塊23係筆直向下(面朝下),且之後,該電子部件20a係配置於該第一未固化樹脂層14之上,使得該電子部件20a的該等凸塊23係對準於該第一線路圖案12的該等連接墊12x。之後,該電子部件20a的凸塊23係藉由朝下推進該轉換頭44而埋入於該第一未固化樹脂層14中。因此,該電子部件20a的該等凸塊23係電性連接至該等第一線路圖案12的該等連接墊12x。該電子部件20a的該等凸塊23的高度是設定為例如幾乎是20μm,且該第一未固化樹脂層14的膜厚係設定與該凸塊23的高度相當。
於此時,如第一實施例,由於該第一未固化樹脂層14係加熱至100至150℃且流體化,因此,該電子部件20a的該等凸塊23係可藉由小的堆進力而埋入於該第一未固化樹脂層14。因此,並無損害該電子部件20a的可能性。於此方法中,只有該電子部件20a的該等凸塊23可選擇性地埋入於該第一未固化樹脂層14中。
之後,如第3C圖所示,用於覆蓋該電子部件20a的該第二未固化樹脂層16係藉由與第一實施例相同的方法而形成。該第二未固化樹脂層16亦形成於該核心基板10的下面表側上。如第一實施例中所述,該第二未固化樹脂層16係藉由加熱而在其流體化狀態,形成於真空狀態下,並無在該電子部件20內產生損害的可能性。
之後,如第3D圖所示,如第一實施例,該第一及第二未固化樹脂層係藉由退火而完全固化。因此分別在該核心基板10的兩表面上,可獲得該第一內層絕緣層18。因此,可獲得埋入於該第一內層絕緣層18內的該電子部件20a的結構,亦可獲得該電子部件20a的該等凸塊23係反扣連接至該等第一線路圖案12的該等連接墊12x的結構。就像第一實施例一般,該電子部件20a係由相同材料製造的該第一內層絕緣層18所環繞並埋入於其中。因此,由不同材料所製成的絕緣層是不會出現於該電子部件20a的周圍。因此,如同第一實施例,可克服產生於該第一內層絕緣層18的裂痕、產生於該電子部件20a的該等凸塊23與該等第一線路圖案12之間的不良接觸等等的缺陷,因此,可改善該電子部件封裝結構的可靠度。
之後,如第3E圖所示,形成了類似第一實施例的增層線路(第二及第三線路圖案12a、12b),且上部電子部件20x的該等凸塊23x係連接至最上方的該等第三線路圖案12b的該等連接部份19。因此,可獲得第二實施例中的電子部件封裝結構1a。
於第二實施例中,由於該電子部件20a的該等凸塊23是反扣連接至該等線路圖案12的該等連接墊12x,因此,在電子部件20a上的該內層絕緣層18中,不需要形成導通孔。由於其他步驟與第一實施例相同,因此省略其之說明。
依據該第二實施例,可達成與第一實施例相似的優點。
第4A圖至第4K圖係顯示依據本發明第三實施例中,製造電子部件封裝結構的方法之截面圖。此一模式係由第三實施例所提供,即,該電子部件埋入於藉由以第一實施例相同方法所形成於暫存基板上的該內層絕緣層中,且之後,藉由移除該暫存基板而使該內層絕緣層係使用作為該內層基板的結構。於此第三實施例中,與第一實施例中相同步驟的詳細說明將省略之。
於第三實施例中製造電子部件封裝結構的方法中,如第4A圖所顯示,首先備置由銅(Cu)、鎳(Ni)、不銹鋼(SUS)等等所製成的一第一暫存基板50。作為該第一暫存基板50,可使用如金屬箔等等的彈性基板。但是以使用硬基板為較佳。
之後,如第4B圖所示,該第一未固化樹脂層14係藉由與第一實施例相同的方法而暫時黏附於該第一暫存基板50之上。之後,如第4C圖所示,依據與第二實施例相同的方法,該第一暫存基板50係置於該電子部件固定裝置40的該台面42之上,之後,該電子部件20a係藉由該轉換頭44而舉起,使得該電子部件20a的該等凸塊23係筆直朝下(面朝下),且之後,該電子部件20a的該等凸塊23係選擇性埋入於該第一未固化樹脂層14之中,以與該第一暫存基板50接觸。
之後,如第4D圖所示,用於覆蓋該電子部件20a的該第二未固化樹脂層16係藉由與第一實施例相同的方法所形成。之後,如第4E圖所示,形成了一結構,即,傳導柱17係備置來通過該第一及第二未固化樹脂層14及16,且一第二暫存基板50a係配置於該第二未固化樹脂層16之上。作為該第二暫存基板50a,可使用與該第一暫存基板50相同的材料。
作為形成此結構的一第一方法,備置該第二暫存基板50a,其上,由銅、金等等所製成的該等傳導柱17係筆直備置。該等傳導柱17係藉由對於作為第二暫存基板50a的金屬板,施以壓印(stamping)或蝕刻製程而形成。
之後,於該第二暫存基板50a上筆直備置的該等傳導柱17係被堆至該第一及第二未固化樹脂層14、16之內。因此,形成了通過該第一及第二未固化樹脂層14及16的該等傳導柱17,且又,該第二暫存基板50a配置於該第二未固化樹脂16之上。
同樣地,如一第二方法,各達到該第一暫存基板50的該等導通孔係藉由電射或RIE而形成於該第一及第二未固化樹脂層14及16之內,之後,藉由填入由銅或銀所製成的導電膠(導體)於該等導通孔內而形成了傳導柱17,且之後,該第二暫存基板50a係配置於該第二未固化樹脂層16之上。於此處,在使用該第二方法時,該導體(銅等等)係可藉由使用該第一暫存基板50作為電鍍能源輸送層而進行電鍍,而形成於該等導通孔內作為該等傳導柱17,以取代在該等導通孔形成之後而填入導電膠的方法。
之後,如第4F圖所示,該第一及第二未固化樹脂層14及16係藉由退火而完全固化,而因此獲得該第一內層絕緣層18。之後,如第4G圖所示,選擇性移除該第一及第二暫存基板50及50a,以離開該第一內層絕緣層18、該等傳導柱17以及該電子部件20a的該等凸塊23。此處,該第一及第二暫存基板50及50a係由銅或鎳所製成,溼式蝕刻係使用氯化鐵(III)水溶液、氯化銅(II)水溶液、或過硫酸銨(ammonium peroxodisulfate)水溶液。又,於此處,該第一及第二暫存基板50及50a係由例如不銹鋼等等的鐵系合金所製成,該第一及第二暫存基板50及50a係藉由使用化學拋光劑的拋光製程來選擇性移除的,該化學拋光劑係包含有過氧化氫及二氟化氫銨(ammonium hydrogendifluoride)作為主成份。
於此處,應選擇可以相對於該等傳導柱17及該電子部件20a的該等凸塊23來選擇性移除的材料,來作為該第一及第二暫存基板50及50a為較佳。
因此,曝露該第一內層絕緣層18的兩表面,同樣地,曝露該等傳導柱17的頂端部份及底端部份,以及該電子部件20a之該等凸塊23的頂端部份。於此第三實施例中,移除該第一及第二暫存基板50及50a,且因此,該第一內層絕緣層18係作為該核心基板。
之後,如第4H圖所示,在第4G圖的最後結構是上部翻轉向下,且之後,各連接至該電子部件20a的該等凸塊23及該傳導柱17的頂端部份之該等第一線路圖案12係形成於該第一內層絕緣層18的上表面上。之後,連接至該等傳導柱17之底端部份的該等第一線路部份12係形成於該第一內層絕緣層18的下表面上。
之後,如第4I圖所示,如第一實施例,該等第一線路圖案12a係分別形成於該第一內層絕緣層18的兩表面上的第二內層絕緣層18a之上。各個該等第二線路圖案12a係經由備置於該第二內層絕緣層18a中的該第二導通孔18y而連接至該第一線路圖案12。之後,如第4J圖所示,其中該等開口部份22x備置於該等第二線路部份12a之上的該防焊膜22,係形成於該第二內層絕緣膜18a的兩表面側上。之後,該等連接部份19係藉由施用鎳/金電鍍至該等開口部份22x中的該第二線路圖案12a處而形成。於此處,電性連接至該電子部件20a的該等凸塊23之該等線路圖案係可形成為n層(n是1或更大的整數)線路。
之後,如第4K圖所示,該上部電子部件20x的該等凸塊23x係反扣連接至該第二內層絕緣層18a之上方的該等第二線路圖案12a的該等連接部份19。
藉由上述,可完成第三實施例中的一電子部件封裝結構1b。依據該第三實施例,可達到與第一及第二實施例類似的優點,且相較第一及第二實施例,可減少該電子部件封裝結構的總厚度,此乃由於其中埋入有該電子部件20a的該第一內層絕緣層18係作為該核心基板。
第5A圖至第5J圖係顯示依據本發明第四實施例中,製造電子部件封裝結構的方法之截面圖。此一模式係由第一實施例所提供,即,不具有第三實施例中的凸塊之電子部件是面朝上封裝的。於第四實施例中,與第一至第三實施例中相同步驟的詳細說明,於此處將省略之。
於該第四實施例中製造電子部件封裝結構的方法中,如第5A圖所示,首先,如第三實施例,該第一未固化樹脂層係暫時地黏附於該第一暫存基板50之上。之後,如第5B圖所示,依據與第一實施例相同的方法,該第一暫存基板50係置於該電子部件固定裝置40的該台面42之上,之後,該電子部件20係藉由轉換頭44而舉起,使得該電子部件20的該等連接墊21A係筆直朝上(面朝上),且之後,該電子部件20係暫時地黏附於該第一未固化樹脂層14之上。
之後,如第5C圖所示,用於覆蓋該電子部件20的該第二未固化樹脂層16係藉由與第一實施例相同的方法而形成。之後,如第5D圖所示,如同第三實施例的第4E圖,形成了此一結構,即,傳導柱17係備置來通過該第一及第二未固化樹脂層14及16,且一第二暫存基板50a係配置於該第二未固化樹脂層16之上。之後,如第5E圖所示,該第一及第二未固化樹脂層14及16係藉由退火而完全固化,而因此獲得其中埋入有該電子部件20的該第一內層絕緣層18。
之後,如第5F圖所示,如同第三實施例,該第一及第二暫存基板50及50a係相對於該第一內層絕緣層18及該等傳導柱17而選擇性移除。
之後,如第5G圖所示,該等第一導通孔18x係瞃形成於該第一內層絕緣層18的部件,該部件係位於該電子部件20的該等連接墊21a之上。之後,如第5H圖所顯示,各連接至該電子部件20的該連接墊21a(經由該第一導通孔18X)以及該傳導柱17的頂端部份之該等第一線路圖案12,係形成於該第一內層絕緣層18的上表面上。同樣的,連接至該等傳導柱17的該等第一線路圖案12係形成於該第一內層絕緣層18的下表面上。
此外,經由備置於該第一內層絕緣層18a的該等第二導通孔18y,而連接至該等第一線路圖案12的該等第二線路圖案12a,係分別形成於該第一內層絕緣層18的兩表面側上。之後,如第5I圖所顯示,其中備置有在該等第二線路圖案12a的該等開口部份22x之該防焊膜22,係分別形成於該第二內層絕緣層18a的兩表面側上,且之後,藉由施用鍍鎳/金於該等開口部份22x中的該等第二線路圖案12a之上,形成該等連接部份19。
於此處,電性連接至該電子部件20的該等連接墊21a之該等線路圖案係可形成為n層(n是1或更大的整數)線路。
之後,如第5J圖所顯示,該上部電子部件20x的該等凸塊23x係反扣連接至該第一內層絕緣層18a之上方的該等第二線路圖案12a的該等連接部份19。
藉由上述,可完成第四實施例中的一電子部件封裝結構1c。
依據該第四實施例,可達到與第一及第二實施例類似的優點,且相較第一及第二實施例,且該電子部件封裝結構亦可薄如第三實施例。
1...電子部件封裝結構
1a...電子部件封裝結構
1b...電子部件封裝結構
1c...電子部件封裝結構
10...核心基板
10a...貫通孔
11...傳導柱
12...第一線路圖案
12a...第二線路圖案
12b...第三線路圖案
12x...連接墊
14...第一未固化樹脂層
16...第二未固化樹脂層
17...傳導柱
18...第一內層絕緣層
18a...第二內層絕緣層
18x...第一導通孔
18y...第二導通孔
19...連接部份
20...電子部件
20a...電子部件
20x...上部電子部件
21a...連接墊
21b...鈍化膜
22...防焊層
22x...開口部份
23x...凸塊
40...電子部件固定裝置
42...台面
44...轉換頭
50...第一暫存基板
50a...第二暫存基板
100...下部銅箔
102...未充填樹脂
104...傳導柱
106...內層絕緣層
106a...未固化樹脂膜
108...線路圖案
110...上部銅箔
200...電子部件
202...第一凸塊
第1A圖至第1C圖係為顯示在習知技術中,製造電子部件封裝結構之方法的截面圖;第2A圖至第2J圖係顯示依據本發明第一實施例中,製造電子部件封裝結構的方法之截面圖;第3A圖至第3E圖係顯示依據本發明第二實施例中,製造電子部件封裝結構的方法之截面圖;第4A圖至第4K圖係顯示依據本發明第三實施例中,製造電子部件封裝結構的方法之截面圖;以及第5A圖至第5J圖係顯示依據本發明第四實施例中,製造電子部件封裝結構的方法之截面圖。
1...電子部件封裝結構
10...核心基板
10a...貫通孔
11...傳導柱
12...第一線路圖案
12a...第二線路圖案
12b...第三線路圖案
18...第一內層絕緣層
18a...第二內層絕緣層
18x...第一導通孔
18y...第二導通孔
19...連接部份
20...電子部件
20x...上部電子部件
21a...連接墊
21b...鈍化膜
22...防焊層
22x...開口部份
23x...凸塊
Claims (10)
- 一種製造電子部件封裝結構的方法,其特徵在於包含下列步驟:在設有線路圖案之基板的全面上,形成第一未固化樹脂層;將設有連接墊之電子部件以該連接墊朝向上側之方式配置於該第一未固化樹脂層上;形成覆蓋該電子部件之第二未固化樹脂層,該第二未固化樹脂層係由與該第一未固化樹脂層相同之材料所構成;藉由熱處理使該第一未固化樹脂層與該第二未固化樹脂層同時硬化,而獲得已埋設有該電子部件之絕緣層;於前述獲得絕緣層之步驟後,於該絕緣層上形成導通孔,該導通孔係到達該電子部件之該連接墊及該基板上之該線路圖案;以及形成n層(n為1以上之整數)線路圖案,該等n層線路圖案透過已設於該絕緣層之導通孔而電性連接至該電子部件之該連接墊及該基板上之線路圖案。
- 一種製造電子部件封裝結構的方法,其特徵在於包含下列步驟:在設有線路圖案之基板的全面上,形成第一未固化樹脂層;使設有凸塊之電子部件的該凸塊埋入該第一未固 化樹脂層中,並使該電子部件之凸塊電性連接至該基板之該線路圖案;形成覆蓋該電子部件之第二未固化樹脂層,該第二未固化樹脂層係由與該第一未固化樹脂層相同之材料所構成;藉由熱處理使該第一未固化樹脂層與該第二未固化樹脂層同時硬化,而獲得已埋設有該電子部件之絕緣層;於前述獲得絕緣層之步驟後,於該絕緣層上形成導通孔,該導通孔係到達該基板上之該線路圖案;以及形成n層(n為1以上之整數)線路圖案,且該等n層線路圖案透過已設於該絕緣層之導通孔而電性連接至該電子部件之該連接墊及該基板上之線路圖案。
- 一種製造電子部件封裝結構的方法,其特徵在於包含下列步驟:於第一暫存基板上形成第一未固化樹脂層;將電子部件配置於該第一未固化樹脂層;形成覆蓋該電子部件之第二未固化樹脂層,該第二未固化樹脂層係由與該第一未固化樹脂層相同之材料所構成;使已直立設有導電柱之第二暫存基板的該導電柱插入前述第一及第二未固化樹脂層,藉此形成:設有貫通前述第一及第二未固化樹脂層之導電柱,且第二暫存基板配置在該第二未固化樹脂層的結構; 藉由熱處理使該第一未固化樹脂層與該第二未固化樹脂層同時硬化,而獲得已埋設有該電子部件之絕緣層;去除前述第一及第二暫存基板。
- 如申請專利範圍第1或2項之製造電子部件封裝結構的方法,其中該基板所設有之線路圖案係在透過貫通該基板而設置之導電柱而彼此連接的狀態下形成於該基板的兩面上,且前述n層線路圖案係形成於該基板的兩面側上。
- 如申請專利範圍第1或2項之製造電子部件封裝結構的方法,其更具有下列步驟:在前述n層線路圖案之最上方的線路圖案上,將上側電子部件進行倒裝晶片連接。
- 如申請專利範圍第1項之製造電子部件封裝結構的方法,其中前述配置電子部件之步驟係在已加熱該第一未固化樹脂層之狀態下,以0.01至1.0 MPa的壓力推壓該電子部件,藉此使該電子部件暫時黏附於該第一未固化樹脂層上者。
- 如申請專利範圍第1或2項之製造電子部件封裝結構的方法,其中前述形成該第二未固化樹脂層之步驟包含:使未固化之樹脂膜在業經真空環境下加熱而流動化的狀態下,朝該電子部件側推壓。
- 如申請專利範圍第1至3項中任一項之製造電子部件封裝結構的方法,其中該第一未固化樹脂層及該第二未固 化樹脂層係環氧樹脂、聚醯亞胺樹脂及聚苯醚樹脂中之任一者。
- 如申請專利範圍第1至3項中任一項之製造電子部件封裝結構的方法,其中該電子部件為半導體晶片或被動元件。
- 如申請專利範圍第3項之製造電子部件封裝結構的方法,其中該第一暫存基板及該第二暫存基板係由銅、鎳或不銹鋼所構成。
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TW094112389A TWI384630B (zh) | 2004-05-10 | 2005-04-19 | 製造電子部件封裝結構之方法 |
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US (1) | US7319049B2 (zh) |
JP (1) | JP4541753B2 (zh) |
KR (2) | KR101109702B1 (zh) |
TW (1) | TWI384630B (zh) |
Families Citing this family (46)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7410894B2 (en) * | 2005-07-27 | 2008-08-12 | International Business Machines Corporation | Post last wiring level inductor using patterned plate process |
JP2007103772A (ja) * | 2005-10-06 | 2007-04-19 | Texas Instr Japan Ltd | 半導体装置の製造方法 |
JP4841234B2 (ja) * | 2005-11-24 | 2011-12-21 | 日本特殊陶業株式会社 | ビアアレイキャパシタ内蔵配線基板の製造方法 |
EP1962342A4 (en) | 2005-12-14 | 2010-09-01 | Shinko Electric Ind Co | SUBSTRATE WITH INTEGRATED CHIP AND METHOD FOR MANUFACTURING THE SAME |
FI20060256L (fi) | 2006-03-17 | 2006-03-20 | Imbera Electronics Oy | Piirilevyn valmistaminen ja komponentin sisältävä piirilevy |
JP2007311492A (ja) * | 2006-05-17 | 2007-11-29 | Shinko Electric Ind Co Ltd | 半導体装置の製造方法 |
DE102006025553B4 (de) * | 2006-06-01 | 2020-01-16 | Hahn-Schickard-Gesellschaft für angewandte Forschung e.V. | Verfahren zum Herstellen einer elektronischen Baueinheit |
JP2008016630A (ja) * | 2006-07-06 | 2008-01-24 | Matsushita Electric Ind Co Ltd | プリント配線板およびその製造方法 |
CN100514616C (zh) * | 2006-08-29 | 2009-07-15 | 欣兴电子股份有限公司 | 内埋式芯片封装制程及具有内埋芯片的电路基板 |
JP4274290B2 (ja) * | 2006-11-28 | 2009-06-03 | 国立大学法人九州工業大学 | 両面電極構造の半導体装置の製造方法 |
CN100593963C (zh) * | 2007-07-17 | 2010-03-10 | 欣兴电子股份有限公司 | 内埋式线路结构及其工艺 |
TWI396269B (zh) * | 2007-10-17 | 2013-05-11 | Unimicron Technology Corp | 電路板之製法 |
JP5271627B2 (ja) * | 2008-07-30 | 2013-08-21 | 株式会社フジクラ | 多層プリント配線板 |
TWI366906B (en) * | 2009-03-31 | 2012-06-21 | Ind Tech Res Inst | Die stacking structure and fabricating method thereof |
US8390083B2 (en) * | 2009-09-04 | 2013-03-05 | Analog Devices, Inc. | System with recessed sensing or processing elements |
JP5325736B2 (ja) * | 2009-10-06 | 2013-10-23 | 新光電気工業株式会社 | 半導体装置及びその製造方法 |
US8786062B2 (en) | 2009-10-14 | 2014-07-22 | Advanced Semiconductor Engineering, Inc. | Semiconductor package and process for fabricating same |
US20110084372A1 (en) * | 2009-10-14 | 2011-04-14 | Advanced Semiconductor Engineering, Inc. | Package carrier, semiconductor package, and process for fabricating same |
US8569894B2 (en) | 2010-01-13 | 2013-10-29 | Advanced Semiconductor Engineering, Inc. | Semiconductor package with single sided substrate design and manufacturing methods thereof |
TWI411075B (zh) | 2010-03-22 | 2013-10-01 | Advanced Semiconductor Eng | 半導體封裝件及其製造方法 |
US9407997B2 (en) | 2010-10-12 | 2016-08-02 | Invensense, Inc. | Microphone package with embedded ASIC |
US8941222B2 (en) | 2010-11-11 | 2015-01-27 | Advanced Semiconductor Engineering Inc. | Wafer level semiconductor package and manufacturing methods thereof |
US9406658B2 (en) | 2010-12-17 | 2016-08-02 | Advanced Semiconductor Engineering, Inc. | Embedded component device and manufacturing methods thereof |
US8619431B2 (en) * | 2010-12-22 | 2013-12-31 | ADL Engineering Inc. | Three-dimensional system-in-package package-on-package structure |
JP5309352B2 (ja) * | 2011-02-15 | 2013-10-09 | Tdk株式会社 | 電子部品内蔵モジュール用層間絶縁シート、電子部品内蔵モジュール及び電子部品内蔵モジュールの製造方法 |
JP5413382B2 (ja) * | 2011-02-15 | 2014-02-12 | Tdk株式会社 | 電子部品内蔵モジュールの製造方法 |
US9142502B2 (en) * | 2011-08-31 | 2015-09-22 | Zhiwei Gong | Semiconductor device packaging having pre-encapsulation through via formation using drop-in signal conduits |
US8916421B2 (en) * | 2011-08-31 | 2014-12-23 | Freescale Semiconductor, Inc. | Semiconductor device packaging having pre-encapsulation through via formation using lead frames with attached signal conduits |
US8780576B2 (en) * | 2011-09-14 | 2014-07-15 | Invensas Corporation | Low CTE interposer |
CN103052268B (zh) * | 2011-10-11 | 2016-03-02 | 欣兴电子股份有限公司 | 线路结构的制作方法 |
US8597983B2 (en) | 2011-11-18 | 2013-12-03 | Freescale Semiconductor, Inc. | Semiconductor device packaging having substrate with pre-encapsulation through via formation |
KR101332916B1 (ko) * | 2011-12-29 | 2013-11-26 | 주식회사 네패스 | 반도체 패키지 및 그 제조 방법 |
US9190389B2 (en) | 2013-07-26 | 2015-11-17 | Infineon Technologies Ag | Chip package with passives |
US9070568B2 (en) * | 2013-07-26 | 2015-06-30 | Infineon Technologies Ag | Chip package with embedded passive component |
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US10177115B2 (en) * | 2014-09-05 | 2019-01-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Package structures and methods of forming |
CN105590914B (zh) * | 2014-10-24 | 2018-04-06 | 碁鼎科技秦皇岛有限公司 | 电子元件封装结构及制作方法 |
TWI566349B (zh) * | 2014-12-04 | 2017-01-11 | 矽品精密工業股份有限公司 | 封裝結構及其製法 |
US9666558B2 (en) | 2015-06-29 | 2017-05-30 | Point Engineering Co., Ltd. | Substrate for mounting a chip and chip package using the substrate |
CN106356355B (zh) * | 2015-07-15 | 2020-06-26 | 恒劲科技股份有限公司 | 基板结构及其制作方法 |
US10068853B2 (en) * | 2016-05-05 | 2018-09-04 | Taiwan Semiconductor Manufacturing Co., Ltd. | Integrated fan-out package and method of fabricating the same |
JP6904055B2 (ja) * | 2017-05-19 | 2021-07-14 | Tdk株式会社 | 半導体ic内蔵基板及びその製造方法 |
US10903136B2 (en) * | 2017-11-07 | 2021-01-26 | Tdk Taiwan Corp. | Package structure having a plurality of insulating layers |
JPWO2021009865A1 (ja) * | 2019-07-17 | 2021-09-13 | 株式会社メイコー | 高密度多層基板、及びその製造方法 |
CN113140538A (zh) * | 2021-04-21 | 2021-07-20 | 上海闻泰信息技术有限公司 | 转接板、封装结构及转接板的制作方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20020175402A1 (en) * | 2001-05-23 | 2002-11-28 | Mccormack Mark Thomas | Structure and method of embedding components in multi-layer substrates |
US6590291B2 (en) * | 2000-01-31 | 2003-07-08 | Shinko Electric Industries Co., Ltd. | Semiconductor device and manufacturing method therefor |
US6734542B2 (en) * | 2000-12-27 | 2004-05-11 | Matsushita Electric Industrial Co., Ltd. | Component built-in module and method for producing the same |
US6784530B2 (en) * | 2002-01-23 | 2004-08-31 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module with embedded semiconductor chip and method of manufacturing |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH1070363A (ja) * | 1996-08-27 | 1998-03-10 | Toshiba Corp | 印刷配線板の製造方法 |
JPH1079578A (ja) * | 1996-09-04 | 1998-03-24 | Oki Electric Ind Co Ltd | 配線基板の製造方法 |
JP2000151057A (ja) * | 1998-11-09 | 2000-05-30 | Hitachi Ltd | 電子部品実装構造体およびその製造方法並びに無線icカードおよびその製造方法 |
JP2001156457A (ja) * | 1999-11-30 | 2001-06-08 | Taiyo Yuden Co Ltd | 電子回路装置の製造方法 |
JP3598060B2 (ja) * | 1999-12-20 | 2004-12-08 | 松下電器産業株式会社 | 回路部品内蔵モジュール及びその製造方法並びに無線装置 |
JP3547423B2 (ja) | 2000-12-27 | 2004-07-28 | 松下電器産業株式会社 | 部品内蔵モジュール及びその製造方法 |
JP2002271020A (ja) * | 2001-03-08 | 2002-09-20 | Toshiba Chem Corp | プリント配線板、ビルドアップ配線板およびその製造方法 |
JP2003046258A (ja) * | 2001-07-27 | 2003-02-14 | Kyocera Corp | 配線基板用絶縁シート及びそれを用いた多層配線基板及びその製造方法 |
JP3572305B2 (ja) * | 2001-09-27 | 2004-09-29 | 松下電器産業株式会社 | 絶縁シートおよび多層配線基板ならびにその製造方法 |
JP2003243563A (ja) * | 2001-12-13 | 2003-08-29 | Matsushita Electric Ind Co Ltd | 金属配線基板と半導体装置及びその製造方法 |
US6841413B2 (en) * | 2002-01-07 | 2005-01-11 | Intel Corporation | Thinned die integrated circuit package |
JP4627957B2 (ja) * | 2002-05-29 | 2011-02-09 | 日立化成工業株式会社 | 半導体装置の製造方法及び積層型半導体装置 |
JP2004079701A (ja) * | 2002-08-14 | 2004-03-11 | Sony Corp | 半導体装置及びその製造方法 |
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Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6590291B2 (en) * | 2000-01-31 | 2003-07-08 | Shinko Electric Industries Co., Ltd. | Semiconductor device and manufacturing method therefor |
US6734542B2 (en) * | 2000-12-27 | 2004-05-11 | Matsushita Electric Industrial Co., Ltd. | Component built-in module and method for producing the same |
US20020175402A1 (en) * | 2001-05-23 | 2002-11-28 | Mccormack Mark Thomas | Structure and method of embedding components in multi-layer substrates |
US6784530B2 (en) * | 2002-01-23 | 2004-08-31 | Matsushita Electric Industrial Co., Ltd. | Circuit component built-in module with embedded semiconductor chip and method of manufacturing |
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Publication number | Publication date |
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JP4541753B2 (ja) | 2010-09-08 |
JP2005322769A (ja) | 2005-11-17 |
TW200539464A (en) | 2005-12-01 |
KR20060045610A (ko) | 2006-05-17 |
US7319049B2 (en) | 2008-01-15 |
KR101156657B1 (ko) | 2012-06-15 |
US20050247665A1 (en) | 2005-11-10 |
KR101109702B1 (ko) | 2012-01-31 |
KR20110081795A (ko) | 2011-07-14 |
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