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KR960006004A - 반도체 소자 및 그 제조방법 - Google Patents

반도체 소자 및 그 제조방법 Download PDF

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KR960006004A
KR960006004A KR1019940017957A KR19940017957A KR960006004A KR 960006004 A KR960006004 A KR 960006004A KR 1019940017957 A KR1019940017957 A KR 1019940017957A KR 19940017957 A KR19940017957 A KR 19940017957A KR 960006004 A KR960006004 A KR 960006004A
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semiconductor device
dielectric film
manufacturing
concentration impurity
gate electrode
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KR1019940017957A
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조병진
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김주용
현대전자산업 주식회사
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Priority to KR1019940017957A priority Critical patent/KR960006004A/ko
Priority to JP7186755A priority patent/JP2774952B2/ja
Priority to GB9515147A priority patent/GB2291741B/en
Priority to DE19527131A priority patent/DE19527131B4/de
Priority to CN95115080A priority patent/CN1041471C/zh
Priority to US08/507,668 priority patent/US5559049A/en
Publication of KR960006004A publication Critical patent/KR960006004A/ko

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/023—Manufacture or treatment of FETs having insulated gates [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0223—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate
    • H10D30/0227—Manufacture or treatment of FETs having insulated gates [IGFET] having source and drain regions or source and drain extensions self-aligned to sides of the gate having both lightly-doped source and drain extensions and source and drain regions self-aligned to the sides of the gate, e.g. lightly-doped drain [LDD] MOSFET or double-diffused drain [DDD] MOSFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28114—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor characterised by the sectional shape, e.g. T, inverted-T
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32134—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/601—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs 
    • H10D30/605—Insulated-gate field-effect transistors [IGFET] having lightly-doped drain or source extensions, e.g. LDD IGFETs or DDD IGFETs  having significant overlap between the lightly-doped extensions and the gate electrode
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/611—Insulated-gate field-effect transistors [IGFET] having multiple independently-addressable gate electrodes influencing the same channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions 
    • H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
    • H10D64/311—Gate electrodes for field-effect devices
    • H10D64/411—Gate electrodes for field-effect devices for FETs
    • H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
    • H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
    • H10D64/518—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their lengths or sectional shapes

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 소자 및 그 제조방법에 관한 것으로, 게이트 전극을 T형으로 형성하고, T형 게이트 전극의 오목한 부분에 전기적으로 플로팅(Floating)된 폴리실리콘층을 형성하여 T형 게이트와 용량적으로 커플링(Capacitive Coupling)이 되어있는 보조 게이트를 형성하므로써, 고집적 회로소자에서 요구되는 짧은 채널길이를 형성시킬 수 있고, LDD구조의 저농도 불순물 영역(Light doped region)의 채널 저항을 줄여 소자의 동작 속도를 크게 향상시킬 수 있도록 한 반도체 소자 및 그 제조 방법에 관한 것이다.

Description

반도체 소자 및 그 제조방법
본 내용은 요부공개 건이므로 전문내용을 수록하지 않았음
제1도는 본 발명의 반도체 소자 단면도이다.
제2A도 내지 제2F도는 본 발명의 제1실시예를 설명하기 위한 소자의 단면도이다.
제3A도 내지 제3E도는 본 발명의 제2실시예를 설명하기 위한 소자의 단면도이다.

Claims (14)

  1. 게이트 전극과 LDD구조의 소오스/드레인 영역을 갖는 반도체 소자에 있어서, 저농도 불순물 영역(50)의 저항을 전기적으로 콘트롤하기 위하여, 저농도 불순물 영역(50)과 전기적으로 플로팅되도록 보조 게이트(40)가 형성되는 것을 특징으로 하는 반도체 소자.
  2. 제1항에 있어서, 상기 보조 게이트(40)는 T형 게이트 전극(20)의 오목한 부분에 형성되는 것을 특징으로 하는 반도체 소자.
  3. 제1항에 있어서, 상기 저농도 불순물 영역(50)과 보조 게이트(40)사이에 유전체막(30)이 형성되는 것을 특징으로 하는 반도체 소자.
  4. 제3항에 있어서, 상기 유전체막(30)은 PSG, BSG, BPSG,MTO 또는 ONO인 것을 특징으로 하는 반도체 소자.
  5. 반도체 소자의 제조방법에 있어서, 실리콘 기판(1)상에 게이트 산화막(10) 및 T형 게이트 전극(20)을 형성하는 단계와, 상기 단계로부터 전체구조 상부에 소정의 불순물이 함유된 유전체막(30) 및 폴리실리콘층(40A)을 순차적으로 형성한 후 블랭켓 식각공정을 실시하여 상기 T형 게이트 전극(20)의 오목한 부분에 유전체막(30) 및 보조 게이트(40)를 형성하는 단계와, 상기 단계로부터 고농도 불순물 주입공정으로 고농도 불순물 영역(60)을 형성하는 단계와, 상기 단계로부터 전체 구조상에 층간 절연막(30)을 증착한 후 표면 평탄화를 위해 열처리 공정을 실시하는 단계와, 상기 단체로부터 열처리공정에 의해 상기 불순물이 함유된 유전체막(30)으로부터 불순물이 실리콘 기판(1)쪽으로 확산되어 저농도 불순물 영역(50)을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.
  6. 제5항에 있어서, 상기 T형 게이트 전극(20)은 불순물이 도핑된 실리콘과 불순물이 도핑되지 않은 실리콘을 600℃이하의 온도하에서 비정질 상태로 연속증착하고, 리소그라피 공정을 통하여 게이트를 한정한 후 열처리공정을 실시하고, 이후 폴리습식식각용액으로 선택식각하여 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.
  7. 제6항에 있어서, 상기 열처리공정은 600~750℃ 의 온도범위에서 0.5~5시간 실시하여 상기 도프 실리콘층의 불순물을 활성화시키면서 상기 언도프 실리콘층으로 불순물이 확산되지 않는 상태로 다결정화하는 것을 특징으로 하는 반도체 소자의 제조방법.
  8. 제6항에 있어서, 상기 폴리식식각용액은 NHO3: CH3COOH : HF : H2O = 21 : 3 : 0.25 ~ 1.0 : 1.5~ 16의 조성비로 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.
  9. 제5항에 있어서, 상기 유전체막(30)은 NMOS일 경우 PSG를 사용하고, PMOS일 경우 PSG 또는 BPSG를 사용하여 100~200Å 정도의 얇은 두께로 형성하는 것을 특징으로 하는 반도체 소자의 제조방법.
  10. 제5항에 있어서, 상기 보조 게이트 (40)를 형성하기 위한 폴리실리콘층(40A)는 NMOS일 경우 n+폴리실리콘을 사용하고, PMOS일 경우 p+폴리실리콘을 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.
  11. 제5항에 있어서, 상기 저농도 불순물 영역(50)은 NMOS일 경우 PSG로 된 유전체막(30)으로 부터 n형 불순물인 인(P)이 실리콘 기판(1)쪽으로 확산되어 형성되며, PMOS일 경우 BSG 또는 BPSG로 된 유전체막(30)으로 부터 p형 불순물인 붕소(B)가 실리콘 기판(1)쪽으로 확산되어 형성되는 것을 특징으로 하는 반도체 소자의 제조방법.
  12. 반도체 소자의 제조방법에 있어서, 실리콘 기판(1)상에 게이트 산화막(10)및 T형 게이트 전극(20)을 형성하는 단계와, 상기 단계로부터 전체구조 상부에 도프 글래스(70)를 두껍게 증착하는 단계와, 상기 단계로부터 도프 글래스(70)를 고온 열처리하여 도프 글래스(70)로부터 소정의 불순물이 실리콘 기판(1)쪽으로 확산되어 저농도 불순물 영역(50)을 형성하는 단계와, 상기 단계로부터 도프 글래스(70)를 제거한 후 전체구조상에 유전체막(30) 및 폴리실리콘층(40A)을 순차적으로 형성하고, 블랭켓 식각공정을 실시하여 상기 T형 게이트 전극(20)의 오목한 부분에 유전체막(30) 및 보조 게이트(40)를 형성하는 단계와, 상기 단계로부터 고농도 불순물 주입공정으로 고농도 불순물 영역(60)을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 소자의 제조방법.
  13. 제12항에 있어서, 상기 도프 글래스(70)는 NMOS일 경우 PSG를 사용하고, PMOS일 경우 PSG 또는 BPSG를 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.
  14. 제12항에 있어서, 상기 유전체막(30)은 MTO 또는 ONO 구조를 사용하는 것을 특징으로 하는 반도체 소자의 제조방법.
    ※ 참고사항 : 최초출원 내용에 의하여 공개하는 것임.
KR1019940017957A 1994-07-25 1994-07-25 반도체 소자 및 그 제조방법 KR960006004A (ko)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019940017957A KR960006004A (ko) 1994-07-25 1994-07-25 반도체 소자 및 그 제조방법
JP7186755A JP2774952B2 (ja) 1994-07-25 1995-07-24 半導体素子の製造方法
GB9515147A GB2291741B (en) 1994-07-25 1995-07-24 Lightly doped drain field effect transistors
DE19527131A DE19527131B4 (de) 1994-07-25 1995-07-25 Halbleitervorrichtung mit einer T-förmigen Gatestruktur und Verfahren zu deren Herstellung
CN95115080A CN1041471C (zh) 1994-07-25 1995-07-25 半导体器件及其制造方法
US08/507,668 US5559049A (en) 1994-07-25 1995-07-25 Method of manufacturing a semiconductor device

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Application Number Priority Date Filing Date Title
KR1019940017957A KR960006004A (ko) 1994-07-25 1994-07-25 반도체 소자 및 그 제조방법

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KR960006004A true KR960006004A (ko) 1996-02-23

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US (1) US5559049A (ko)
JP (1) JP2774952B2 (ko)
KR (1) KR960006004A (ko)
CN (1) CN1041471C (ko)
DE (1) DE19527131B4 (ko)
GB (1) GB2291741B (ko)

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US5710054A (en) * 1996-08-26 1998-01-20 Advanced Micro Devices, Inc. Method of forming a shallow junction by diffusion from a silicon-based spacer
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US5756384A (en) * 1997-05-20 1998-05-26 Vanguard International Semiconductor Corporation Method of fabricating an EPROM cell with a high coupling ratio
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US5559049A (en) 1996-09-24

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