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JPS6376444A - チツプキヤリア - Google Patents

チツプキヤリア

Info

Publication number
JPS6376444A
JPS6376444A JP61219414A JP21941486A JPS6376444A JP S6376444 A JPS6376444 A JP S6376444A JP 61219414 A JP61219414 A JP 61219414A JP 21941486 A JP21941486 A JP 21941486A JP S6376444 A JPS6376444 A JP S6376444A
Authority
JP
Japan
Prior art keywords
chip
lsi chip
ceramic substrate
lsi
chip carrier
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61219414A
Other languages
English (en)
Inventor
Mutsuo Tsuji
睦夫 辻
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61219414A priority Critical patent/JPS6376444A/ja
Priority to EP87308232A priority patent/EP0260969A1/en
Priority to US07/098,218 priority patent/US4855869A/en
Publication of JPS6376444A publication Critical patent/JPS6376444A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/02—Containers; Seals
    • H01L23/04—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls
    • H01L23/053—Containers; Seals characterised by the shape of the container or parts, e.g. caps, walls the container being a hollow construction and having an insulating or insulated base as a mounting for the semiconductor body
    • H—ELECTRICITY
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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
    • H—ELECTRICITY
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    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H—ELECTRICITY
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
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    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73253—Bump and layer connectors
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8312—Aligning
    • H01L2224/83136—Aligning involving guiding structures, e.g. spacers or supporting members
    • H—ELECTRICITY
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319—Arrangement of the layer connectors prior to mounting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/838—Bonding techniques
    • H01L2224/8385—Bonding techniques using a polymer adhesive, e.g. an adhesive based on silicone, epoxy, polyimide, polyester
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    • H01L2924/01033—Arsenic [As]
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    • H01L2924/01074—Tungsten [W]
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    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
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    • H01L2924/078—Adhesive characteristics other than chemical
    • H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
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    • H01L2924/11—Device type
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    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate
    • H01L2924/15172—Fan-out arrangement of the internal vias
    • H01L2924/15173—Fan-out arrangement of the internal vias in a single layer of the multilayer substrate
    • H—ELECTRICITY
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    • H01L2924/1517—Multilayer substrate
    • H01L2924/15182—Fan-in arrangement of the internal vias
    • H01L2924/15184—Fan-in arrangement of the internal vias in different layers of the multilayer substrate
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    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/156—Material
    • H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
    • H01L2924/15787—Ceramics, e.g. crystalline carbides, nitrides or oxides

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Die Bonding (AREA)
  • Wire Bonding (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は電子装置等に使用される配線基板１ｃＬＳ！チ
ツプを実装したチップキャリアに関するものである。
〔従来の技術〕
従来この種のチップキャリアは、第２図に示すように、
セラミック基板２１上の金属層２２にＬＳＩテップ２３
を固着し、ワイヤー２４でＬＳＩテップ２３と基板２１
上のパッド２５とを電気的に接続した後、キャップ２６
で封止して構成されている（例えば特開昭５７−１２６
１５１公報）。
〔発明が解決しようとする問題点〕
上述した従来のチップキャリアでは、ＬＳＩ　テップ１
がフェイスアップ実装のために上部にヒートシンク等の
放熱部品を配設しても放熱効果が少なく、マた、下部に
はチップキャリアを搭載する基板が配設されるので、放
熱部品が取付けられず、消費電力の多いＬＳＩチップの
実装には適さないという欠点があった。
本発明は、前述した従来の問題に鑑みてなされたもので
あシ、その目的はＬＳＩチップの放熱性を向上させるこ
とができるチップキャリアラ提供することにある。
〔問題点を解決するための手段〕
本発明のチップキャリアは、ＬＳＩチップと、内面に前
記ＬＳＩ　チップのリードと接続されるす−ド用パッド
および外面に前記リード用パッドと接層される入出力用
パッドを形成したセラミック基板と、前記ＬＳＩ　チッ
プをセラミック基板にフェイスダウンで実装するスペー
サーと、前記ＬＳＩチップに接着配置した熱伝導性プレ
ートと、前記プレートと前記セラミック基板との間を封
止する金属枠体とを有している。
〔作用〕
本発明におけるチップキャリアは、ＬＳＩ　チップが熱
伝導性プレート、と接層配置されるので、ＬＳＩチップ
の放熱れ路が形成される。
〔実施例〕
次に本発明について図面を参照して説明する。
第１図は本発明によるチップ中ヤリアの一実施例を示す
縦断面図である。同図において、セラミック基板１の内
面には、リード用パッド２が、外面には入出力用パッド
３が、内部にはリード用パッド２と入出力用パッド３と
を接続する導体配線層４がそれぞれ設けられている。ま
た、このセラミック基板１の内面側周辺部にはシーム溶
接に適した例えば、コバールなどからなる第１の金属枠
５が例えば銀ろうなどの接着剤６によシ固漕されている
。また、このセラミック基板１の中央部には例えばシリ
コーンゴムなどからなるスペーサ７が例えばシリコン系
の接層剤８によシ接層配置されている。さらにこのスペ
ーサＴ上にはＬＳＩチップ９がフェイスダウンで前記同
様の接着剤８によシｌｉ！！漕され、ＬＳＩテップ９の
リード１０がセラミック基板１上のリード用パッド２に
接続されている。また、このＬＳＩテップ９上には、熱
伝導性の良好な例えばＣｕ、／Ｍ／　、　Ｂ　＠　０材
等からなるプレート１１と、その周辺部に例えば銀ろう
などの接層剤１２により接層された第２の金属枠１３と
からなるキャップ１４が、熱伝導性の良好な例えば、銀
粉式ジェポキシ系の接着剤１５により接着配置され、キ
ャップ１４の第２の金属枠１３はセラミック基板１上の
第１の金属枠５上にシーム溶接されて固着され、封止さ
れる。この場合、この第１の金属枠５の高さはスペーサ
７およプレート１０の高さを考慮に入れて可能な限り低
く設定される。
このよりなＷ成によれば、ＬＳＩ　　テップ９の上面に
は熱伝導性の高いキャップ１４のプレート１１が熱伝導
性の良好な接着剤１５を介して接着配置されているので
、このプレート１１上にヒートシンクなどの放熱部品が
容易に取シ付けることができるとともに、ＬＳＩチップ
９で発生した熱がプレート１１に良好に伝導されて放熱
される。
〔発明の効果〕
以上説明したように本発明は、フェイスダウン実装され
たＬＳＩチップと、熱伝導率の良いプレートとが接層さ
れることによｆｉ、ＬＳＩチップの発生する熱が効率良
くプレート上に取付けられるヒートシンク等の放熱部品
に伝導することができるのて、放熱性を向上させること
ができる。また、セラミック基板に接層された金属枠の
高さを低くしたことによシ、セラミック基板の幅を小さ
くすることができるのでチップキャリア全体の大きさも
小さくすることができる。さらにセラミック基板とプレ
ートとの間に金属枠体を介在させたことｋよシ金属枠を
シーム溶接によ）封止を行なうことができるので、封止
時ＫＬＳＩチップに与える熱が少なく、ＬＳＩチップの
信頼性が向上できるなどの極めて優れた効果が得られる
。
【図面の簡単な説明】
第１図は本発明のチップキャリアの縦断面図、第２図は
従来のチップキャリアの縦断面図である。 １・・壷・セラミック基板、２・・・・リード用パッド
、３・嚇・・入出力用パッド、４・・・・導体配線層、
５・・・・第１の金属枠、６・・・・接５ｆ剤、７・・
・・スペ−１−１８・・・・接着剤、９・・争・ＬＳＩ
テップ、１ｏ−・・・！Ｊ−）”、１１　・・働・プレ
ート、１２・・・・接層剤、１３・・・・第１の金属枠
、１４・・・・キャップ、１５Φ・＠Φ接溜剤。

Claims (1)

    【特許請求の範囲】
  1. 　ＬＳＩチップと、内面に前記ＬＳＩチップのリードと
    接続されるリード用パッドおよび外面に前記リード用パ
    ッドと接続される入出力用パッドを形成したセラミック
    基板と、前記セラミック基板にＬＳＩチップをフエース
    ダウン実装するスペーサと、前記ＬＳＩチップに接着配
    置させる熱伝導性プレートと、前記プレートと前記セラ
    ミック基板との周辺部を封止する金属枠体とを備えたこ
    とを特徴とするチップキャリア。
JP61219414A 1986-09-19 1986-09-19 チツプキヤリア Pending JPS6376444A (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP61219414A JPS6376444A (ja) 1986-09-19 1986-09-19 チツプキヤリア
EP87308232A EP0260969A1 (en) 1986-09-19 1987-09-17 Chip carrier
US07/098,218 US4855869A (en) 1986-09-19 1987-09-18 Chip carrier

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61219414A JPS6376444A (ja) 1986-09-19 1986-09-19 チツプキヤリア

Publications (1)

Publication Number Publication Date
JPS6376444A true JPS6376444A (ja) 1988-04-06

Family

ID=16735021

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61219414A Pending JPS6376444A (ja) 1986-09-19 1986-09-19 チツプキヤリア

Country Status (3)

Country Link
US (1) US4855869A (ja)
EP (1) EP0260969A1 (ja)
JP (1) JPS6376444A (ja)

Cited By (1)

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Publication number Priority date Publication date Assignee Title
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Publication number Publication date
EP0260969A1 (en) 1988-03-23
US4855869A (en) 1989-08-08

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