JPS6346758A - Mos capacitor and manufacture thereof - Google Patents

Abstract

PURPOSE:To obtain an MOS capacitor having a small size and a large capacity to take an electrostatic capacity in a large range by providing a semiconductor substrate having many grooves on its surface, a dielectric oxide film formed on the substrate and electrodes formed on the film. CONSTITUTION:The surface area of a semiconductor substrate 11 made of a silicon substrate is set, for example, to desired value by many grooves 11a formed in a stripe or lattice shape by etching. A dielectric oxide film 13 formed of a silicon oxide film (SiO2, epsilonapprox.=3.0-3.5) formed in a desired thickness by thermally oxidizing the substrate. Further, electrodes 14 formed by patterning are provided to become a desired size. Since the surface area of the substrate can be increased to be controlled by the etching degree of the grooves, the electrostatic capacity of an MOS capacitor can be arbitrarily set, and the size of the electrodes can be reduced as the surface area increases.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to M
OS (Metal-Oxide-8emicond
Actor) The present invention relates to a capacitor and its manufacturing method.

[Conventional technology]

Conventionally, MOS capacitors have mainly had a flat plate-like structure with all layers. This manufacturing method will be explained with reference to FIG.

First, as shown in FIG. 3(a), a silicon oxide film (Si02) 32 is formed to a desired thickness on a silicon substrate 31 by thermal oxidation. Next, as shown in FIG. 3(b), a metal film 33 is formed on the 5iO1 film 32 by vacuum deposition.

Next, as shown in FIG. 3(c), the metal film 33 f /# is turned using a known photolithography technique to form an electrode 34 having a gold layer over a desired area.

Thereafter, heat treatment is performed at about 500° C. in an inert gas atmosphere.

With the above steps, the method for manufacturing a Δ=1OS capacitor is completed.

Taking this into account, MOS capacitors with different static capacitances are made by changing the film thickness of 5i021imo32 by thermal oxidation treatment,
It is manufactured by changing the area of the electrode 34 formed by patterning the metal film 33 and gold.

[Problem that the invention seeks to solve]

However, in the conventional MOS capacitor described above, since the structure is a flat plate type, when the body material is fixed to the dielectric 1, the capacitance can be controlled by the dielectric 5i02 film (
The dielectric constant ε (3.0 to 3.5) is largely dependent on the film thickness and electrode area.

For this reason, for example, the thickness of the SiO□ film is set to 9×103 people,
In order to triple the static capacity i from 8 pF to 24 pF, what is the electrode area? 7.3 x 10'μm2 to 2.2 x 1010
5tt, three times as much is required proportionally, and there is a problem that the chip area increases as the capacity increases.

Conversely, to reduce the capacitance from 24 pF to 1/3 from 8 pF by setting the total surface area to 2.2 x 105 μm2, the thickness of the film should be changed from 3 x 10 3 to 9 x 10 3. Since it takes three times as much inversely, there is a problem that the thermal oxidation treatment time becomes longer than the capacity reduction.

Therefore, it is an object of the present invention to solve the above-mentioned problems and to provide a small, large-capacity MOS capacitor that can have a wide range of capacitances, and a method for manufacturing the same.

[Means for solving problems]

The MOS capacitor of the first invention described in the claims includes a semiconductor substrate having a large number of grooves on the surface, a dielectric oxide film formed on the semiconductor substrate, and a dielectric oxide film formed on the dielectric oxide film. and an electrode.

A second invention described in the claims is an invention of a method for manufacturing MOS capacitor gold according to the first invention, which comprises: etching a semiconductor substrate to form a large number of #s on the surface; A dielectric oxide film is formed first, and then the entire electrode is formed on the dielectric oxide film.

[Effect]

As described above, according to the present invention, a dielectric oxidation pattern is completely formed on a semiconductor substrate having a large number of grooves formed by etching. Therefore, the total surface area of the semiconductor substrate can be increased and controlled by changing the amount of etching of the grooves, so that the total capacitance of the MOS capacitor can be set arbitrarily. Additionally, as the surface area increases, the electrode dimensions can be reduced, so for example when reducing capacitance,
As the electrode dimensions can be reduced, the increase in the thickness of the dielectric oxide film can be reduced and changes can be made easily.

〔Example〕

Hereinafter, an embodiment of a MOS capacitor according to the first invention will be described in detail based on FIG. 1(e).

In the figure, reference numeral 11 denotes a semiconductor substrate made of a silicon substrate, the surface area of which is defined by a large number of grooves 11a formed in a stripe or lattice shape by etching, for example.
It is set to the desired level. Further, 13 is a dielectric oxide film consisting of a silicon j oxide film (S'0! r' and 3.0 to 3.5), which is formed to a desired thickness by thermally oxidizing a thin sheet metal. has been done. Historically, 14a is an electrode formed by turning to a predetermined size.

In the above embodiment, Tpi is formed in a stripe or grid pattern.
11 a f, but in addition to this, if it is arranged in a lattice shape, for example, as shown in Fig. 2, it is possible to add 1311b in the diagonal direction (downward to the right in the figure). You can also do it.

In this way, the pattern of the grooves 11a is not limited to stripes, lattice patterns, etc. from the technical perspective of the present invention, but can be formed in many patterns, whether regular or irregular, depending on the amount of etching of the semiconductor substrate 11. Any pattern that can be formed and whose surface area can be increased and controlled may be used.

Moreover, the groove 11a can also be formed into a tapered shape if necessary.

Next, a method for manufacturing a MOS capacitor having the above-described structure, which is a second invention, will be described with reference to FIGS. 1(a) to 1(e).

First, as shown in FIG. 1(a), a resist is coated on a semi-23-piece substrate 11 made of a silicon substrate, masked, exposed, and developed. By turning, the entire resist mask 12 is formed. Next, as shown in FIG. 1(b), the silicon base &11 is etched through the resist mask 12 to form f411a in a stripe or lattice shape to make the bottom surface uneven, and then the resist mask 12 is removed. do.

Next, as shown in FIG. 1(C), the substrate is thermally oxidized to form a dielectric oxide film 13 made of silicon oxide B (St Ox). Form the film to a desired thickness. After that.

As shown in FIG. 1(d), a metal film 14 is deposited on the 5108 film 13 by vacuum deposition.

Thereafter, as shown in FIG. 1(6), the metal film 14f/# is turned by the known F/IJ lithography technique to form an electrode 14a covering the entire predetermined area. Further, heat treatment is performed at approximately 500° C. in an inert gas atmosphere to improve the ohmic characteristics.

Here, the advantages of the MOS capacitor of the present invention will be explained.

First, the electrode mask area was set to 2.2 x 105 μm2, and a striped $Ila with a width of 5 μm, a depth of 511 m, and an interval of 10 μm was formed on a silicon substrate 11.
Taking the case of a capacitor as an example, the effective area of the electrode is 4.4 x 105 μm2, which is twice the area of the electrode mask. Therefore, when the electrode mask area is the same, the capacitance can be doubled in total compared to a conventional flat plate capacitor. In other words, when manufacturing a MOS capacitor with the same capacity, it is 11 times smaller than the conventional one! Extreme dimension 1/2
and can be made small.

In addition, from the point of view of controlling the thickness of the 5iOffi film 13, in the conventional case, the ta electrode surface injection k
2,2 x 10' pm2, capacitance fn24
In order to increase the pF value to 8 pF, it was necessary to triple the thickness of the 5ift film 13. However, in the MOS capacitor of the present invention manufactured by forming striped grooves 11at with the above dimensions, the electrode area must be 1/2 that of the conventional one in order to increase the capacitance to 8 pF without changing the total electrode mask dimensions for a capacitance of 24 pF.
Therefore, it is only necessary to increase the total film thickness of Sio and Membrane 3 by 1.5 times, which is excellent in terms of workability.

Such advantages in size reduction and workability are achieved by the groove 11.
Of course, the same can be said not only when a is striped but also for the other patterns described above.

〔Effect of the invention〕

As described in detail above, according to the present invention, the number of surface species on the semiconductor substrate is increased and controlled depending on the etching quality of the grooves, that is, the degree of formation of the grooves.

Therefore, the capacitance of the MOS capacitor can be arbitrarily set within a wide range of conditions, and the capacitor can be easily realized in a small size and with a large capacity.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a simple embodiment of the present invention, FIG. 2 is an explanatory diagram of another embodiment of the present invention, and FIG. 3 is a process cross-sectional diagram illustrating a conventional example. DESCRIPTION OF SYMBOLS 11... Semiconductor substrate, lla... Groove, 13... Dielectric oxide film, 14a... Electrode. Patent applicant Oki Electric Industry Co., Ltd. ---1□'. ! !・Semiconductor substrates ffa, lfb: Takao ni 155 month no yani no tsu;
Figure 2

Claims (2)

[Claims] (1) A MOS capacitor comprising a semiconductor substrate having a large number of grooves on its surface, a dielectric oxide film formed on the semiconductor substrate, and an electrode formed on the dielectric oxide film. . (2) (a) A step of etching a semiconductor substrate to form a large number of grooves on the surface; (b) A step of forming a dielectric oxide film on this semiconductor substrate; (c) After that, the above dielectric 1. A method for manufacturing a MOS capacitor, comprising the step of forming an electrode on an oxide film.