JPS6317327B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a capacitor chip in which a pattern of a required capacitance is formed on a conductive layer formed on a substrate surface via an insulator.

To manufacture planar capacitor chips, a flat substrate, such as a silicon wafer or an alumina substrate, is divided by multiple dividing lines, and if necessary, insulation is applied to each divided area in the required pattern. A film and a metallization coating are applied so that a large number of capacitor chips can be manufactured all at once on the substrate.

A conventional method of manufacturing a capacitor chip of this type will be explained with reference to a plan view and a front view of the capacitor chip in FIGS. 1 and 2, respectively. The solid line in the diagram is 1
It shows the division. The case of a capacitor using a silicon wafer as a substrate will be explained. For example, an N-type silicon single crystal wafer with a specific resistance of 0.1 Ω-cm is prepared as the substrate 1, and an insulating film 2, such as a silicon oxide film (SiO ₂ ), is formed on the surface by thermal oxidation or CVD.
The surface is coated using a method such as the above, and unnecessary portions such as partitions are etched away using a well-known photolithography method. Further, the surface of this wafer is coated with metallization such as aluminum or other metal by vapor deposition, sputtering or plating, and desired portions are removed by etching using photolithography. This state is shown for one section in FIGS. 1 and 2. However, at this time, the substrate 1 is not divided into wafers.

Thereafter, if necessary, a metal film is applied to the back surface of the wafer by metallization, and the wafer is divided into required sizes to complete a large number of capacitor chips.

By the way, the capacitance C of the capacitor is determined by the area of the metal layer being s, the thickness of the insulating film being d, the permittivity of vacuum being εo,
If the relative dielectric constant is κe, then C=κeεos/d. Here, assuming that the constituent materials of the capacitors are the same, the capacitance C is determined by the area of the metal layer and the thickness of the insulating film.

Therefore, in the conventional capacitor manufacturing method described above, in order to manufacture capacitor chips of various capacities by changing the area of the metal layer 3, many types of photomasks for the metal layer are required. In addition, when changing the thickness of the insulating film 2, the film thickness must be accurately covered in a pre-manufacturing process, which poses many difficulties in terms of specification changes and thickness variations.

This invention eliminates the drawbacks of the conventional methods described above, and forms a required resist pattern on a conductive layer through multiple photolithography steps using a small number of types of photomasks and shifting the position each time.
It is an object of the present invention to provide a method for manufacturing a capacitor chip, in which a pattern with a required capacitance is formed on a conductive layer through etching treatment, and capacitors with various capacitances can be easily obtained using a small number of photomasks.

Hereinafter, a method for manufacturing a capacitor chip according to an embodiment of the present invention will be explained with reference to plan views of a capacitor shown in the order of steps in FIGS. 3, 5, and 6. First, the pre-process is the same as the pre-process of the conventional method described above. That is, a silicon wafer is prepared as a substrate 1, an insulating film 2 is applied to the surface, and unnecessary portions are etched away using photolithography. Furthermore, this wafer is coated with a metal layer 3 by metallization.

The first layer mask is baked on the wafer coated with the metal layer 3 by a well-known photolithography method using a first photomask, and the photoresist is developed. This state is shown in a plan view and a front view in FIGS. 3 and 4. 4a is a resist pattern of the first layer of the wiring mask, and 5 is an overlay identification mark made on the resist film.

Subsequently, a photoresist is applied on the wafer in the state shown in FIG. 3, and is baked using a second photomask at a position shifted to the right with respect to the first layer resist pattern 4a, and the photoresist is developed. This state is shown in FIG. Reference numeral 4b indicates a resist pattern in the second layer of the wiring mask, and reference numeral 6 indicates a pattern applied to the resist film to hide unnecessary identification marks 5 for photomask alignment. The degree to which the second photomask is shifted to the right is
It is determined from the above formula depending on the required capacitance value. If a mark corresponding to the area value of the metal layer 3 is formed in the chip, it becomes easy to overlap the chip as shown in FIG. 5, and to easily identify the chip when it is divided into chips.

Next, from the state shown in FIG. 5, the metal layer 3 is etched using the first and second layer resist patterns 4a and 4b as masks, as shown in the plan view and front view in FIGS. 6 and 7. , a metal layer pattern 3a having a required area is formed. 7 is an identification mark made of a metal layer, and 8 is a remaining metal layer to hide the unnecessary identification mark. After this, the wafer is divided into multiple capacitor chips.

In this way, capacitors with various capacitances can be manufactured using two photomasks of two types for wiring masks for capacitor formation. Also,
Since the process for determining the capacitor capacity is the subsequent process of baking the second layer of photoresist, it is easy to deal with delays or changes in determining the capacity specifications.

In addition, in the method of the present invention, the substrate may be made of other materials other than silicon wafers, such as alumina, glass,
It can also be applied to ceramics, etc. When the substrate is an insulating material, it is not necessary to form an insulating film on the upper surface, and a ground side metal layer is provided on the lower surface. Also,
In addition to aluminum, other metals such as gold, copper, etc. may be used as the metal layer constituting the conductive layer on the upper surface side. Furthermore, a semiconductor such as polysilicon can also be used as the conductive layer.

As described above, according to the present invention, a small number of types of photomasks are sequentially used while shifting their positions each time on a conductive layer formed on an insulator, and a required resist pattern is formed through multiple photolithography processes. Since the conductive layer is formed and etched to form a pattern with the required capacitance, capacitors corresponding to a large number of capacitances can be easily obtained using a small number of photomasks.

[Brief explanation of the drawing]

Figures 1 and 2 are a plan view and a front view of a capacitor chip manufactured by a conventional manufacturing method, Figures 3 and 5.
6 are plan views showing the capacitor chip according to the manufacturing method of one embodiment of the present invention in the order of steps, FIG. 4 is a front view of FIG. 3, and FIG. 7 is a front view of FIG. 6. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Insulating film, 3...Metal layer forming a conductive layer, 3a...Metal layer pattern, 4a,
4b...Resist pattern, 7...Identification mark made of metal layer. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

[Scope of Claims] 1. A conductive layer in each section formed by metallization on a substrate made of a conductive material and coated with an insulating film on the upper surface, or on a substrate made of an insulating material and coated with a metal film on the lower surface. In the method of manufacturing a plurality of capacitor chips by forming patterns each having a predetermined capacitance on the substrate and dividing the substrate into sections, the position of a small number of photomasks is shifted by one type each time with respect to the conductive layer. A method for manufacturing a capacitor chip, which comprises sequentially using a plurality of capacitors, forming a required resist pattern on a conductive layer through a plurality of photolithography steps, and performing etching treatment to form a pattern with a required capacitance on the conductive layer. 2. A method for manufacturing a capacitor chip according to claim 1, characterized in that an overlay identification mark is formed on the resist pattern, and the identification mark is formed on the conductive layer by etching. 3. The method for manufacturing a capacitor chip according to claim 1 or 2, wherein the substrate is made of a semiconductor wafer. 4. The method for manufacturing a capacitor chip according to any one of claims 1 to 3, wherein the conductive layer is made of a metal layer.