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KR910000277B1 - Manufacturing Method of Semiconductor Device - Google Patents

Manufacturing Method of Semiconductor Device Download PDF

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KR910000277B1
KR910000277B1 KR1019870015349A KR870015349A KR910000277B1 KR 910000277 B1 KR910000277 B1 KR 910000277B1 KR 1019870015349 A KR1019870015349 A KR 1019870015349A KR 870015349 A KR870015349 A KR 870015349A KR 910000277 B1 KR910000277 B1 KR 910000277B1
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insulating film
substrate
connection window
conductive film
semiconductor device
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KR890011059A (en
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이윤진
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삼성전자 주식회사
강진구
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0149—Manufacturing their interconnections or electrodes, e.g. source or drain electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

내용 없음.No content.

Description

반도체 장치의 제조방법Manufacturing Method of Semiconductor Device

제1a-b도는 종래 접속창 형성방법에 따른 반도체 장치의 레이아웃 및 단면도.1A-B are a layout and a cross-sectional view of a semiconductor device according to a conventional method for forming a connection window.

제2도는 본 발명에 따른 반도체 장치의 레이아웃 평면도.2 is a layout plan view of a semiconductor device according to the present invention.

제3a-d도는 본 발명에 따른 제조공정도.3a-d is a manufacturing process diagram according to the present invention.

본 발명은 반도체 장치의 제조공정에 관한 것으로서 특히 다층의 배선을 형성하는 공정에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a manufacturing process of a semiconductor device, and more particularly to a process of forming a multilayer wiring.

반도체 장치가 점차적으로 고집적화 되어감에 따라 소자형성후의 배선공정은 더욱더 고도의 기술을 필요로 할뿐 아니라 다층의 배선층을 형성하고 배설층간을 접속하거나 좁아진 배선층 사이로 하부층과 접속하기 위한 접속창을 형성하는 공정이 어려워진다.As semiconductor devices become increasingly integrated, the wiring process after element formation not only requires more advanced techniques, but also forms connection windows for forming multilayer wiring layers and connecting interconnect layers or connecting lower layers with narrower wiring layers. The process becomes difficult.

제1a도는 종래 제1도전막 사이에 형성된 접속창을 통해 반도체 기판과 접속하는 실시예의 반도체 장치의 레이아웃 평면도를 도시한 것이다.FIG. 1A shows a layout plan view of a semiconductor device of an embodiment in which a conventional semiconductor device is connected to a semiconductor substrate through a connection window formed between the first conductive films.

도면을 참조하면 영역(1)(2)는 기판상에 형성된 소자부분과 소정영역 이외에는 절연되게 형성되는 제1도전막 영역이고, 영역(3)는 제1도전막과 기판상에서 기판과 영역(4)의 접속창 영역을 제외하고는 절연되게 형성되는 제2도전막 영역이다.Referring to the drawings, regions (1) and (2) are first conductive film regions which are formed to be insulated other than a predetermined region and an element portion formed on the substrate, and region (3) is a substrate and region (4) on the first conductive film and the substrate. A second conductive film region is formed to be insulated except for the connection window region.

제1b도는 제1a도의 평면도를 갖는 반도체 장치에서 접속창을 형성하기 위하여 마스크 패턴을 형성하고 접속창을 형성한 단면도를 도시한 것이다.FIG. 1B illustrates a cross-sectional view of forming a mask pattern and forming a connection window in order to form a connection window in the semiconductor device having the plan view of FIG. 1A.

도면을 참조하면 반도체 기판(5)상에 기판과 절연되게 제1도전막(6)을 형성하고 제1도전막(6)상에 이후 형성되는 제2도전막과의 절연을 위해서 절연막(7)을 형성한후 상기 제1a도의 영역(4)와 같이 좁은 접속창 형성을 위하여 포토레지스트 마스크 패턴(8)을 형성하고 상기 포토레지스트 마스크 패턴(8)을 식각 마스크로 하여 접속창 영역(9)의 절연막(7)을 식각한다. 상기와 같이 접속창이 형성되면 포토레지스트 마스크 패턴(8)을 제거하고 제2도전막을 형성한다. 그러나 반도체 장치가 점점 고집적화되면서 도선간의 공간이 더욱 좁아지게 되며 도전막 사이의 좁은 공간에 접속창을 형성할 경우에는 사진 공정시 형성할 수 있는 접속창 마스크 패턴의 한계를 넘는 경우도 생길수 있을뿐 아니라 마스크 패턴 형성이 어려우며 식각도 용이하지 못한 문제점이 있었다.Referring to the drawings, the first conductive film 6 is formed on the semiconductor substrate 5 to be insulated from the substrate, and the insulating film 7 is insulated from the second conductive film subsequently formed on the first conductive film 6. After forming the photoresist mask pattern 8 to form a narrow junction window like the region 4 of FIG. 1a and forming the photoresist mask pattern 8 as an etching mask, The insulating film 7 is etched. When the connection window is formed as described above, the photoresist mask pattern 8 is removed to form a second conductive film. However, as semiconductor devices become more and more integrated, the space between conductors becomes narrower, and when the connection window is formed in the narrow space between the conductive layers, it may not be possible to exceed the limit of the connection window mask pattern that can be formed during the photolithography process. The mask pattern is difficult to form and there is a problem that the etching is not easy.

또한 상기 문제점들로 인하여 소자의 고집적화에도 한계를 가져왔다.In addition, due to the above problems, there is a limit to the high integration of the device.

따라서 본 발명의 목적은 실제공간보다 더 크게 마스크 패터닝(Patterning)을 하고도 더 작은 접속창(Contact Hole)을 형성할 수 있어서 공정의 실시가 용이하고 소자의 집적도를 높일수 있는 반도체 장치의 제조방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a semiconductor device that can be formed in a smaller contact hole even after mask patterning than a real space, thereby facilitating the process and increasing the device integration. In providing.

이하 본 발명을 첨부한 도면을 참조하여 상세히 설명한다.Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

제2도는 본 발명에 따른 접속창을 형성하는 반도체 장치의 일실시예의 레이아웃 평면도이다.2 is a layout plan view of an embodiment of a semiconductor device for forming a connection window according to the present invention.

도면을 참조하면 영역(11)(12) 제1도전막 영역이고 이 영역은 기판 및 기판에 형성된 소자부분과 소정 영역에서 접속되고 나머지 영역에서는 제1절연막으로 절연되게 형성된 영역이다. 또한 영역(13)은 기판과 영역(15)의 접속창을 통해 접속되고 나머지 영역과 절연되게 형성되는 제2도전막 영역이고, 영역(14)는 접속창 영역(15)을 형성하기 위한 본 발명에 따른 접속창 마스크 영역이다.Referring to the drawings, the regions 11 and 12 are first conductive film regions which are connected to a substrate and an element portion formed on the substrate in a predetermined region and are insulated from the first insulating film in the remaining regions. In addition, the region 13 is a second conductive film region which is formed through the connection window between the substrate and the region 15 and is insulated from the remaining region, and the region 14 is the present invention for forming the connection window region 15. According to the connection window mask area.

상기 제2도에 도시한 바와같이 접속창 마스크폭을 d1만큼 가지는 넓은 포토레지스트 마스크로 형성하나 실제 제2도전막과 기판이 접속하는 부분의 접속창을 폭이 d2인 영역(15)이다.As shown in FIG. 2, the area 15 is formed by a wide photoresist mask having a connection window mask width d1, but the connection window of the portion where the second conductive film is connected to the substrate is d2 in width.

제3a-d도는 본 발명에 따른 실시예의 제조공정도로서 소자가 형성된 반도체 기판(20)상에 다층의 배선을 형성하는 공정이다.3A to 3D are manufacturing process diagrams of an embodiment according to the present invention, in which a multilayer wiring is formed on a semiconductor substrate 20 on which elements are formed.

도면중 소자가 형성된 반도체 기판 부분은 도시하지 않았으나 제1도전막과 접속되는 부분은 필요한 부위에서 제1절연막을 통해 접속창을 형성하고 접속함은 이미 잘 알려진 사실임을 유의하여야 한다.Although not shown in the drawing, the portion of the semiconductor substrate on which the element is formed is to be noted that it is already well known that the portion to be connected to the first conductive film forms a connection window through the first insulating film at a necessary portion.

제3a도를 참조하면 제1절연막(21)이 형성된 반도체 기판(20)상에 제1도전막(22)을 형성하고 제1도전막(22)상에 제2절연막(23)을 도포하고 통상의 사진 식각공정으로 제2절연막(23)과 제1도전막(22)을 함께 패터닝(Patterning)하여 제1도전막(22) 상부에 제2절연막(23)을 남게 형성한다.Referring to FIG. 3A, the first conductive film 22 is formed on the semiconductor substrate 20 on which the first insulating film 21 is formed, and the second insulating film 23 is coated on the first conductive film 22. The second insulating layer 23 and the first conductive layer 22 are patterned together in a photolithography process to form a second insulating layer 23 on the first conductive layer 22.

상기에서는 제1도전막상에 제2절연층을 형성하고 함께 패터닝을 한 실시예를 나타내었으나 제1절연막상에 제1도전막을 패터닝한후 제1도전막의 상부와 측벽에 제2절연막을 형성하여 공정을 진행할 수도 있다.In the above, an embodiment in which a second insulating layer is formed on the first conductive layer and patterned together is shown. However, after the first conductive layer is patterned on the first insulating layer, a second insulating layer is formed on the top and sidewalls of the first conductive layer. You can also proceed.

상기 제2절연막(23)은 제1도전막(22) 하부에 반도체 기판상의 소자부분과 절연을 목적으로 형성된 제1절연막(21)의 두께보다 충분히 두껍게 형성한다.The second insulating layer 23 is formed to be thicker than the thickness of the first insulating layer 21 formed for the purpose of insulating the element portion on the semiconductor substrate under the first conductive layer 22.

그다음 기판 전면에 제3절연막(24)을 도포한후 제2도와 같은 접속창 마스크를 형성하기 위하여 포토레지스트를 도포하고 통상의 사진공정으로 제3b도와 같이 접속창 마스크 패턴(25)을 형성한다.Then, after the third insulating film 24 is coated on the entire surface of the substrate, a photoresist is applied to form a connection window mask as shown in FIG. 2, and the connection window mask pattern 25 is formed as shown in FIG.

그다음 상기 마스크 패턴(25)을 식각 마스크로 하여 상기 공정에서 노출된 영역(26)의 절연막을 식각한다. 이때 접속창 영역에서 제1도전막(22) 하부의 제1절연막(21)이 모두 제거되도록 식각을 하면 제1도전막 측벽에 제3절연막의 잔유물(27)이 남게되고 마스크되지 않은 영역(26)의 제2절연막(23)은 제1도전막 하부의 제1절연막(21)의 두께만큼 식각되어 제3c도와 같이 접속창(28)이 형성한다. 제2절연막의 접속창쪽 부위는 제1절연막만큼 식각이 되나 제2절연막의 두께가 제1절연막보다 충분히 두꺼우므로 제2도전막 형성시 제1도전막과의 절연에는 문제가 없게된다. 그다음 상기 기판상에 제2도전막(29)을 형성하면 상기 제2도전막(29)은 상기 접속창(28)을 통해 기판(20)과 접속하게 된다.[제3d도]Next, the insulating film of the region 26 exposed in the process is etched using the mask pattern 25 as an etch mask. In this case, when the first insulating film 21 under the first conductive film 22 is etched away from the connection window area, the residue 27 of the third insulating film remains on the sidewall of the first conductive film and the unmasked area 26 The second insulating film 23 of () is etched by the thickness of the first insulating film 21 under the first conductive film to form a connection window 28 as shown in 3c. The connection window side portion of the second insulating film is etched as much as the first insulating film, but since the thickness of the second insulating film is sufficiently thicker than that of the first insulating film, there is no problem in insulation from the first conductive film when the second conductive film is formed. Then, when the second conductive film 29 is formed on the substrate, the second conductive film 29 is connected to the substrate 20 through the connection window 28. [FIG. 3D]

상술한 바와같이 본 발명은 상부에 절연막이 형성된 제1도전막상에 한번 더 절연막을 형성한후 마스크 패턴을 접속창 영역보다 넓게 형성하고 좁은 접속창을 형성하여 좁게 형성된 접속창을 통해 기판과 제2도전막을 형성함으로써 도선과 도선 사이의 공간에 구애됨이 없이 작은 접속창을 넓은 접속창 마스크로 쉽게 형성할 수 있다.As described above, in the present invention, after forming the insulating film on the first conductive film having the insulating film formed thereon, the mask pattern is formed wider than the connection window area and the narrow connection window is formed to form the substrate and the second through the narrowly formed connection window. By forming the conductive film, a small connection window can be easily formed as a wide connection window mask without being limited to the space between the conductive wires and the conductive wires.

따라서 본 발명은 공정이 용이하게 고집적화 할수 있는 이점이 있다.Therefore, the present invention has the advantage that the process can be easily integrated.

Claims (4)

반도체 장치의 제조방법에 있어서, 반도체 기판상의 제1절연막상에 상기 반도체 기판에 형성된 소자의 소정부분과 접속을 하기 위한 제1도전막을 도포하는 제1공정과, 상기 제1도전막상에 제2절연막을 도포하고 제2절연막과 제1도전막을 함께 패터닝하는 제2공정과, 기판상에 제3절연막을 도포하는 제3공정과, 접속창 형성을 위하여 기판상에 접속창 영역보다 넓은 접속창 마스크를 형성하는 제4공정과, 상기 접속창 마스크를 식각 마스크로 하여 접속창 영역을 식각하는 제5공정과, 상기 접속창 마스크를 제거하고 기판상에 제2도전막을 형성하는 제6공정을 구비하여 상기 공정의 연속으로 이루어짐을 특징으로 하는 반도체 장치의 제조방법.A method of manufacturing a semiconductor device, comprising: a first step of applying a first conductive film for connection with a predetermined portion of an element formed on the semiconductor substrate on a first insulating film on a semiconductor substrate; and a second insulating film on the first conductive film. And a second step of patterning the second insulating film and the first conductive film together, a third step of applying the third insulating film on the substrate, and forming a connection window mask wider than the connection window area on the substrate to form the connection window. And a fourth step of forming, a fifth step of etching the connection window area by using the connection window mask as an etching mask, and a sixth step of removing the connection window mask and forming a second conductive film on the substrate. A method for manufacturing a semiconductor device, characterized by a continuous process. 제1항에 있어서, 제2절연막을 제1절연막보다 충분히 두꺼운 두께의 절연산화막임을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 1, wherein the second insulating film is an insulating oxide film having a thickness thicker than that of the first insulating film. 반도체 장치의 제조방법에 있어서, 반도체 기판상의 제1절연막상에 상기 반도체 기판에 형성된 소자의 소정부분과 접속을 하기 위한 제1도전막을 형성하는 제1공정과, 상기 제1도전막 상부와 측면에 제2절연막을 형성하는 제2공정과, 기판상에 제3절연막을 도포하는 제3공정과, 접속창 형성을 위하여 기판상에 접속창 영역보다 넓은 접속창 마스크를 형성하는 제4공정과, 상기 접속창 마스크를 식각 마스크로 하여 접속창 영역을 식각하는 제5공정과, 상기 접속창 마스크를 제거하고 기판상에 제2도전막을 형성하는 제6공정을 구비하여 상기 공정의 연속으로 이루어짐을 특징으로 하는 반도체 장치의 제조방법.A method of manufacturing a semiconductor device, comprising: a first step of forming a first conductive film for connection with a predetermined portion of an element formed on the semiconductor substrate on a first insulating film on a semiconductor substrate, and on top and side surfaces of the first conductive film; A second step of forming a second insulating film, a third step of applying a third insulating film on the substrate, a fourth step of forming a connection window mask wider than the connection window area on the substrate to form a connection window, and And a fifth process of etching the junction window region using the junction window mask as an etch mask, and a sixth process of removing the junction window mask and forming a second conductive film on the substrate. A method of manufacturing a semiconductor device. 제3항에 있어서, 제2절연막이 제1절연막보다 충분히 두꺼운 두께의 절연산화막임을 특징으로 하는 반도체 장치의 제조방법.The method of manufacturing a semiconductor device according to claim 3, wherein the second insulating film is an insulating oxide film having a thickness thicker than that of the first insulating film.
KR1019870015349A 1987-12-30 1987-12-30 Manufacturing Method of Semiconductor Device Expired KR910000277B1 (en)

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KR910000277B1 true KR910000277B1 (en) 1991-01-23

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