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KR0179707B1 - Multi-layer interconnection structure of semiconductor device and method for manufacturing thereof - Google Patents

Multi-layer interconnection structure of semiconductor device and method for manufacturing thereof Download PDF

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Publication number
KR0179707B1
KR0179707B1 KR1019950046087A KR19950046087A KR0179707B1 KR 0179707 B1 KR0179707 B1 KR 0179707B1 KR 1019950046087 A KR1019950046087 A KR 1019950046087A KR 19950046087 A KR19950046087 A KR 19950046087A KR 0179707 B1 KR0179707 B1 KR 0179707B1
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metal
insulating film
forming
metal layer
substrate
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KR1019950046087A
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KR970053507A (en
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황준
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김주용
현대전자산업주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204—Conductive materials
    • H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

본 발명은 반도체 장치의 다층 배선구조 제조방법에 관한 것으로, 인접한 금속라인간의 간격을 노광기의 해상력 한계 이하로 최소로 유지할 수 있도록 한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a multi-layered wiring structure of a semiconductor device, wherein the spacing between adjacent metal lines can be kept to a minimum below the resolution limit of the exposure machine.

본 발명은 반도체기판상에 층간절연막을 형성하는 단계와; 상기 층간절연막을 선택적으로 식각하여 복수 개의 콘택트을 형성하는 단계; 기판 전면에 제1금속층을 형성하는 단계; 상기 제1금속층상에 제1절연막을 형성하는 단계; 상기 제1절연막과 제1금속층을 소정패턴으로 패터닝하여 제1금속배선을 형성하는 단계; 상기 제1금속배선의 노출된 표면에만 제2절연막을 형성하는 단계; 기판 전면에 제2금속층을 형성하는 단계; 및 상기 제2금속층을 상기 제1금속배선 상부의 제1절연막이 노출되도록 화학적 기계 연마하여 제2금속배선을 형성하는 단계로 이루어지는 반도체 장치의 다층 배선구조의 제조방법을 제공한다.The present invention comprises the steps of forming an interlayer insulating film on a semiconductor substrate; Selectively etching the interlayer insulating film to form a plurality of contacts; Forming a first metal layer on the entire surface of the substrate; Forming a first insulating film on the first metal layer; Patterning the first insulating layer and the first metal layer in a predetermined pattern to form a first metal wiring; Forming a second insulating film only on the exposed surface of the first metal wiring; Forming a second metal layer on the entire surface of the substrate; And chemically mechanically polishing the second metal layer to expose the first insulating layer on the first metal wire, thereby forming a second metal wire.

Description

반도체 장치의 다층 배선구조 및 그 제조방법Multilayer wiring structure of semiconductor device and manufacturing method thereof

제1도는 종래의 반도체 장치의 배선 형성방법을 도시한 공정순서도.1 is a process flowchart showing a wiring forming method of a conventional semiconductor device.

제2도는 본 발명에 의한 반도체 장치의 다층 배선구조 형성방법을 도시한 공정순서도.2 is a process flowchart showing a method for forming a multilayer wiring structure of a semiconductor device according to the present invention.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1 : 반도체기판 2 : 층간절연막1: semiconductor substrate 2: interlayer insulating film

3 : 제1금속배선 4, 6 : Al2O3막3: first metal wiring 4, 6: Al 2 O 3 film

5 : 포토레지스트패턴 7 : 제2금속배선5: photoresist pattern 7: second metal wiring

본 발명은 반도체 장치의 다층 배선구조 및 그 제조방법에 관한 것으로, 특히 노광기의 해상력의 한계를 넘는 금속라인간의 간격 폭(sapce width)을 갖는 다층의 접속구조(interconnection) 및 이의 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring structure of a semiconductor device and a method of manufacturing the same, and more particularly, to a multilayer interconnection structure having a spacing width between metal lines exceeding a limit of resolution of an exposure apparatus, and a method of forming the same. .

반도체 장치의 다층구조의 배선 형성공정에 있어서, 하부 금속층의 포토마스크(photomask) 패턴 형성시 노광기의 해상력의 한계가 있기 때문에 금속라인과 인접한 금속라인과의 간격이 커질 수밖에 없어(통상 0.5㎛ 이상 유지해야 함) 매우 넓은 영역에 걸쳐 고집적화에 장애를 가져오게 되며, 특히 다층 배선구조에 있어서 고집적화에 커다란 장래 요인으로 작용하게 된다.In the wiring formation process of the multilayer structure of the semiconductor device, since the resolution of the exposure machine is limited when forming the photomask pattern of the lower metal layer, the distance between the metal line and the adjacent metal line is large (usually maintained at 0.5 μm or more). It causes obstacles to high integration over a very wide area, and it is a great future factor for high integration especially in multi-layer wiring structure.

제1도에 종래 기술에 의한 배선 형성방법을 도시하였다.1 shows a wiring forming method according to the prior art.

먼저, 제1도 (a)에 도시된 바와 같이 반도체기판(11)상에 절연층(12)을 형성한 후, 이를 소정의 패턴으로 패터닝하여 배선 접속을 위한 콘택홀을 형성한 후, 제1도 (b)에 도시된 바와 같이 기판 전면에 금속을 증착하고 이를 소정의 금속라인 패턴으로 패터닝하여 상기 콘택홀을 통해 기판과 접속되는 금속배선(13)을 형성한다. 이때, 상기에서 설명한 바와 같이 금속배선 패터닝시의 노광기의 해상력 한계로 인해 인접한 금속배선간의 간격(W)을 감소시키는데 한계가 따르게 된다. 이는 반도체 장치의 고집적화에 제한요인으로 작용하게 된다.First, as shown in FIG. 1A, an insulating layer 12 is formed on the semiconductor substrate 11, and then patterned into a predetermined pattern to form a contact hole for wiring connection. As shown in (b), a metal is deposited on the entire surface of the substrate and patterned into a predetermined metal line pattern to form a metal wiring 13 connected to the substrate through the contact hole. At this time, as described above, due to the limitation of the resolution of the exposure machine during the patterning of the metal wiring, the limit is followed to reduce the distance W between adjacent metal wirings. This is a limiting factor in the high integration of the semiconductor device.

본 발명은 상술한 종래 기술의 문제를 해결하기 위한 것으로, 인접한 금속라인간의 간격을 노광기의 해상력 한계 이하로 최소로 유지할 수 있도록 한 반도체 장치의 다층 배선구조 및 이의 제조방법을 제공하는데 그 목적이 있다.SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a multilayer wiring structure of a semiconductor device and a method of manufacturing the same so that the distance between adjacent metal lines can be kept to a minimum below the resolution limit of the exposure machine. .

상기 목적을 달성하기 위한 본 발명의 반도체 장치의 다층 배선구조는 반도체기판과; 상기 반도체기판상에 형성된 복수 개의 콘택홀을 갖춘 층간절연막; 상기 복수 개의 콘택홀 상에 형성되어 콘택홀을 통해 기판에 접속되되, 콘택홀을 하나씩 건너뛰어 형성되는 복수 개의 제1금속배선; 상기 제1금속배선 전표면에 형성된 절연막; 및 상기 제1금속배선 사이사이에 상기 콘택홀을 통해 기판에 접속되는 복수 개의 제2금속배선으로 구성되는 것을 특징으로 한다.The multilayer wiring structure of the semiconductor device of the present invention for achieving the above object is a semiconductor substrate; An interlayer insulating film having a plurality of contact holes formed on the semiconductor substrate; A plurality of first metal wires formed on the plurality of contact holes and connected to the substrate through the contact holes, wherein the plurality of first metal wires are formed by skipping the contact holes one by one; An insulating film formed on the entire surface of the first metal wiring; And a plurality of second metal wires connected to the substrate through the contact hole between the first metal wires.

상기 목적을 달성하기 위한 본 발명의 반도체 장치의 다층 배선구조 제조방법은 반도체기판 상에 층간절연막을 형성하는 단계와; 상기 층간절연막을 선택적으로 식각하여 복수 개의 콘택홀을 형성하는 단계; 기판 전면에 제1금속층을 형성하는 단계; 상기 제1금속층상에 제1절연막을 형성하는 단계; 상기 제1절연막과 제1금속층을 소정패턴으로 패터닝하여 제1금속배선을 형성하는 단계; 상기 제1금속배선의 노출된 표면에만 제2절연막을 형성하는 단계; 기판 전면에 제2금속층을 형성하는 단계; 및 상기 제2금속층을 상기 제1금속배선 상부의 제1절연막이 노출되도록 화학적 기계 연마하여 제2금속배선을 형성하는 단계로 이루어진다.A method for manufacturing a multilayer wiring structure of a semiconductor device of the present invention for achieving the above object comprises the steps of forming an interlayer insulating film on a semiconductor substrate; Selectively etching the interlayer insulating film to form a plurality of contact holes; Forming a first metal layer on the entire surface of the substrate; Forming a first insulating film on the first metal layer; Patterning the first insulating layer and the first metal layer in a predetermined pattern to form a first metal wiring; Forming a second insulating film only on the exposed surface of the first metal wiring; Forming a second metal layer on the entire surface of the substrate; And chemically polishing the second metal layer to expose the first insulating layer on the first metal wiring to form a second metal wiring.

이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.

제2도에 본 발명의 일실시예에 의한 반도체 장치의 다층 배선구조 형성방법을 공정순서에 따라 도시하였다.2 illustrates a method for forming a multilayer wiring structure of a semiconductor device according to an embodiment of the present invention in accordance with the process sequence.

먼저, 제2도 (a)에 도시된 바와 같이 반도체기판(1)상에 층간절연막(2)으로서, 예컨대 BPSG(borophospho-silicate glass)와 같은 도우프드(doped) 산화막을 형성한 후, 이를 선택적으로 식각하여 배선 접속을 위한 콘택홀을 형성한다.First, as shown in FIG. 2 (a), a doped oxide film such as borophospho-silicate glass (BPSG), for example, is formed on the semiconductor substrate 1 and then selectively Etching to form a contact hole for wiring connection.

이어서 제2도 (b)에 도시된 바와 같이 상기 기판 전면에 제1금속층(3)으로서, A1을 형성하고, 이위에 절연막으로서, Al2O3막(4)을 형성한다. 이 때, Al2O3막은 상기 제1금속층인 Al이 증착된 기판을 뜨거운 순수(DI;deionized water)에 린스함으로써 성장시키는 자연산화막을 이용하며, 그 두께는 200-800Å으로 한다. 이어서 상기 Al2O3막(4)위에 포토레지스트를 도포한 후, 이를 선택적으로 노광 및 현상하여 소정의 제1금속배선 패턴(5)을 형성한다.Subsequently, as shown in FIG. 2 (b), A1 is formed on the entire surface of the substrate as the first metal layer 3, and an Al 2 O 3 film 4 is formed thereon as an insulating film. At this time, the Al 2 O 3 film is a natural oxide film which is grown by rinsing a substrate on which Al, which is the first metal layer, is deposited, with hot pure water (DI; deionized water). Subsequently, a photoresist is applied on the Al 2 O 3 film 4, and then selectively exposed and developed to form a predetermined first metal wiring pattern 5.

다음에 제2도 (c)에 도시된 바와 같이 상기 포토레지스트패턴(5)을 마스크로 이용하여 상기 Al2O3막(4)과 제1금속층(3)을 식각하여 제1금속배선(3)을 형성한 후, 양극산화(anodic oxidation) 방식으로 상기 제1금속층(3)의 노출된 표면에만 약 200-1500Å 두께의 Al2O3막(6)이 형성되도록 한다. 따라서 상기 제1금속배선(3)의 상부와 측면에 Al2O3막(4, 6)이 형성되게 된다.Next, as shown in FIG. 2C, the Al 2 O 3 film 4 and the first metal layer 3 are etched using the photoresist pattern 5 as a mask to form the first metal wiring 3. ), The Al 2 O 3 film 6 having a thickness of about 200-1500 Å is formed only on the exposed surface of the first metal layer 3 by anodizing. Therefore, Al 2 O 3 films 4 and 6 are formed on the upper and side surfaces of the first metal wire 3.

이어서 제2도 (d)에 도시된 바와 같이 상기 포토레지스트패턴을 제거한 후, 기판 전면에 제2금속층(7)을 스퍼터링에 의해 증착하여 형성한다.Subsequently, as shown in FIG. 2 (d), the photoresist pattern is removed and a second metal layer 7 is formed by sputtering on the entire surface of the substrate.

다음에 제2도 (e)에 도시된 바와 같이 상기 제2금속층(7)을 상기 제1금속배선 상부의 Al2O3막(4)이 노출되도록 화학적 기계 연마(CMP;chemical mechanical polishing) 하여 제2금속배선(7)을 형성한다.Next, as illustrated in FIG. 2E, the second metal layer 7 is chemically mechanically polished to expose the Al 2 O 3 film 4 on the first metal wiring. The second metal wiring 7 is formed.

이와 같이 함으로써 Al2O3막에 의해 절연된 제1금속배선(3)과 제2금속배선(7)을 동일 평면상에 형성할 수 있다.In this way, the first metal wiring 3 and the second metal wiring 7 insulated by the Al 2 O 3 film can be formed on the same plane.

이상 상술한 바와 같이 본 발명의 다층구조 배선은 1개 라인씩 건너뛰어 제1금속배선을 형성하고, 그 사이에 제2금속배선이 형성되도록 하며, 제1금속배선과 제2금속배선 사이는 얇은 Al2O3막에 의해 절연되도록 함으로써 인접한 배선간의 간격을 노광기의 해상력 한계 이하로 형성할 수 있게 되어 고집적화에 유리하게 되며, 제1금속배선과 제2금속배선을 동일 레벨로 형성하므로 표면이 평탄화되는 효과를 얻을 수 있다.As described above, the multi-layered wiring of the present invention skips one line to form a first metal wiring, and a second metal wiring is formed therebetween, and the first metal wiring and the second metal wiring are thin. Insulation by the Al 2 O 3 film makes it possible to form a gap between adjacent wirings below the resolution limit of the exposure machine, which is advantageous for high integration. The first and second metal wirings are formed at the same level so that the surface is flattened. The effect can be obtained.

Claims (10)

반도체기판과; 상기 반도체기판상에 형성된 복수 개의 콘택홀을 갖춘 층간절연막; 상기 복수 개의 콘택홀 상에 형성되어 콘택홀을 통해 기판에 접속되되, 콘택홀을 하나씩 건너뛰어 형성되는 복수 개의 제1금속배선; 상기 제1금속배선 전표면에 형성된 절연막; 및 상기 제1금속배선 사이사이에 상기 콘택홀을 통해 기판에 접속되는 복수 개의 제2금속배선으로 구성되는 것을 특징으로 하는 반도체 장치의 다층 배선구조.A semiconductor substrate; An interlayer insulating film having a plurality of contact holes formed on the semiconductor substrate; A plurality of first metal wires formed on the plurality of contact holes and connected to the substrate through the contact holes, wherein the plurality of first metal wires are formed by skipping the contact holes one by one; An insulating film formed on the entire surface of the first metal wiring; And a plurality of second metal wirings connected to the substrate through the contact hole between the first metal wirings. 제1항에 있어서, 상기 절연막은 Al2O3막임을 특징으로 하는 반도체 장치의 다층 배선구조.The multilayer wiring structure of a semiconductor device according to claim 1, wherein said insulating film is an Al 2 O 3 film. 반도체기판상에 층간절연막을 형성하는 단계와; 상기 층간절연막을 선택적으로 식각하여 복수 개의 콘택홀을 형성하는 단계; 기판 전면에 제1금속층을 형성하는 단계; 상기 제1금속층상에 제1절연막을 형성하는 단계; 상기 제1절연막과 제1금속층을 소정패턴으로 패터닝하여 제1금속배선을 형성하는 단계; 상기 제1금속배선의 노출된 표면에만 제2절연막을 형성하는 단계; 기판 전면에 제2금속층을 형성하는 단계; 및 상기 제2금속층을 상기 제1금속배선 상부의 제1절연막이 노출되도록 화학적 기계 연마하여 제2금속배선을 형성하는 단계로 이루어지는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.Forming an interlayer insulating film on the semiconductor substrate; Selectively etching the interlayer insulating film to form a plurality of contact holes; Forming a first metal layer on the entire surface of the substrate; Forming a first insulating film on the first metal layer; Patterning the first insulating layer and the first metal layer in a predetermined pattern to form a first metal wiring; Forming a second insulating film only on the exposed surface of the first metal wiring; Forming a second metal layer on the entire surface of the substrate; And chemically mechanically polishing the second metal layer to expose the first insulating layer on the first metal wiring to form a second metal wiring. 제3항에 있어서, 상기 제1금속층 및 제2금속층은 Al으로 형성하는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.The method of manufacturing a multilayer wiring structure of a semiconductor device according to claim 3, wherein said first metal layer and said second metal layer are formed of Al. 제3항에 있어서, 상기 제1절연막 및 제2절연막은 Al2O3로 형성하는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.The method of manufacturing a multilayer wiring structure of a semiconductor device according to claim 3, wherein said first insulating film and said second insulating film are formed of Al 2 O 3 . 제3항에 있어서, 상기 제1절연막은 상기 제1금속층이 형성된 기판을 뜨거운 순수에 린스함으로써 성장시키는 자연산화막으로 형성하는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.The method of manufacturing a multilayer wiring structure of a semiconductor device according to claim 3, wherein said first insulating film is formed of a natural oxide film grown by rinsing a substrate on which said first metal layer is formed with hot pure water. 제3항에 있어서, 상기 제1절연막은 200-800Å 두께로 형성하는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.The method of manufacturing a multilayer wiring structure of a semiconductor device according to claim 3, wherein said first insulating film is formed to a thickness of 200-800 Å. 제3항에 있어서, 상기 제2절연막은 양극산화방식으로 형성하는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.The method for manufacturing a multilayer wiring structure of a semiconductor device according to claim 3, wherein said second insulating film is formed by anodizing. 제3항에 있어서, 상기 제2절연막은 200-1500Å 두께로 형성하는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.The method of manufacturing a multilayer wiring structure of a semiconductor device according to claim 3, wherein said second insulating film is formed to a thickness of 200-1500 Å. 제3항에 있어서, 상기 제1금속배선은 상기 복수 개의 콘택홀 상에 형성하되, 콘택홀을 하나씩 건너뛰어 형성되도록 하는 것을 특징으로 하는 반도체 장치의 다층 배선구조의 제조방법.The method of claim 3, wherein the first metal wiring is formed on the plurality of contact holes, and the contact holes are formed by skipping the contact holes one by one.
KR1019950046087A 1995-12-01 1995-12-01 Multi-layer interconnection structure of semiconductor device and method for manufacturing thereof KR0179707B1 (en)

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