KR0137566B1 - Contact hole formation method of semiconductor device - Google Patents

Abstract

The present invention comprises the steps of forming a predetermined pattern including a conductive layer (2) on the semiconductor substrate 20; Forming a first insulating layer 3 on the entire structure; Forming a predetermined layer (4) on the surface of the first insulating layer (3), the etching ratio being different from that of the second insulating layer (5) to be formed later; Forming a second insulating layer (5) on the predetermined layer (4) and then removing the second insulating layer (5) at a predetermined site; Removing the exposed predetermined layer (4), and then forming a spacer insulating layer (6) over the entire structure; And a sixth step of sequentially removing the predetermined portions of the spacer insulating layer 6 and the first insulating layer 3 until the semiconductor substrate 20 is exposed. Insulation between the lower wiring structure and the polysilicon pad layer and contact hole formation to a certain extent or less than the limit of the exposure equipment can be performed by symmetry and automatic alignment of the contact holes. It relates to a method for forming a contact hole of a semiconductor device having a unique effect capable of forming a.

Description

Contact hole formation method of semiconductor device

1A through 1F are cross-sectional views of a process for forming an automatic alignment contact hole according to an embodiment of the present invention;

2A to 2D are cross-sectional views of an automatic alignment contact hole forming process when misalignment occurs in one embodiment of the present invention;

3A to 3B are cross-sectional views of a process for forming an automatic alignment contact hole according to another embodiment of the present invention;

4A to 4B are cross-sectional views of an automatic alignment contact hole formation process when misalignment occurs in another embodiment of the present invention.

* Description of the symbols for the main parts of the drawings *

1: gate oxide layer

2: gate electrode

3; First insulating layer

4: polysilicon pad layer

5: second insulating layer

6: spacer insulation layer

20: silicon substrate

The present invention relates to a method for forming a contact hole in a semiconductor device.

In general, as the degree of integration of semiconductor devices including DRAMs (Dynamic Randon Access Memory (DRAM)) increases, the size of the contact itself connecting upper and lower wirings and capacitors, and the distance between peripheral wirings are reduced.

Therefore, in order to form a contact in a semiconductor device having a multi-layered conductive line, accurate and strict alignment is required in the manufacturing process, thereby reducing process margin. In addition, the reduction of the contact hole size requires a high precision of the semiconductor manufacturing equipment, it is very difficult to form a micropattern of a certain size or less, for example, 0.4㎛ or less with current equipment.

When designing to maintain the contact hole spacing, the gate mask and the contact mask follow certain design rules, and the following factors should be considered.

First, msialignment tolerance in mask alignment

Second, lens distortion during the exposure process

Fourth, critical dimension variation during mask fabrication and photolithography process

Fourth, registration between masks

Therefore, in consideration of the various matters described above, the size and spacing of the contact hole itself are widened, making it difficult to integrate the device. In the conventional method of forming a contact hole in a semiconductor device, a contact hole is formed by removing an insulating layer on a portion, which is intended as a contact of a semiconductor substrate, by a dry or wet etching method. However, in order to form the contact of the upper conductor pattern between the lower conductor patterns, the distance between the contact hole and the lower conductor pattern should be maintained at a predetermined level or more. Spacer or sidewall oxide layers are formed to ensure.

As a result, the conventional method for forming a contact hole as described above has a problem that the formation process is complicated, the process margin is small, and the etching damage is increased by exposing the silicon substrate several times during the etching process, resulting in a decrease in reliability and process yield of device operation. did.

Accordingly, the present invention is to solve the problems as described above, that is, the insulation of the lower wiring structure and the polysilicon pad layer on the upper portion of the lower wiring structure and the symmetry and automatic alignment of the contact hole can be performed even to some extent misalignment. It is an object of the present invention to provide a method for forming a contact hole in a semiconductor device.

In order to achieve the above object, the present invention provides a method for forming a contact hole in a semiconductor device, the method comprising: forming a predetermined pattern including a conductive layer on a semiconductor substrate; Forming a first insulating layer on the entire structure; Forming a predetermined layer on the surface of the first insulating layer, the predetermined layer having a different etching ratio from the second insulating layer to be formed later; Forming a second insulating layer on the predetermined layer, and then removing a second insulating layer of a predetermined site; A fifth step of forming a spacer insulating layer on the entire structure after removing the exposed predetermined layer; And a sixth step of sequentially removing the predetermined portions of the spacer insulating layer and the first insulating layer until the semiconductor substrate is exposed.

In addition, the present invention provides a method for forming a contact hole in a semiconductor device, the method comprising: forming a predetermined pattern including a conductive layer on a semiconductor substrate; Forming a first insulating layer on the entire structure; Forming a predetermined layer on the surface of the first insulating layer, the predetermined layer having a different etching ratio from the second insulating layer to be formed later; Forming a second insulating layer on the predetermined layer, and then removing a second insulating layer of a predetermined site; Removing the exposed predetermined layer, and then removing the first insulating layer until the semiconductor substrate is exposed; A sixth step of forming a spacer insulating layer over the entire structure; And a seventh step of sequentially removing the predetermined area of the sound spacer insulating layer and the first insulating layer until the semiconductor substrate is exposed.

Hereinafter, the method will be described in detail with reference to FIGS. 1A to 4B attached to a method for forming an automatic alignment contact hole for a semiconductor device according to the present invention.

First, an embodiment shown in FIGS. 1A to 2D will be described.

1A through 1F are cross-sectional views of a process for forming a contact hole of a semiconductor device according to an embodiment of the present invention.

As shown in FIG. 1A, a gate oxide layer 1 and a gate electrode 2 having a lower wiring structure are formed on the silicon substrate 20.

Subsequently, as shown in FIG. 1B, the first insulating layer 3, the polysilicon pad layer 4, and the second insulating layer 5 are sequentially deposited on the entire structure. Here, the polysilicon pad layer 4 is a material different in etching ratio from the first and second insulating layers 3 and 5, and may include various kinds of materials. An important point is the first and second insulating layers. If the difference between the etching rate and any other question can be replaced.

Subsequently, as shown in FIG. 1C, the second insulating layer 5 in the portion that is intended to be a contact hole is etched by a masking operation to expose the lower polycrystalline silicon pad layer 4.

Next, as shown in FIG. 1D, the exposed polysilicon pad layer 4 is removed by a dry or wet etching method, and as shown in FIG. 1E, the lower wiring structure, the upper wiring structure, and the polycrystal are disposed on the entire structure. A spacer insulating layer 6 is deposited to insulate the silicon pad layer 4 and the upper wiring structure.

Finally, as shown in FIG. 1F, the spacer insulating layer 6 and the first insulating layer 3 are anisotropically etched until the silicon substrate 20 is exposed to form a contact hole under the structure of FIG. 1E.

2A to 2D illustrate an embodiment of implementing an automatic alignment contact hole when a certain amount of misalignment occurs during a mask operation during contact hole formation according to an embodiment of the present invention.

First, FIG. 2A is a state in which the second polysilicon pad layer 4 is exposed by etching the second insulating layer 5 when some misalignment occurs in the contact hole mask operation under the structure of FIG. 1B. 2b is a state in which the first insulating layer 3 is exposed by removing the polysilicon pad layer 4 under the structure of FIG. 2a. FIG. 2C is a cross-sectional view of the spacer wiring layer 6 formed for the purpose of insulating the lower wiring structure, the upper wiring structure, and the polysilicon pad layer and the upper wiring structure under the structure of FIG. 2B. 2C is a cross-sectional view of the spacer insulation layer 6 and the first insulation layer 3 under anisotropic etching to form a contact hole until the silicon substrate 20 is exposed.

Here, as illustrated in FIGS. 2A to 2D, a contact hole capable of sufficiently performing the function may be formed even when some misalignment occurs when forming the contact hole according to an embodiment of the present invention. Is easy to see.

Another embodiment of the present invention will be described in detail with reference to FIGS. 3A-4B.

First, another embodiment of the present invention proceeds the same from the above embodiment to the process shown in FIGS. 1a to 1d.

Subsequently, as shown in FIG. 3A, under the structure of FIG. 1D, the first insulating layer 3 is etched until the silicon substrate 20 is exposed.

Subsequently, as shown in FIG. 3B, the spacer insulating layer 6 is formed of a silicon substrate (B) to insulate the lower wiring structure, the upper wiring structure, and the polysilicon pad layer 4 and the upper wiring structure under the structure of FIG. Deposition and anisotropically etch until 20) is exposed to form an auto-aligned contact hole.

Herein, a case in which misalignment occurs during mask operation during contact hole formation according to another embodiment of the present invention will be described with reference to FIGS. 4A to 4B.

First, FIG. 4A is a cross-sectional view of the first insulating layer 3 being etched until the silicon substrate 20 is exposed under the structure of FIG. 1D. FIG. 4B is a lower wiring structure and an upper portion under the structure of FIG. 4A. A cross-sectional view of a spacer structure layer 6 is deposited until the silicon substrate 20 is exposed and anisotropically etched to form an auto-aligned contact hole for the wiring structure and the insulation between the polysilicon pad layer 4 and the upper wiring structure. In this figure, it can be easily seen that a contact hole capable of sufficiently performing the function may be easily formed even when some misalignment occurs when forming the contact hole according to another embodiment of the present invention.

The present invention made as described above can perform the symmetry and automatic alignment of the contact holes in the insulation of the lower wiring structure and the polysilicon pad layer on the upper portion of the lower wiring structure and the formation of contact holes below the limit size of the exposure equipment to some extent. In addition, there is a unique effect of forming a contact hole of a micro device even with a single mask operation.

Claims (7)

In the contact hole forming method of a semiconductor device, Forming a predetermined pattern including a conductive layer on the semiconductor substrate; Forming a first insulating layer on the entire structure; Forming a predetermined layer on the surface of the first insulating layer, the predetermined layer having a different etching ratio from the second insulating layer to be formed later; Forming a second insulating layer on the predetermined layer, and then removing a second insulating layer of a predetermined site; A fifth step of forming a spacer insulating layer on the entire structure after removing the exposed predetermined layer; And removing a predetermined portion of the spacer insulating layer and the first insulating layer sequentially until the semiconductor substrate is exposed. The method of claim 1, The fourth step, And forming a second insulating layer on the predetermined layer, and then removing the second insulating layer of a predetermined portion by using an etching ratio with the predetermined layer. The method of claim 1, The sixth step, And removing the spacer insulation layer and the first insulation layer by sequentially anisotropic etching until the semiconductor substrate is exposed. The method of claim 1, The predetermined layer, A method for forming a contact hole in a semiconductor device comprising a polysilicon pad layer. A contact hole forming method of a semiconductor device, comprising: a first step of forming a predetermined pattern including a conductive layer on a semiconductor substrate; Forming a first insulating layer on the entire structure; Forming a predetermined layer on the surface of the first insulating layer, the predetermined layer having a different etching ratio from the second insulating layer to be formed later; Forming a second insulating layer on the predetermined layer, and then removing a second insulating layer of a predetermined site; A fifth step of removing the exposed predetermined layer and then removing the first insulating layer until the semiconductor substrate is exposed; A sixth step of forming a spacer insulating layer over the entire structure; And removing a predetermined portion of the spacer insulating layer and the first insulating layer sequentially until the semiconductor substrate is exposed. The method of claim 5, The fourth step, And forming a second insulating layer on the predetermined layer, and then removing the second insulating layer of a predetermined portion by using an etching ratio with the predetermined layer. The method of claim 5, The predetermined layer, A method for forming a contact hole in a semiconductor device comprising a polysilicon pad layer.