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JPH0551892B2 - - Google Patents

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Publication number
JPH0551892B2
JPH0551892B2 JP26093987A JP26093987A JPH0551892B2 JP H0551892 B2 JPH0551892 B2 JP H0551892B2 JP 26093987 A JP26093987 A JP 26093987A JP 26093987 A JP26093987 A JP 26093987A JP H0551892 B2 JPH0551892 B2 JP H0551892B2
Authority
JP
Japan
Prior art keywords
film
cross
photoresist
photomask
light shielding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP26093987A
Other languages
Japanese (ja)
Other versions
JPH01102464A (en
Inventor
Toshimitsu Kamitaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Kyushu Ltd
Original Assignee
NEC Kyushu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Kyushu Ltd filed Critical NEC Kyushu Ltd
Priority to JP62260939A priority Critical patent/JPH01102464A/en
Publication of JPH01102464A publication Critical patent/JPH01102464A/en
Publication of JPH0551892B2 publication Critical patent/JPH0551892B2/ja
Granted legal-status Critical Current

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  • Preparing Plates And Mask In Photomechanical Process (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置製造におけるフオトレジス
トパターンの形成に用いられるフオトマスクに関
する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a photomask used for forming a photoresist pattern in semiconductor device manufacturing.

〔従来の技術〕[Conventional technology]

従来、半導体装置の製造に用いられるフオトマ
スクは、第4図に示すように、平らなガラス基板
1Aとその表面に形成された金属膜や金属酸化膜
等からなる遮光膜2とから構成されていた。
Conventionally, a photomask used in the manufacture of semiconductor devices, as shown in FIG. 4, has been composed of a flat glass substrate 1A and a light shielding film 2 made of a metal film, metal oxide film, etc. formed on the surface of the glass substrate 1A. .

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来のフオトマスクは、ガラス基板1
Aが平らであるため、このフオトマスクを用い半
導体基板上のフオトレジスト膜を露光し現像した
場合、形成されるフオトレジスタのパターンの断
面形状は全て同一となる。従つて、このようにし
て形成されたフオトレジストのパターンをマスク
とし導体膜や絶縁膜をエツチングした場合、その
断面(エツチング面形状は全て同一となつてい
た。
The conventional photomask described above has a glass substrate 1
Since A is flat, when a photoresist film on a semiconductor substrate is exposed and developed using this photomask, the cross-sectional shapes of the photoresist patterns formed will all be the same. Therefore, when a conductive film or an insulating film is etched using the photoresist pattern thus formed as a mask, the cross-sections (etched surface shapes) are all the same.

しかしながら、たとえば、金属配線をゲート電
極として用いる場合、金属配線の断面形状はでき
るだけ急峻な段である事がMOSトランジスタの
特性の安定化にとつては望ましい。一方、単に金
属配線として用いる場合は、その断面形状が急峻
な段となると、その上部に形成される金属配線が
その段部で断線しやすくなる為、下層の金属配線
の断面形状は、できるだけ、ゆるいテーパーを持
つ構造である事が望ましい。
However, for example, when a metal wiring is used as a gate electrode, it is desirable for the cross-sectional shape of the metal wiring to have as steep a step as possible in order to stabilize the characteristics of the MOS transistor. On the other hand, when using the metal wiring simply as a metal wiring, if the cross-sectional shape becomes a steep step, the metal wiring formed on the upper layer is likely to break at that step. It is desirable that the structure has a gentle taper.

この二つの金属配線構造を形成する為には、従
来のフオトマスクを用いた方法では、工程が長く
なるという問題点があつた。
In order to form these two metal wiring structures, the conventional method using a photomask has the problem of requiring a long process.

〔問題点を解決するための手段〕[Means for solving problems]

本発明のフオトマスクは、透明基板の一面に段
差のある領域の溝部を設け、前記透明基板の一面
の前記溝部を除く表面に電極形成用の遮光膜を形
成し、前記透明基板の溝部の表面に配線形成用の
遮光膜を形成したものである。
In the photomask of the present invention, a groove in a stepped area is provided on one surface of the transparent substrate, a light-shielding film for forming an electrode is formed on the surface of the one surface of the transparent substrate excluding the groove, and a light-shielding film for forming an electrode is formed on the surface of the groove of the transparent substrate. A light shielding film for forming wiring is formed.

実施例 次に、本発明の実施例について図面を参照して
説明する。
Embodiments Next, embodiments of the present invention will be described with reference to the drawings.

第1図は本発明の一実施例の断面図である。 FIG. 1 is a sectional view of an embodiment of the present invention.

第1図において、フオトマスク10はガラス基
板1とその表面に形成されたクロム等からなる遮
光膜2A,2Bとから構成されているが、特にこ
のガラス基板1には段差3が設けられている。こ
の段差は、例えばフオトレジストをマスクとしガ
ラス基板1をエツチングすることより容易に形成
できる。
In FIG. 1, a photomask 10 is composed of a glass substrate 1 and light shielding films 2A and 2B made of chromium or the like formed on the surface of the glass substrate 1. In particular, the glass substrate 1 is provided with a step 3. This step can be easily formed by etching the glass substrate 1 using, for example, a photoresist as a mask.

このように構成された本実施例を用い、半導体
基板上にフオトレジストをパターンを形成するた
めに露光装置によつて焼き付け転写を行なう場
合、焦点深度の差によつて、焦点の合つた部分
と、焦点のずれた部分とが生じ、その結果、半導
体基板上に形成されるフオトレジストパターンの
断面形状、及び膜厚に差が生ずる。従つてこのフ
オトレジスト材料をエツチングする場合、その断
面形状に差が生じ、目的に応じた断面形状を一度
の焼き付け転写によつて形成する事ができる。
When using this embodiment configured in this manner and performing printing transfer using an exposure device to form a photoresist pattern on a semiconductor substrate, the difference in depth of focus causes the in-focus area to , out-of-focus portions occur, and as a result, differences occur in the cross-sectional shape and film thickness of the photoresist pattern formed on the semiconductor substrate. Therefore, when this photoresist material is etched, a difference occurs in its cross-sectional shape, and a cross-sectional shape depending on the purpose can be formed by one-time printing and transfer.

以下、本実施例を用い、多結晶シリコン膜をエ
ツチングする場合について第2図を用いて説明す
る。
Hereinafter, the case of etching a polycrystalline silicon film using this embodiment will be explained with reference to FIG.

まず第2図aに示すように、表面にSiO2等か
らなる絶縁膜12、多結晶シリコン膜11及びポ
ジ型のフオトレジスト膜14が形成された半導体
基板13上に、遮光膜2A,2Bからなるパター
ンが形成された本実施例のフオトマスク10を配
置し、その上から紫外線15を照射し、フオトレ
ジスト膜14を露光する。この時遮光膜2Bの方
が遮光膜2Aのより焦点が合つているとする。
First, as shown in FIG. 2a, a semiconductor substrate 13 on which an insulating film 12 made of SiO 2 or the like, a polycrystalline silicon film 11, and a positive photoresist film 14 are formed is coated with light-shielding films 2A and 2B. The photomask 10 of this embodiment having a pattern formed thereon is placed, and ultraviolet rays 15 are irradiated from above to expose the photoresist film 14. At this time, it is assumed that the light shielding film 2B is more focused than the light shielding film 2A.

次に第2図bに示すように、現像処理を行うと
遮光膜2B下のフオトレジスト膜14Aには遮光
膜2Bのパターンが正確に転写され、その断面は
急峻な形状を示す。一方遮光膜2A下のフオトレ
ジスト膜14Bにはその断面形状にゆるやかなテ
ーパーが形成される。
Next, as shown in FIG. 2B, when a development process is performed, the pattern of the light shielding film 2B is accurately transferred to the photoresist film 14A under the light shielding film 2B, and its cross section shows a steep shape. On the other hand, a gentle taper is formed in the cross-sectional shape of the photoresist film 14B under the light shielding film 2A.

次に第2図cに示すように、フオトレジスト膜
14A,14Bをマスクとして異方性エツチング
法により多結晶シリコン膜11をエツチングす
る。このエツチングによりフオトレジスト膜14
A下の多結晶シリコン膜11Aの断面形状は急峻
になるが、フオトレジスト膜14B下の多結晶シ
リコン膜11Bにはテーパーが形成されることに
なる。
Next, as shown in FIG. 2c, polycrystalline silicon film 11 is etched by anisotropic etching using photoresist films 14A and 14B as masks. By this etching, the photoresist film 14
The cross-sectional shape of the polycrystalline silicon film 11A under A becomes steep, but a taper is formed in the polycrystalline silicon film 11B under the photoresist film 14B.

第3図a,bは上記実施例のフオトマスクを用
いて多結晶シリコン膜をエツチングし、
MOSFETのゲート電極20と配線21を形成し
た場合の断面図である。
FIGS. 3a and 3b show etching of a polycrystalline silicon film using the photomask of the above embodiment,
FIG. 2 is a cross-sectional view of a MOSFET when a gate electrode 20 and wiring 21 are formed.

MOSFETのゲート電極はチヤネル長の安定性
を得る為には、できるだけその断面形状は、テー
パーがつていない事が望ましい。一方、その他の
配線部分に用いる場合は上層部の他の金属配線の
断線を防止し、かつ、表面保護膜及び層間絶縁膜
のステツプカバレージの状態を良くする為には、
その断面形状はテーパーができるだけついている
方が望ましい。
In order to obtain stability of the channel length of the gate electrode of a MOSFET, it is desirable that its cross-sectional shape is as untapered as possible. On the other hand, when using it for other wiring parts, in order to prevent disconnection of other metal wiring in the upper layer and to improve the step coverage of the surface protection film and interlayer insulation film,
It is desirable that the cross-sectional shape be as tapered as possible.

本実施例を用いることにより第3図a,bに示
したように、急峻な断面形状を有するゲート電極
20とテーパーを有する配線21を容易に形成で
きる。
By using this embodiment, as shown in FIGS. 3a and 3b, the gate electrode 20 having a steep cross-sectional shape and the tapered wiring 21 can be easily formed.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、フオトマスクを
構成する透明基板に段差を設けることによりパタ
ーニングされたフオトレジスト膜からなるマスク
の断面形状を異なつたものとすることができるた
め、このマスクを用いて断面形状の異つた電極、
配線等を半導体基板上に容易に形成できる効果が
ある。
As explained above, in the present invention, the cross-sectional shape of the mask made of a patterned photoresist film can be made different by providing steps on the transparent substrate constituting the photomask. electrodes of different shapes,
This has the effect that wiring and the like can be easily formed on a semiconductor substrate.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例の断面図、第2図a
〜cは本発明の一実施例を多結晶シリコンのパタ
ーニングに適用した場合を説明するための半導体
チツプの断面図、第3図a,bは本発明の一実施
例をMOSFETの製造に適用した場合を説明する
ための断面図、第4図は従来のフオトマスクの断
面図である。 1,1A…ガラス基板、2,2A,2B…遮光
膜、3…段差、10…フオトマスク、11,11
A,11B…多結晶シリコン膜、12…絶縁膜、
13…半導体基板、14,14A,14B…フオ
トレジスト膜、15…紫外線、20…ゲート電
極、21…配線。
Fig. 1 is a sectional view of an embodiment of the present invention, Fig. 2a
-c are cross-sectional views of a semiconductor chip for explaining the case where an embodiment of the present invention is applied to patterning of polycrystalline silicon, and Figures 3a and 3b are cross-sectional views of a semiconductor chip in which an embodiment of the present invention is applied to the manufacture of MOSFET. A cross-sectional view for explaining the case, FIG. 4 is a cross-sectional view of a conventional photomask. 1, 1A... Glass substrate, 2, 2A, 2B... Light shielding film, 3... Step, 10... Photomask, 11, 11
A, 11B... polycrystalline silicon film, 12... insulating film,
13... Semiconductor substrate, 14, 14A, 14B... Photoresist film, 15... Ultraviolet rays, 20... Gate electrode, 21... Wiring.

Claims (1)

【特許請求の範囲】[Claims] 1 透明基板の一面に段差のある領域の溝部を設
け、前記透明基板の一面の前記溝部を除く表面に
電極形成用の遮光膜を形成し、前記透明基板の溝
部の表面に配線形成用の遮光膜を形成したことを
特徴とするフオトマスク。
1. A groove in a stepped area is provided on one surface of the transparent substrate, a light shielding film for electrode formation is formed on the surface of the one surface of the transparent substrate excluding the groove, and a light shielding film for forming wiring is formed on the surface of the groove of the transparent substrate. A photomask characterized by forming a film.
JP62260939A 1987-10-15 1987-10-15 Photomask Granted JPH01102464A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62260939A JPH01102464A (en) 1987-10-15 1987-10-15 Photomask

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62260939A JPH01102464A (en) 1987-10-15 1987-10-15 Photomask

Publications (2)

Publication Number Publication Date
JPH01102464A JPH01102464A (en) 1989-04-20
JPH0551892B2 true JPH0551892B2 (en) 1993-08-03

Family

ID=17354875

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62260939A Granted JPH01102464A (en) 1987-10-15 1987-10-15 Photomask

Country Status (1)

Country Link
JP (1) JPH01102464A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0592295U (en) * 1992-05-15 1993-12-17 淑朗 矢田貝 Forklets for cargo handling and forklift pawls

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100347541B1 (en) * 1999-12-23 2002-08-07 주식회사 하이닉스반도체 Reticle for manufacturing a semiconductor device

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5379387A (en) * 1976-12-23 1978-07-13 Nec Corp Optical mask

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5379387A (en) * 1976-12-23 1978-07-13 Nec Corp Optical mask

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0592295U (en) * 1992-05-15 1993-12-17 淑朗 矢田貝 Forklets for cargo handling and forklift pawls

Also Published As

Publication number Publication date
JPH01102464A (en) 1989-04-20

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