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JPS63207164A - Thin-film resistor device - Google Patents

Thin-film resistor device

Info

Publication number
JPS63207164A
JPS63207164A JP62039287A JP3928787A JPS63207164A JP S63207164 A JPS63207164 A JP S63207164A JP 62039287 A JP62039287 A JP 62039287A JP 3928787 A JP3928787 A JP 3928787A JP S63207164 A JPS63207164 A JP S63207164A
Authority
JP
Japan
Prior art keywords
resistance
resistor
low
layer
thin film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62039287A
Other languages
Japanese (ja)
Inventor
Makio Iida
飯田 真喜男
Toshio Sonobe
園部 俊夫
Susumu Sugiyama
進 杉山
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denso Corp
Toyota Central R&D Labs Inc
Original Assignee
Toyota Central R&D Labs Inc
NipponDenso Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Central R&D Labs Inc, NipponDenso Co Ltd filed Critical Toyota Central R&D Labs Inc
Priority to JP62039287A priority Critical patent/JPS63207164A/en
Publication of JPS63207164A publication Critical patent/JPS63207164A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D88/00Three-dimensional [3D] integrated devices

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To inhibit the increase of, a resistor-pattern area or a chip area by forming a resistance element by a thin-film low resistor, in which a high resistance layer having high sheet resistance is arranged onto a resistance layer having low sheet resistance, and a thin-film high resistor consisting of the high resistance layer having high sheet resistance. CONSTITUTION:A resistance element is shaped by a thin-film low resistor A formed by disposing a high resistance layer 9 having high sheet resistance onto a resistance layer 8 having low sheet resistance and a thin-film high resistor B composed of the high resistance layer 9 having high sheet resistance. When the fundamental constitution is realized by the change of film thickness, resistor pattern shapes can be reduced in both a high resistance section and a low resistance section because the high resistance section is shaped in thin-film thickness and the low resistance section in thick film thickness, and an addition process by the formation, etc., of an interlayer insulating layer is removed because the low resistance section is formed in constitution in which only thick films and thin films are superposed continuously, thus largely simplifying processes.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は薄膜抵抗体装置に関するものであり、特に半導
体集積回路チップ上に薄膜抵抗体を形成した薄膜抵抗体
装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a thin film resistor device, and more particularly to a thin film resistor device in which a thin film resistor is formed on a semiconductor integrated circuit chip.

〔従来の技術〕[Conventional technology]

一般に、薄膜抵抗体はNiCrあるいはTa2N等を用
い、半導体基板上に設けられた酸化膜上に蒸着あるいは
スパッタリング法にて、所定のシート抵抗値となるよう
に単層膜として形成する。また、カーボン薄膜抵抗も公
知である(特開昭61−4270号公報参照)。半導体
集積回路デバイスでは通常複数の抵抗値をもつ複数の抵
抗素子を必要とするため、従来法では、NiCr等を蒸
着等で基板全面に形成後引き続いて所望の抵抗値となる
ように種々の長さおよび幅のパターン形状にエソチッグ
し、その後同−基板内の能動素子部等との間を配線して
いる。
In general, a thin film resistor is formed as a single layer film using NiCr, Ta2N, or the like by vapor deposition or sputtering on an oxide film provided on a semiconductor substrate so as to have a predetermined sheet resistance value. Carbon thin film resistors are also known (see Japanese Patent Laid-Open No. 61-4270). Semiconductor integrated circuit devices usually require multiple resistance elements with multiple resistance values, so in the conventional method, NiCr or the like is formed on the entire surface of the substrate by vapor deposition or the like, and then various lengths are deposited to obtain the desired resistance value. After etching is performed to form a pattern with a certain height and width, wiring is then performed between the active element portion and the like within the same substrate.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

しかし、上記従来法に依れば、薄膜抵抗体のシート抵抗
値が一種類となるため、必要とする抵抗体の抵抗値に依
っては抵抗体パターン面積が広(なり、チップ面積が拡
大して、歩留りの低下やコスト増加を招くという問題点
がある。
However, according to the above conventional method, the sheet resistance of the thin film resistor is one type, so depending on the resistance value of the resistor required, the resistor pattern area becomes large (and the chip area increases). However, there is a problem in that it causes a decrease in yield and an increase in cost.

本発明は異なるシート抵抗値を有する薄膜抵抗素子を半
導体集積回路のチップ上に形成する際の上記問題点に鑑
みてなされたもので、抵抗体パターン面積あるいはチッ
プ面積の著しい増大を抑制することができる薄膜抵抗体
装置を提供するものである。
The present invention has been made in view of the above-mentioned problems when forming thin film resistive elements having different sheet resistance values on a semiconductor integrated circuit chip, and is capable of suppressing a significant increase in the resistor pattern area or chip area. The present invention provides a thin film resistor device that can be used.

〔問題点を解決するための手段〕[Means for solving problems]

本発明の薄膜抵抗体装置は、能動素子領域を形成した半
導体基板の主面に形成された絶縁膜上に異なる抵抗値を
有する薄膜抵抗素子を形成してなる薄膜抵抗体装置にお
いて、シート抵抗が低い抵抗層上にシート抵抗が高い高
抵抗層を配置してなる薄膜低抵抗体と、前記シート抵抗
が高い高抵抗層よりなる薄膜抵抗体とにより、前記抵抗
素子を形成してなることを特徴とする。
The thin film resistor device of the present invention is a thin film resistor device in which thin film resistor elements having different resistance values are formed on an insulating film formed on the main surface of a semiconductor substrate in which an active element region is formed. The resistor element is formed by a thin film low resistance element formed by disposing a high resistance layer having a high sheet resistance on a low resistance layer, and a thin film resistor formed by the high resistance layer having a high sheet resistance. shall be.

以下、本発明の詳細な説明する。一般に、薄膜の抵抗値
(すなわちシート抵抗)は膜厚によって変化し、薄い膜
は高抵抗に、厚い膜は低抵抗になる。また薄膜のシート
抵抗は構成物質の比抵抗によっても変わる。本発明は、
このようなシート抵抗の性質を利用するとともに、同一
チップ上において、多層もしくは単層の層構造を変え、
かつ並列抵抗において抵抗値の差が大であるときは合成
抵抗はほぼ低抵抗体の抵抗値により定められるとの原理
を利用する。その基本的構成は、薄膜抵抗体については
、シート抵抗が低い抵抗層上にシート抵抗が高い抵抗層
を配置すると、並列抵抗が作られかつ前者の抵抗層によ
り抵抗がほぼ定められる所望の低抵抗値が得られ、一方
薄膜高低抵抗体については、前記シート抵抗が高い抵抗
層そのものを用いると、所望の抵抗値が得られるのみな
らず、全抵抗体が露出された時該高抵抗層がチップ上面
に露出され、低抵抗層はマスクされるために、チップ上
面全体を一つのマスクパターンでかつ1種のエッチラグ
剤でしかも同一エツチング時間でエツチングできること
となり、工程数の増加が避けられるとの利点が生じる。
The present invention will be explained in detail below. Generally, the resistance value (that is, sheet resistance) of a thin film changes depending on the film thickness, with a thin film having a high resistance and a thick film having a low resistance. The sheet resistance of a thin film also changes depending on the specific resistance of its constituent materials. The present invention
In addition to utilizing this property of sheet resistance, we can also change the multilayer or single layer structure on the same chip.
In addition, the principle that when the difference in resistance values of parallel resistances is large, the combined resistance is determined approximately by the resistance value of the low resistance element is used. Its basic structure is that, for thin film resistors, if a resistive layer with a high sheet resistance is placed on a resistive layer with a low sheet resistance, a parallel resistance is created and the desired low resistance is determined by the former resistive layer. On the other hand, for thin film high/low resistance elements, if the resistance layer itself with high sheet resistance is used, not only will the desired resistance value be obtained, but when the entire resistor is exposed, the high resistance layer will remain on the chip. Since the low resistance layer is exposed on the top surface and is masked, the entire top surface of the chip can be etched with one mask pattern and one type of etch lag agent in the same etching time, which has the advantage of avoiding an increase in the number of steps. occurs.

上記基本的構成を膜厚変化により実現すれば、高抵抗部
位は薄い膜厚、低抵抗部位は厚い膜厚となっているため
、両者とも抵抗体パターン形状を小さくでき、また低抵
抗部位は厚い膜と薄い膜とを連続的に積み重ねたのみの
構成となっているため、層間絶縁層の形成などによる附
加工程がなく、工程が大巾に簡略化できる。
If the above basic configuration is realized by changing the film thickness, the film thickness will be thinner in the high resistance part and thicker in the low resistance part, so the shape of the resistor pattern can be made smaller in both cases, and the shape of the resistor pattern can be made smaller in both areas. Since it has a structure in which only films and thin films are successively stacked, there is no additional processing step such as forming an interlayer insulating layer, and the process can be greatly simplified.

また上記基本的構成を物質の相違により実現すれば、低
シート抵抗層に積み重ねられる高シート抵抗層の厚さは
任意になる。
Furthermore, if the above basic configuration is realized by using different materials, the thickness of the high sheet resistance layer stacked on the low sheet resistance layer can be arbitrary.

さらに、材質と膜厚変化を同時に行なって本発明の基本
構成を実現することもできる。その例を第1図に示す。
Furthermore, the basic configuration of the present invention can be realized by simultaneously changing the material and film thickness. An example is shown in FIG.

すなわち、能動素子領域等を形成した半導体基板1の主
面上に絶縁膜2を形成し、その上にTa2N等の第1の
抵抗層3を低抵抗形成部位に厚い膜厚で形成し、次いで
全面に前記第1の抵抗層3と異なる組成の5iCr等の
第2の抵抗層4を薄い膜厚で形成し、引き続いて高抵抗
形成部位と前記低抵抗形成部位を除く領域の第2の抵抗
層4をエツチング除去し、必要な配線・電極5をA1等
により形成する。
That is, an insulating film 2 is formed on the main surface of a semiconductor substrate 1 on which an active element region etc. are formed, a first resistance layer 3 of Ta2N or the like is formed thereon with a large thickness in a low resistance formation region, and then A second resistance layer 4 made of 5iCr or the like having a composition different from that of the first resistance layer 3 is formed on the entire surface with a thin film thickness, and then a second resistance layer 4 is formed on the entire surface except for the high resistance formation area and the low resistance formation area. The layer 4 is removed by etching, and necessary wiring/electrodes 5 are formed using A1 or the like.

上記では、(al一層の高抵抗体と、二層の低抵抗体の
例を説明したが、(bl高抵抗体が1層で低抵抗体が3
層以上の構成も可能である。かかる構成(blは構成(
alに比べて工程が長くなるが、抵抗体パターン面積を
極めて小さくする利点がある。なお、同一チップ上で(
at、 (blの構成を場所的に区別して実施すること
により、抵抗値は異なるが、面積が極めて小さくかつほ
ぼ同じ薄膜抵抗をチップ上に多数整然と配列することも
できよう。
In the above, an example of a high-resistance material with one layer of (al) and a low-resistance material with two layers was explained;
A configuration with more than one layer is also possible. Such a configuration (bl is the configuration (
Although the process is longer than Al, it has the advantage of making the resistor pattern area extremely small. In addition, on the same chip (
By implementing the configuration of at, (bl in different locations, it would be possible to orderly arrange a large number of thin film resistors with different resistance values, but with extremely small areas and approximately the same size, on a chip.

以下、さらに好ましい実施例について本発明を説明する
The present invention will be described below with reference to more preferred embodiments.

〔実施例〕〔Example〕

本構成を用いMOSLSI上に薄膜抵抗を形成した実施
例を第2図ないし第6図に示す。第2図に示すように、
P型シリコン基板1に、P型チャネルストッパー2、L
OCO5酸化膜3、ゲート酸化膜4、Po1ySi配線
5、ソース及びドレインN型拡散層6゜「、BPSGリ
フロー膜7を通常のMO5LSIプロセスで形成した後
、Ta2Nを用い、シート抵抗が例えば110Ω/口と
低い低抵抗層8をBPSG リフロ−膜7上に形成する
。次に第3図のように、全面に、5iCrを用い、シー
ト抵抗が例えば1000Ω/口と大きい高抵抗薄膜抵抗
9をスパッタ法を用いて形成する。ホトエッチ技術を用
いて、第4図のように薄膜低抵抗Aおよび薄膜高抵抗B
を形成する。
Examples in which a thin film resistor is formed on a MOSLSI using this configuration are shown in FIGS. 2 to 6. As shown in Figure 2,
P-type silicon substrate 1, P-type channel stopper 2, L
After forming an OCO5 oxide film 3, a gate oxide film 4, a PolySi wiring 5, a source and drain N-type diffusion layer 6, and a BPSG reflow film 7 by a normal MO5LSI process, using Ta2N, the sheet resistance is, for example, 110Ω/hole. A low resistance layer 8 is formed on the BPSG reflow film 7. Next, as shown in FIG. Using photoetch technology, thin film low resistance A and thin film high resistance B are formed as shown in FIG.
form.

なお、この薄膜低抵抗Aの形成の際には、高抵抗層9の
パターンより広い低抵抗層8を第2図の段階で予め形成
し、第5図の段階で、高抵抗層9のパターンニング後該
抵抗層9をマスクにして低抵抗層80表出部を工・ノチ
ングにより除去すると、上下の抵抗層8.9が完全に重
畳した薄膜低抵抗体Aが得られる。しかしながら、下部
が広く上部が狭いあるいはこの逆の薄膜低抵抗体Aであ
っても本発明の効果が得られる。
Note that when forming this thin film low resistance A, the low resistance layer 8 which is wider than the pattern of the high resistance layer 9 is formed in advance in the step shown in FIG. 2, and the pattern of the high resistance layer 9 is changed in the step shown in FIG. After coating, the exposed portion of the low resistance layer 80 is removed by machining and notching using the resistance layer 9 as a mask, thereby obtaining a thin film low resistance element A in which the upper and lower resistance layers 8.9 are completely overlapped. However, the effects of the present invention can be obtained even if the thin film low resistance element A is wide at the bottom and narrow at the top, or vice versa.

また、第3図の段階において第7図に示す如きリフトオ
フプロセスを採用することもできる。すなわち、上記抵
抗層9に対してエツチングの選択性を有するマスク14
を抵抗9の非形成部に抵抗N9より厚く形成した後、全
面に抵抗層9の材料を被着し、マスクをエツチングによ
り除去すると第4図の構造が得られる。
Further, a lift-off process as shown in FIG. 7 can also be employed at the stage of FIG. 3. That is, the mask 14 has etching selectivity with respect to the resistive layer 9.
After forming resistor N9 to be thicker than resistor N9 in the area where resistor 9 is not formed, the material of resistor layer 9 is deposited on the entire surface and the mask is removed by etching to obtain the structure shown in FIG.

続いて、ソースドレーンのコンタクトホール11.11
’を形成すると第5図となり、A/配線12を形成する
ことにより第6図のように、2種類(100Ω/口、 
1000Ω/口)のシート抵抗の薄膜抵抗A、Bを集積
化したMO3LSIが形成できる。
Next, source drain contact holes 11.11
' is formed as shown in Fig. 5, and by forming the A/wiring 12, two types (100 Ω/hole,
An MO3LSI can be formed in which thin film resistors A and B with a sheet resistance of 1000Ω/unit are integrated.

前記実施例によれば、高抵抗部(8)はシート抵抗の高
い薄膜材料からなるため、パターン形状を小さくするこ
とができ、また低抵抗部(^)はシート抵抗の高い膜と
シート抵抗の低い膜とからなる並列抵抗体で構成されて
いるため、各々のシート抵抗値に大きな差をもたせれば
、はぼシート抵抗の低い膜と同じシート抵抗値となる。
According to the above embodiment, the high resistance part (8) is made of a thin film material with a high sheet resistance, so the pattern shape can be made small, and the low resistance part (8) is made of a film with a high sheet resistance and a thin film with a high sheet resistance. Since it is composed of a parallel resistor consisting of a film with a low sheet resistance, if there is a large difference in the sheet resistance values of each, the sheet resistance value will be the same as that of the film with a low sheet resistance.

たとえばR,= 110Ω/口、R,=1にΩ/口とす
れば、低抵抗部の合成シート抵抗は約100Ω/口とな
り、高抵抗部と同様に小さなパターン形状が得られる。
For example, if R,=110Ω/portion and R,=1 are set to Ω/portion, the combined sheet resistance of the low resistance part will be about 100Ω/portion, and a small pattern shape can be obtained like the high resistance part.

〔発明の効果〕〔Effect of the invention〕

本発明によると、薄膜抵抗の面積が小さくなり、これに
よりチップの面積が小さくなるとともに、薄膜抵抗形成
工程が簡単であるから、薄膜抵抗体装置の小型化とコス
トダウンが図られる。
According to the present invention, the area of the thin film resistor is reduced, thereby reducing the area of the chip, and the process of forming the thin film resistor is simple, so that the size and cost of the thin film resistor device can be reduced.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の薄膜抵抗体装置の一実施例を示す断面
図、 第2図ないし第7図は薄膜抵抗体装置の製造工程図であ
る。 l・・・P型シリコン基板、  8・・・低抵抗層、9
・・・高抵抗層。 第2図 第4図 第6図
FIG. 1 is a sectional view showing one embodiment of the thin film resistor device of the present invention, and FIGS. 2 to 7 are manufacturing process diagrams of the thin film resistor device. l...P-type silicon substrate, 8...low resistance layer, 9
...High resistance layer. Figure 2 Figure 4 Figure 6

Claims (1)

【特許請求の範囲】 1、能動素子領域を形成した半導体基板の主面に形成さ
れた絶縁膜上に異なる抵抗値を有する薄膜抵抗素子を形
成してなる薄膜抵抗体装置において、 シート抵抗が低い抵抗層上にシート抵抗が高い高抵抗層
を配置してなる薄膜抵抗体と、前記シート抵抗が高い高
抵抗層よりなる薄膜高抵抗体とにより、前記抵抗素子を
形成してなることを特徴とする薄膜抵抗体装置。
[Claims] 1. In a thin film resistor device in which thin film resistive elements having different resistance values are formed on an insulating film formed on the main surface of a semiconductor substrate in which an active element region is formed, sheet resistance is low. The resistance element is formed by a thin film resistor formed by disposing a high resistance layer having a high sheet resistance on a resistance layer, and a thin film high resistance object formed by the high resistance layer having a high sheet resistance. Thin film resistor device.
JP62039287A 1987-02-24 1987-02-24 Thin-film resistor device Pending JPS63207164A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62039287A JPS63207164A (en) 1987-02-24 1987-02-24 Thin-film resistor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62039287A JPS63207164A (en) 1987-02-24 1987-02-24 Thin-film resistor device

Publications (1)

Publication Number Publication Date
JPS63207164A true JPS63207164A (en) 1988-08-26

Family

ID=12548940

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62039287A Pending JPS63207164A (en) 1987-02-24 1987-02-24 Thin-film resistor device

Country Status (1)

Country Link
JP (1) JPS63207164A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02159756A (en) * 1988-12-14 1990-06-19 Nec Corp Thin film resistance element of tantalum

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6161450A (en) * 1984-09-03 1986-03-29 Oki Electric Ind Co Ltd Method for manufacturing semiconductor devices

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6161450A (en) * 1984-09-03 1986-03-29 Oki Electric Ind Co Ltd Method for manufacturing semiconductor devices

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02159756A (en) * 1988-12-14 1990-06-19 Nec Corp Thin film resistance element of tantalum

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