JPS62252965A - Thin film integrated device and manufacture thereof - Google Patents
Thin film integrated device and manufacture thereofInfo
- Publication number
- JPS62252965A JPS62252965A JP61097101A JP9710186A JPS62252965A JP S62252965 A JPS62252965 A JP S62252965A JP 61097101 A JP61097101 A JP 61097101A JP 9710186 A JP9710186 A JP 9710186A JP S62252965 A JPS62252965 A JP S62252965A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- resistor
- resistor layer
- layer
- semiconductor layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 54
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 10
- 239000010408 film Substances 0.000 claims abstract description 34
- 239000004065 semiconductor Substances 0.000 claims abstract description 32
- UHYPYGJEEGLRJD-UHFFFAOYSA-N cadmium(2+);selenium(2-) Chemical compound [Se-2].[Cd+2] UHYPYGJEEGLRJD-UHFFFAOYSA-N 0.000 claims abstract description 10
- 239000000463 material Substances 0.000 claims abstract description 10
- 238000000034 method Methods 0.000 claims abstract description 6
- 239000000758 substrate Substances 0.000 claims abstract description 6
- 230000010354 integration Effects 0.000 claims 1
- 229910052782 aluminium Inorganic materials 0.000 abstract description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract description 2
- 239000011521 glass Substances 0.000 abstract description 2
- 239000002131 composite material Substances 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 5
- 239000002184 metal Substances 0.000 description 5
- 229920002120 photoresistant polymer Polymers 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 239000011651 chromium Substances 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000007738 vacuum evaporation Methods 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- -1 alloys Chemical class 0.000 description 1
- 238000013459 approach Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- LIVNPJMFVYWSIS-UHFFFAOYSA-N silicon monoxide Chemical compound [Si-]#[O+] LIVNPJMFVYWSIS-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D86/00—Integrated devices formed in or on insulating or conducting substrates, e.g. formed in silicon-on-insulator [SOI] substrates or on stainless steel or glass substrates
Landscapes
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
この発明は、薄膜トランジスタ、薄膜抵抗等の複数個の
薄膜素子が集積されて成る薄膜集積装置に関する。DETAILED DESCRIPTION OF THE INVENTION Field of the Invention This invention relates to a thin film integrated device in which a plurality of thin film elements such as thin film transistors and thin film resistors are integrated.
従来の技術
従来、薄膜集積装置に用いられる抵抗体層としては、酸
化物と金属との複合膜がある。これはたとえば酸化シリ
コン（ＳｉＯ）とクロム（Ｃｒ）との複合膜などである
が、ＳｉＯとＣｒの分子比率を変化させて複合膜の比抵
抗を調節することが可能である。2. Description of the Related Art Conventionally, a composite film of oxide and metal has been used as a resistor layer used in a thin film integrated device. This is, for example, a composite film of silicon oxide (SiO) and chromium (Cr), and the resistivity of the composite film can be adjusted by changing the molecular ratio of SiO and Cr.
このほかにも、アルミニウム（Ａｅ）とタンタル（Ｔａ
）の合金のように金属同士の複合膜等もあり、さらに一
部を陽極酸化して、薄膜コンデンサを構成した薄膜集積
装置もある。In addition, aluminum (Ae) and tantalum (Ta)
) There are also composite films of metals such as alloys, and there are also thin film integrated devices in which a part of the capacitor is anodized to form a thin film capacitor.
発明が解決しようとする問題点
従来の薄膜集積装置では、薄膜トランジスタの半導体層
と薄膜抵抗の抵抗体層は、ちがう材料から構成されてお
り、たとえば半導体層を所定の形状にバターニングした
後、別の材料からなる抵抗体層を所定の形状にバターニ
ングするような場合には、前に形成した半導体層に対し
汚染等の影響を与えないように抵抗体層をバターニング
する必要があシ、製造工程において制約が生じるという
問題があった。Problems to be Solved by the Invention In conventional thin film integrated devices, the semiconductor layer of the thin film transistor and the resistor layer of the thin film resistor are made of different materials. When patterning a resistor layer made of a material into a predetermined shape, it is necessary to pattern the resistor layer so as not to affect the previously formed semiconductor layer by contamination or the like. There was a problem in that restrictions occurred in the manufacturing process.
また、抵抗体層として酸化物と金属との複合膜を用いた
場合には、一般に高い抵抗率を得ようとすれば酸化物の
分子比率を多くする必要がある。Further, when a composite film of an oxide and a metal is used as a resistor layer, it is generally necessary to increase the molecular ratio of the oxide in order to obtain a high resistivity.
このとき金属と酸素とが反応しやすくなり、抵抗値が変
わ９やずいという欠点があった。At this time, the metal and oxygen tend to react with each other, resulting in a change in resistance value of 9 mm.
上記した酸化物と金属との複合膜お金属同士の複合膜で
は高抵抗率のものは得がたく、高い抵抗値を得るために
は、薄膜抵抗の電極間の距離と抵抗体層の幅の比を十分
に大きくとる必要があシ、形状や寸法に制約が生ずると
いう問題があった。It is difficult to obtain a high resistivity with the above-mentioned composite films of oxides and metals, and in order to obtain high resistance values, it is necessary to adjust the distance between the electrodes of the thin film resistor and the width of the resistor layer. There is a problem in that the ratio needs to be sufficiently large, which creates restrictions on the shape and dimensions.
また、膜厚と抵抗率とはほぼ反比例の関係にあり、膜厚
をいくらうすくしても限度があシ、高抵抗率のものを得
るのは困難であった。Furthermore, the film thickness and resistivity are almost inversely proportional, and no matter how thin the film thickness is, there is a limit and it is difficult to obtain a film with high resistivity.
そこで本発明は、以上のような問題点を解決して、所望
の抵抗値を有する薄膜抵抗が容易に得られる薄膜集積装
置を提供することを目的としている。SUMMARY OF THE INVENTION An object of the present invention is to solve the above problems and provide a thin film integrated device in which a thin film resistor having a desired resistance value can be easily obtained.
問題点を解決するための手段
本発明の薄膜集積装置においては、絶縁性基板上に、少
なくとも、ドレイン電極、ソース電極。Means for Solving the Problems In the thin film integrated device of the present invention, at least a drain electrode and a source electrode are formed on an insulating substrate.
ゲート電極、ゲート絶縁膜および半導体層を有する薄膜
トランジスタおよび、少なくとも一対の電極および抵抗
体層を有する薄膜抵抗が構成されるとともに、前記半導
体層および抵抗体層が同一材料で構成され、前記抵抗体
層の膜厚が所望の抵抗値を得る値に設定されたことを特
徴とする。A thin film transistor having a gate electrode, a gate insulating film, and a semiconductor layer, and a thin film resistor having at least one pair of electrodes and a resistor layer are constructed, and the semiconductor layer and the resistor layer are made of the same material, and the resistor layer The film thickness is set to a value that provides a desired resistance value.
作 用
本発明によれば、抵抗体層が半導体層と同一の材料で構
成されているので、同様の工程で製造することができ、
製造装置を共用することができる。Function According to the present invention, since the resistor layer is made of the same material as the semiconductor layer, it can be manufactured in the same process.
Manufacturing equipment can be shared.
また、抵抗体層が半導体であるので、膜厚により抵抗率
が大きく変化し、広い範囲にわたって所望の抵抗値を得
ることができる。このため、専有面積の少ない薄膜抵抗
を構成することができ、薄膜集積装置の小型化が容易に
なる。Further, since the resistor layer is a semiconductor, the resistivity changes greatly depending on the film thickness, and a desired resistance value can be obtained over a wide range. Therefore, a thin film resistor can be constructed that occupies a small area, and the thin film integrated device can be easily miniaturized.
実施例
以下、本発明の実施例を添付図面にもとづいて説明する
。Embodiments Hereinafter, embodiments of the present invention will be described based on the accompanying drawings.
第１図は本発明の一実施例の薄膜集積装置の断面を示し
たものである。ガラス等の絶縁性基板１上に５０ ｎ
ｍ程度の膜厚を有するＡＩから成るゲート電極２、前記
ゲート電極２を被覆する３００ｎｍ程度の膜厚を有する
アルミナ（Ａｇ２Ｏ３）からなるゲート絶縁膜３、前記
ゲート絶縁膜３の上に５０ｎｍ穆度の膜厚を有するＣｄ
Ｓｅからなる半導体層４および２００ ｎ ｍ程度の膜
厚を有し同様にＣｄＳｅからなる抵抗体層５、前記半導
体層４および抵怨体層６の上に数〜数十ミクロンの所定
の間隔を隔てて１００ ｎ ｍ程度の膜厚を有するＡｌ
からなるソース電極６、ドレイン電極７および薄膜抵抗
の一対の電極８、電極９から構成されている。FIG. 1 shows a cross section of a thin film integrated device according to an embodiment of the present invention. 50 nm on an insulating substrate 1 made of glass etc.
A gate electrode 2 made of AI having a film thickness of about m, a gate insulating film 3 made of alumina (Ag2O3) having a film thickness of about 300 nm covering the gate electrode 2, and a 50 nm thick film on the gate insulating film 3. Cd with a film thickness of
A semiconductor layer 4 made of Se, a resistor layer 5 having a film thickness of about 200 nm and also made of CdSe, and a predetermined interval of several to several tens of microns above the semiconductor layer 4 and the resistor layer 6. Al with a film thickness of about 100 nm separated by
It consists of a source electrode 6, a drain electrode 7, and a pair of thin film resistor electrodes 8 and 9.
前記半導体層４および抵抗体層６の形成には、たとえば
７オリレジスト膜を用いたりフトオフ法等がある。すな
わち、フォトレジスト膜を前記ゲート絶縁膜３の上に全
面塗布形成した後、露光。The semiconductor layer 4 and the resistor layer 6 may be formed using, for example, a 7-way resist film, a foot-off method, or the like. That is, after a photoresist film is coated on the entire surface of the gate insulating film 3, it is exposed to light.
現像処理により半導体層４または抵抗体層５を付着する
領域のみの７オトレジスト膜を除去する。By development, the photoresist film 7 is removed only in the region where the semiconductor layer 4 or the resistor layer 5 is to be attached.
この後、全面にたとえばＣｄＳｅ等の半導体材料を真空
蒸着法などにより付着した後、７オトレジスト膜および
フォトレジスト膜上の半導体層または抵抗体層を除去す
る方法である。このように半導体層４と抵抗体層５は同
時に形成することができて、製造工程を大幅に短縮する
ことができる。Thereafter, a semiconductor material such as CdSe is deposited on the entire surface by vacuum evaporation, and then the semiconductor layer or resistor layer on the photoresist film and the photoresist film is removed. In this way, the semiconductor layer 4 and the resistor layer 5 can be formed simultaneously, and the manufacturing process can be significantly shortened.
従来、抵抗体層の抵抗率は一定であり、薄膜抵抗の形状
を変化させて所望の抵抗値を実現していた。しかしなが
ら面積等の制約のため、実現可能な抵抗値の幅に制限が
あった。本発明のポイントは、薄膜抵抗の抵抗体層が半
導体であれば、その膜厚に依存して、その抵抗率が大き
く変化することを見出したことに基づいている。以下こ
のことを詳細に説明する。Conventionally, the resistivity of the resistor layer was constant, and the desired resistance value was achieved by changing the shape of the thin film resistor. However, due to constraints such as area, there is a limit to the range of resistance values that can be realized. The point of the present invention is based on the discovery that if the resistor layer of a thin film resistor is a semiconductor, its resistivity changes greatly depending on its film thickness. This will be explained in detail below.
第２図は、一対の電極８および電極９の間の距離を１．
００μｍ、抵抗体層５の幅を５００μｍ一定として、膜
厚を変化させた時の薄膜抵抗の抵抗率を調べた結果であ
る。抵抗体層としてはＣｄ Ｓ ｅを用い、真空蒸着法
によシ形成した。図から明らかなように、膜厚を数倍す
ることにより、抵抗率は数千倍の範囲で変化し、所望の
抵抗値を有する薄膜抵抗を容易に得ることができる・；
したがって、微少面積中でも、所望の薄膜抵抗を構成す
ることができ、薄膜集積装置の微細化を促進することが
でき、設計の自由度が増すという特徴もかねそなえてい
る。In FIG. 2, the distance between a pair of electrodes 8 and 9 is set to 1.
00 μm, and the width of the resistor layer 5 was constant at 500 μm, and the resistivity of the thin film resistor was investigated when the film thickness was changed. The resistor layer was formed using CdSe by vacuum evaporation. As is clear from the figure, by increasing the film thickness several times, the resistivity changes over a range of several thousand times, making it easy to obtain a thin film resistor with a desired resistance value.
Therefore, a desired thin film resistor can be constructed even in a minute area, miniaturization of the thin film integrated device can be promoted, and the degree of freedom in design can be increased.
以上の例でも示したように、抵抗体層がポリシリコンや
ＣｄＳｅ のように多結晶半導体薄膜であれば、膜厚
によって結晶性が大きく変化するため、抵抗率をより大
きく変化させることができ、本発明による効果がさらに
大きくなる。As shown in the above examples, if the resistor layer is a polycrystalline semiconductor thin film such as polysilicon or CdSe, the crystallinity changes greatly depending on the film thickness, so the resistivity can be changed more greatly. The effects of the present invention are even greater.
第３図は２相の転送パルスにより入力パルスを順次転送
する薄膜集積装置の一例を示す回路図である。すなわち
、４個のＴ１〜Ｔ４ で示す薄膜トランジスタと２個
の薄膜抵抗Ｒ５，Ｒ６によシ、その基板ブロックが構成
されておシ、Ｔ１のソース電極とＴ２のゲート電極、Ｔ
２のドレイン電極とＲ５の一方の電極およびＴ３のドレ
イン電極、Ｔ３ノソース電極とＴ４のゲート電極、Ｔ４
ノドレイン電橿とＲ６の一方の電極をそれぞれ接続して
、次段の同様にして構成した基本ブロックに接続してい
る。この回路は、Ｔ１．Ｔ３のゲート電極にＣＫ１．Ｃ
Ｋ２の２相の転送パルスをそれぞれ印加してＴ１のドレ
イン電極に印加された入力パルス■ｘＮを順次転送して
いくダイナミックシフトレジスタを構成している。この
回路においてＡ点およびＢ点の電位は、Ｔ２またはＴ４
のゲート電極に印加された電圧により、たとえば、Ｔ２
１”４がＯＦＦの時には、０点、Ｄ点の電位であるＶＢ
の値暉近づき、Ｔ２１Ｔ４がＯＮの時には、ＥＡ、Ｆ点
の電位であるｖｏの値に近づく。この時、Ａ点。FIG. 3 is a circuit diagram showing an example of a thin film integrated device that sequentially transfers input pulses using two-phase transfer pulses. That is, the substrate block is composed of four thin film transistors T1 to T4 and two thin film resistors R5 and R6, a source electrode of T1, a gate electrode of T2, and a gate electrode of T2.
2 drain electrode, one electrode of R5, drain electrode of T3, T3 source electrode and gate electrode of T4, T4
The nodrain electric rod and one electrode of R6 are connected to each other and connected to the next stage basic block constructed in the same manner. This circuit has T1. CK1. to the gate electrode of T3. C
A dynamic shift register is constructed in which two-phase transfer pulses of K2 are applied to sequentially transfer input pulses xN applied to the drain electrode of T1. In this circuit, the potentials at points A and B are T2 or T4
For example, the voltage applied to the gate electrode of T2
When 1"4 is OFF, VB which is the potential of point 0 and point D
When T21 and T4 are ON, the value approaches the value of vo, which is the potential at points EA and F. At this time, point A.
Ｂ点の電位の振幅を大きくするには・Ｒ６・Ｒ６の抵抗
値と、Ｔ２．Ｔ４のＯＦＦ時または、０８時の抵抗値の
比の値を大きくする必要がある。したがって、Ｒ５，Ｒ
６の抵抗体層と、Ｔ２．Ｔ４の半導体層を同一材料で構
成すれば、それぞれの膜厚をかえるだけで任意の抵抗値
の比を得ることができる。Ｔ２．Ｔ４ の特性は、製造
工程によシ所望の値から多少ずれることがしばしばある
がＲ５゜Ｒ６の材料が同一であれば同様に特性が変化す
るため、抵抗値の比を常に一定に保つことができ、薄膜
集積装置の動作を正確に行なうことができる。To increase the amplitude of the potential at point B, the resistance values of R6 and R6 and T2. It is necessary to increase the ratio of the resistance values when T4 is OFF or when T4 is 08. Therefore, R5,R
6 resistor layer, and T2.6 resistor layer. If the semiconductor layers T4 are made of the same material, any resistance value ratio can be obtained by simply changing the thickness of each layer. T2. The characteristics of T4 often deviate from the desired value due to the manufacturing process, but if the materials of R5 and R6 are the same, the characteristics will change in the same way, so it is possible to always keep the ratio of resistance values constant. Therefore, the thin film integrated device can be operated accurately.
発明の効果
本発明によれば、薄膜集積装置中の薄膜抵抗を容易に構
成することかで′き、所望の抵抗値を簡単に得ることが
できる。また、薄膜抵抗の専有面積を最小にすることが
でき、各種薄膜集積装置に広く利用できるものである。Effects of the Invention According to the present invention, a thin film resistor in a thin film integrated device can be easily configured, and a desired resistance value can be easily obtained. Furthermore, the area occupied by the thin film resistor can be minimized, and it can be widely used in various thin film integrated devices.
第１図は本発明の一実施例の薄膜集積装置の断面図、第
２図は抵抗体層の膜厚を変化させた時の薄膜抵抗の抵抗
率を示すグラフ、第３図は本発明の他の実施例である薄
膜集積装置の回路図である。
４・・・・・−半導体層、６・・−・・・抵抗体層・代
理人の氏名 弁理士 中 尾 敏 男 ほか１名第１図
澗」曵トランジスタ
２７′−ト１１不色
第２図FIG. 1 is a cross-sectional view of a thin film integrated device according to an embodiment of the present invention, FIG. 2 is a graph showing the resistivity of a thin film resistor when the film thickness of the resistor layer is changed, and FIG. FIG. 7 is a circuit diagram of a thin film integrated device according to another embodiment. 4...-Semiconductor layer, 6...-Resistor layer/Name of agent Patent attorney Toshi Nakao and one other person figure
Claims (6)
ース電極、ゲート電極、ゲート絶縁膜および半導体層を
有する薄膜トランジスタ、および、少なくとも一対の電
極および抵抗体層を有する薄膜抵抗が構成されるととも
に、前記半導体層および抵抗体層が同一材料で構成され
、前記抵抗体層の膜厚が所望の抵抗値を得る値に設定さ
れたことを特徴とする薄膜集積装置。(1) A thin film transistor having at least a drain electrode, a source electrode, a gate electrode, a gate insulating film, and a semiconductor layer, and a thin film resistor having at least one pair of electrodes and a resistor layer are formed on an insulating substrate, and A thin film integrated device, wherein the semiconductor layer and the resistor layer are made of the same material, and the thickness of the resistor layer is set to a value that provides a desired resistance value.
成されていることを特徴とする特許請求の範囲第１項記
載の薄膜集積装置。(2) The thin film integrated device according to claim 1, wherein the semiconductor layer and the resistor layer are composed of polycrystalline semiconductor thin films.
ｅ）で構成されていることを特徴とする特許請求の範囲
第２項記載の薄膜集積装置。(3) Polycrystalline semiconductor thin film made of cadmium selenide (CdS)
3. The thin film integration device according to claim 2, characterized in that it is comprised of e).
ース電極、ゲート電極、ゲート絶縁膜および半導体層を
有する薄膜トランジスタ、および、少なくとも一対の電
極および抵抗体層を有する薄膜抵抗を構成し、前記半導
体層および抵抗体層を同一材料で構成するとともに、前
記抵抗体層の膜厚を変化させて所望の抵抗値を得ること
を特徴とする薄膜集積装置の製造方法。(4) A thin film transistor having at least a drain electrode, a source electrode, a gate electrode, a gate insulating film, and a semiconductor layer, and a thin film resistor having at least one pair of electrodes and a resistor layer are formed on an insulating substrate, and the semiconductor A method for manufacturing a thin film integrated device, characterized in that the resistor layer and the resistor layer are made of the same material, and the thickness of the resistor layer is varied to obtain a desired resistance value.
成することを特徴とする特許請求の範囲第４項記載の薄
膜集積装置の製造方法。(5) A method for manufacturing a thin film integrated device according to claim 4, wherein the semiconductor layer and the resistor layer are formed of polycrystalline semiconductor thin films.
ｅ）で構成することを特徴とする特許請求の範囲第４項
記載の薄膜集積装置の製造方法。(6) Polycrystalline semiconductor thin film made of cadmium selenide (CdS)
5. The method for manufacturing a thin film integrated device according to claim 4, comprising step e).
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61097101A JPS62252965A (en) | 1986-04-25 | 1986-04-25 | Thin film integrated device and manufacture thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61097101A JPS62252965A (en) | 1986-04-25 | 1986-04-25 | Thin film integrated device and manufacture thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62252965A true JPS62252965A (en) | 1987-11-04 |
Family
ID=14183222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61097101A Pending JPS62252965A (en) | 1986-04-25 | 1986-04-25 | Thin film integrated device and manufacture thereof |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62252965A (en) |
-
1986
- 1986-04-25 JP JP61097101A patent/JPS62252965A/en active Pending
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