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JPS614261A - 集積回路装置 - Google Patents

集積回路装置

Info

Publication number
JPS614261A
JPS614261A JP59126107A JP12610784A JPS614261A JP S614261 A JPS614261 A JP S614261A JP 59126107 A JP59126107 A JP 59126107A JP 12610784 A JP12610784 A JP 12610784A JP S614261 A JPS614261 A JP S614261A
Authority
JP
Japan
Prior art keywords
lead terminal
mold
integrated circuit
terminal
bending
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59126107A
Other languages
English (en)
Inventor
Mamoru Sato
護 佐藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP59126107A priority Critical patent/JPS614261A/ja
Publication of JPS614261A publication Critical patent/JPS614261A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49541—Geometry of the lead-frame
    • H01L23/49548—Cross section geometry
    • H01L23/49551—Cross section geometry characterised by bent parts
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
    • H01L2224/45001—Core members of the connector
    • H01L2224/45099—Material
    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/45144—Gold (Au) as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/484—Connecting portions
    • H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
    • H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01079—Gold [Au]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Geometry (AREA)
  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 （産業上の利用分野） 本発明は集積回路装置のリード端子取り出し方式の改良
に関する。
（従来技術） 従来の集積回路装置のリード端子取り出し方式はモール
ド中央部ニジ取り出し、プリント基板等に取り付ける為
、リード端子部に曲げ加工を加えている。
例えば第２図においてリードフレーム５に取シ付けられ
た集積回路のペレット４（以下、ペレットと呼ぶ）は金
線等の金属線３により外部リード１．端子２と゛接続さ
れ、モールド部ｌの中央部より外部リード端子２として
外部へ引き出されている。
外部リード端子２はプリント基板等に接続する為曲げ加
工をほどこしである。
（発明が解決しようとする問題点） 従来の外部リード取シ出し方式では、取シ扱いによって
は外部リード端子の曲り等を生じ、プリント基板等に実
装する際、リードを修正しなければならないという欠点
があった。
本発明の目的はこれらの欠点を改良し取り扱いによって
外部リード端子の曲シ等を生じない集積回路装置を提供
することにある。
゛　　（問題点を解決するための手段）本発明は集積回
路のリード端子會モールド内部で曲げかつモールド下部
より引き出すことを特徴とする。
本発明によれば外部リード端子の取り扱いＫよる曲りな
どは生ぜず、かつプリント基板等に接続する時に外部リ
ード端子の位置を精度よく出すことができる。
（実施例） 次に、本発明の一実施例を第１図によって説明する。同
図において、リードフレーム１０に載置されたペレット
９は金線等の金属ＩＪ８により外部リード端子７と接続
されている。外部リード端子７はモールド６内部におい
て曲げ加工がされておシかつモールド６の下部より外部
に引き出されている。このようにして外部に取シ出され
たリード端子７は極めて曲げ等の変形に強く、従来のリ
ード端子取り出し方式にくらベリード端子の位置精度が
向上するという利点をもっている。
（発明の効果） 本発明によりブリント基板等へ実装する際リード曲シ等
の問題を解決し実装方式の大巾な歩留向上が期待できる
。
【図面の簡単な説明】
第１図は本発明の一実施例による集積回路装置の断面図
、第２図は従来の集積回路装置の断面図である。 １・・・・・・モールド部、２・・・・・・外部リード
端子、３・・・・・・金線等の金属線、４・・・・・・
集積回路ペレット、５・・・・・・リードフレーム、６
・旧・・モールｈ”部、　　７・・・・・・外部リード
端子、８・・・・・・金線等の金属線、９・・・・・・
集積回路ペレット、１０・・・・・・リードフレーム。

Claims (1)

    【特許請求の範囲】
  1. 集積回路装置のリード端子をモールド内部で曲げかつモ
    ールド下部より引き出すことを特徴とする集積回路装置
    。
JP59126107A 1984-06-19 1984-06-19 集積回路装置 Pending JPS614261A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59126107A JPS614261A (ja) 1984-06-19 1984-06-19 集積回路装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59126107A JPS614261A (ja) 1984-06-19 1984-06-19 集積回路装置

Publications (1)

Publication Number Publication Date
JPS614261A true JPS614261A (ja) 1986-01-10

Family

ID=14926791

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59126107A Pending JPS614261A (ja) 1984-06-19 1984-06-19 集積回路装置

Country Status (1)

Country Link
JP (1) JPS614261A (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0623954A1 (en) * 1993-05-07 1994-11-09 AT&T Corp. Molded plastic packaging of electronic devices
US5508557A (en) * 1992-10-09 1996-04-16 Rohm Co., Ltd. Surface mounting type diode

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5508557A (en) * 1992-10-09 1996-04-16 Rohm Co., Ltd. Surface mounting type diode
US5625223A (en) * 1992-10-09 1997-04-29 Rohm Co., Ltd. Surface mounting type diode
EP0623954A1 (en) * 1993-05-07 1994-11-09 AT&T Corp. Molded plastic packaging of electronic devices
US5548087A (en) * 1993-05-07 1996-08-20 At&T Corp. Molded plastic packaging of electronic devices

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