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JPS5789175A - Data processing control system - Google Patents

Data processing control system

Info

Publication number
JPS5789175A
JPS5789175A JP55166164A JP16616480A JPS5789175A JP S5789175 A JPS5789175 A JP S5789175A JP 55166164 A JP55166164 A JP 55166164A JP 16616480 A JP16616480 A JP 16616480A JP S5789175 A JPS5789175 A JP S5789175A
Authority
JP
Japan
Prior art keywords
timing
inputted
circuit
processing circuit
addition processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP55166164A
Other languages
Japanese (ja)
Other versions
JPS6058503B2 (en
Inventor
Keiichiro Uchida
Hiroshi Tamura
Tetsuo Okamoto
Shigeaki Okuya
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP55166164A priority Critical patent/JPS6058503B2/en
Priority to KR1019810004304A priority patent/KR860001434B1/en
Priority to AU77596/81A priority patent/AU533634B2/en
Priority to US06/322,717 priority patent/US4435765A/en
Priority to ES507355A priority patent/ES8302333A1/en
Priority to BR8107582A priority patent/BR8107582A/en
Priority to CA000390501A priority patent/CA1175576A/en
Priority to DE8181305481T priority patent/DE3169741D1/en
Priority to EP81305481A priority patent/EP0053457B1/en
Publication of JPS5789175A publication Critical patent/JPS5789175A/en
Publication of JPS6058503B2 publication Critical patent/JPS6058503B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead

Landscapes

  • Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Advance Control (AREA)
  • Complex Calculations (AREA)

Abstract

PURPOSE:To access an element, by prescribing a timing for accessing an element of a vector register of each bank, providing a controlling circuit for controlling whether the prescribed timing is used or not, and selecting the prescribed timing. CONSTITUTION:From the center of the first and second bits and the center of the fourth and fifth bits of a shift register 20, the respective outputs are inputted to an addition register 20, the respective outputs are inputted to an addition processing circuit 22 and a multiplication processing circuit 23. On the other hand, an output of a decoder 21 which has received an instruction as an input is also inputted to the circuit 22 and 23. Also, outputs of use displaying circuit 26, 27 of timings ABC, DEF are inputted to the circuits 22, 23, respectively. For instance, the addition processing circuit 22 detects that the ABC timing is being used and the DEG timing is unused, and if the next instruction inputted to the decoder 21 is an adding instruction, its adding instruction is received by the addition processing circuit 22, and the addition processing is started by the DEF timing.
JP55166164A 1980-11-21 1980-11-26 Data processing control method Expired JPS6058503B2 (en)

Priority Applications (9)

Application Number Priority Date Filing Date Title
JP55166164A JPS6058503B2 (en) 1980-11-26 1980-11-26 Data processing control method
KR1019810004304A KR860001434B1 (en) 1980-11-21 1981-11-10 Bank interleaved vector processor having a fixed relationship between start timing signals
AU77596/81A AU533634B2 (en) 1980-11-21 1981-11-18 Data processing system
US06/322,717 US4435765A (en) 1980-11-21 1981-11-18 Bank interleaved vector processor having a fixed relationship between start timing signals
ES507355A ES8302333A1 (en) 1980-11-21 1981-11-20 Data processing apparatus.
BR8107582A BR8107582A (en) 1980-11-21 1981-11-20 DATA PROCESSING SYSTEM
CA000390501A CA1175576A (en) 1980-11-21 1981-11-20 Data processing system for vector operations
DE8181305481T DE3169741D1 (en) 1980-11-21 1981-11-20 Data processing apparatus
EP81305481A EP0053457B1 (en) 1980-11-21 1981-11-20 Data processing apparatus

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55166164A JPS6058503B2 (en) 1980-11-26 1980-11-26 Data processing control method

Publications (2)

Publication Number Publication Date
JPS5789175A true JPS5789175A (en) 1982-06-03
JPS6058503B2 JPS6058503B2 (en) 1985-12-20

Family

ID=15826256

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55166164A Expired JPS6058503B2 (en) 1980-11-21 1980-11-26 Data processing control method

Country Status (1)

Country Link
JP (1) JPS6058503B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59174975A (en) * 1983-03-25 1984-10-03 Fujitsu Ltd Register access control system
JPS61269774A (en) * 1985-05-24 1986-11-29 Fujitsu Ltd Vector instruction executing and controlling system

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63158404U (en) * 1987-04-03 1988-10-18

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59174975A (en) * 1983-03-25 1984-10-03 Fujitsu Ltd Register access control system
JPH0348549B2 (en) * 1983-03-25 1991-07-24 Fujitsu Ltd
JPS61269774A (en) * 1985-05-24 1986-11-29 Fujitsu Ltd Vector instruction executing and controlling system
JPH0477945B2 (en) * 1985-05-24 1992-12-09 Fujitsu Ltd

Also Published As

Publication number Publication date
JPS6058503B2 (en) 1985-12-20

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