JPS5789174A - Data processing control system - Google Patents

Abstract

PURPOSE:To place consecutive elements of a vector register in sequence of corresponding banks, also to prescribe a timing for accessing an element, and to initialize its prescription to an optional timing. CONSTITUTION:A processing instruction is inputted to a decoder 21, and an output of the decoder 21 is inputted to a setting logical circuit 22. To the circuit 22, an output of a controlling circuit 24 is inputted through a resetting logical circuit 23. An output of the circuit 22 is made to branch to 4, and each of them is inputted to A, D, G and H, that is to say, the first, fourth, seventh and eighth bits of a shift register 20. The controlling circuit 24 always controls an access state of a vector register, and when an idle access is detected, it is informed to the resetting logical circuit 23. The resetting circuit 23 which has received the information resets all the bits of the shift register 20, and also presses the setting logical circuit 22 to set the prescription again. The setting logical circuit 22 reads the contents by an output of the decoder 21 to which the instruction has been inputted.