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JPS57105019A - Data transfer controlling system - Google Patents

Data transfer controlling system

Info

Publication number
JPS57105019A
JPS57105019A JP18151680A JP18151680A JPS57105019A JP S57105019 A JPS57105019 A JP S57105019A JP 18151680 A JP18151680 A JP 18151680A JP 18151680 A JP18151680 A JP 18151680A JP S57105019 A JPS57105019 A JP S57105019A
Authority
JP
Japan
Prior art keywords
transfer
data transfer
byte
controller
designated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18151680A
Other languages
Japanese (ja)
Inventor
Yutaka Haruna
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP18151680A priority Critical patent/JPS57105019A/en
Publication of JPS57105019A publication Critical patent/JPS57105019A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE:To efficiently control a data transfer, by executing a direct memory access transfer between a data transfer memory of a byte transfer or a word transfer so as to correspond to each channel, and an input/output device. CONSTITUTION:A latching circuit 18 of 4 bits designates a byte and a wood for direct memory access DMA transfer, and designates it independently of the respective 4 channels being under the control of a DMA controller 11. In case when a byte transfer has been designated by the circuit 18, the controller 11 increases contents of its internal address register by +1 each. On the other band, in case when a word transfer has been designated, if the address register in the controller 11 is increased by +1 each, address signals AD1-AD15 which have been increased by +2 each are sent out to an address bus ADR from a 3-state buffer 13.
JP18151680A 1980-12-22 1980-12-22 Data transfer controlling system Pending JPS57105019A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18151680A JPS57105019A (en) 1980-12-22 1980-12-22 Data transfer controlling system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18151680A JPS57105019A (en) 1980-12-22 1980-12-22 Data transfer controlling system

Publications (1)

Publication Number Publication Date
JPS57105019A true JPS57105019A (en) 1982-06-30

Family

ID=16102116

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18151680A Pending JPS57105019A (en) 1980-12-22 1980-12-22 Data transfer controlling system

Country Status (1)

Country Link
JP (1) JPS57105019A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59178523A (en) * 1983-03-30 1984-10-09 Fujitsu Ltd DMA control method
JPS62179664U (en) * 1987-04-24 1987-11-14
US5208915A (en) * 1982-11-09 1993-05-04 Siemens Aktiengesellschaft Apparatus for the microprogram control of information transfer and a method for operating the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54142950A (en) * 1978-04-28 1979-11-07 Toshiba Corp Data transfer system

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS54142950A (en) * 1978-04-28 1979-11-07 Toshiba Corp Data transfer system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5208915A (en) * 1982-11-09 1993-05-04 Siemens Aktiengesellschaft Apparatus for the microprogram control of information transfer and a method for operating the same
JPS59178523A (en) * 1983-03-30 1984-10-09 Fujitsu Ltd DMA control method
JPS62179664U (en) * 1987-04-24 1987-11-14

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